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4225a882 | 1 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
2 | * @file irsnd.c\r | |
3 | *\r | |
08f2dd9d | 4 | * Copyright (c) 2010-2012 Frank Meyer - frank(at)fli4l.de\r |
4225a882 | 5 | *\r |
7644ac04 | 6 | * Supported mikrocontrollers:\r |
7 | *\r | |
21a4e0ee | 8 | * ATtiny87, ATtiny167\r |
476267f4 | 9 | * ATtiny45, ATtiny85\r |
10 | * ATtiny84\r | |
7644ac04 | 11 | * ATmega8, ATmega16, ATmega32\r |
12 | * ATmega162\r | |
13 | * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284\r | |
14 | * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r | |
15 | *\r | |
21a4e0ee | 16 | * $Id: irsnd.c,v 1.59 2012/06/18 09:00:46 fm Exp $\r |
5481e9cd | 17 | *\r |
4225a882 | 18 | * This program is free software; you can redistribute it and/or modify\r |
19 | * it under the terms of the GNU General Public License as published by\r | |
20 | * the Free Software Foundation; either version 2 of the License, or\r | |
21 | * (at your option) any later version.\r | |
22 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
23 | */\r | |
24 | \r | |
4225a882 | 25 | #include "irsnd.h"\r |
26 | \r | |
1f54e86c | 27 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
28 | * ATtiny pin definition of OC0A / OC0B\r | |
29 | * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B\r | |
30 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
31 | */\r | |
08f2dd9d | 32 | #if defined (__AVR_ATtiny84__) // ATtiny84 uses OC0A = PB2 or OC0B = PA7\r |
33 | # if IRSND_OCx == IRSND_OC0A // OC0A\r | |
34 | # define IRSND_PORT PORTB // port B\r | |
35 | # define IRSND_DDR DDRB // ddr B\r | |
36 | # define IRSND_BIT 2 // OC0A\r | |
37 | # elif IRSND_OCx == IRSND_OC0B // OC0B\r | |
38 | # define IRSND_PORT PORTA // port A\r | |
39 | # define IRSND_DDR DDRA // ddr A\r | |
40 | # define IRSND_BIT 7 // OC0B\r | |
41 | # else\r | |
42 | # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r | |
43 | # endif // IRSND_OCx\r | |
44 | #elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1\r | |
45 | # if IRSND_OCx == IRSND_OC0A // OC0A\r | |
46 | # define IRSND_PORT PORTB // port B\r | |
47 | # define IRSND_DDR DDRB // ddr B\r | |
48 | # define IRSND_BIT 0 // OC0A\r | |
49 | # elif IRSND_OCx == IRSND_OC0B // OC0B\r | |
50 | # define IRSND_PORT PORTB // port B\r | |
51 | # define IRSND_DDR DDRB // ddr B\r | |
52 | # define IRSND_BIT 1 // OC0B\r | |
53 | # else\r | |
54 | # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r | |
55 | # endif // IRSND_OCx\r | |
21a4e0ee | 56 | #elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2\r |
90387f65 | 57 | # if IRSND_OCx == IRSND_OC0A // OC0A\r |
58 | # define IRSND_PORT PORTA // port A\r | |
59 | # define IRSND_DDR DDRA // ddr A\r | |
60 | # define IRSND_BIT 2 // OC0A\r | |
61 | # else\r | |
62 | # error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h\r | |
63 | # endif // IRSND_OCx\r | |
08f2dd9d | 64 | #elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3\r |
65 | # if IRSND_OCx == IRSND_OC2 // OC0A\r | |
66 | # define IRSND_PORT PORTB // port B\r | |
67 | # define IRSND_DDR DDRB // ddr B\r | |
68 | # define IRSND_BIT 3 // OC0A\r | |
69 | # else\r | |
70 | # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r | |
71 | # endif // IRSND_OCx\r | |
72 | #elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC2 = PD7\r | |
73 | # if IRSND_OCx == IRSND_OC2 // OC2\r | |
74 | # define IRSND_PORT PORTD // port D\r | |
75 | # define IRSND_DDR DDRD // ddr D\r | |
76 | # define IRSND_BIT 7 // OC2\r | |
77 | # else\r | |
78 | # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r | |
79 | # endif // IRSND_OCx\r | |
80 | #elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0\r | |
81 | # if IRSND_OCx == IRSND_OC2 // OC2\r | |
82 | # define IRSND_PORT PORTB // port B\r | |
83 | # define IRSND_DDR DDRB // ddr B\r | |
84 | # define IRSND_BIT 1 // OC2\r | |
85 | # elif IRSND_OCx == IRSND_OC0 // OC0\r | |
86 | # define IRSND_PORT PORTB // port B\r | |
87 | # define IRSND_DDR DDRB // ddr B\r | |
88 | # define IRSND_BIT 0 // OC0\r | |
89 | # else\r | |
90 | # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r | |
91 | # endif // IRSND_OCx\r | |
f50e01e7 | 92 | #elif defined (__AVR_ATmega164__) \\r |
93 | || defined (__AVR_ATmega324__) \\r | |
94 | || defined (__AVR_ATmega644__) \\r | |
95 | || defined (__AVR_ATmega644P__) \\r | |
0f700c8e | 96 | || defined (__AVR_ATmega1284__) \\r |
08f2dd9d | 97 | || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4\r |
98 | # if IRSND_OCx == IRSND_OC2A // OC2A\r | |
99 | # define IRSND_PORT PORTD // port D\r | |
100 | # define IRSND_DDR DDRD // ddr D\r | |
101 | # define IRSND_BIT 7 // OC2A\r | |
102 | # elif IRSND_OCx == IRSND_OC2B // OC2B\r | |
103 | # define IRSND_PORT PORTD // port D\r | |
104 | # define IRSND_DDR DDRD // ddr D\r | |
105 | # define IRSND_BIT 6 // OC2B\r | |
106 | # elif IRSND_OCx == IRSND_OC0A // OC0A\r | |
107 | # define IRSND_PORT PORTB // port B\r | |
108 | # define IRSND_DDR DDRB // ddr B\r | |
109 | # define IRSND_BIT 3 // OC0A\r | |
110 | # elif IRSND_OCx == IRSND_OC0B // OC0B\r | |
111 | # define IRSND_PORT PORTB // port B\r | |
112 | # define IRSND_DDR DDRB // ddr B\r | |
113 | # define IRSND_BIT 4 // OC0B\r | |
114 | # else\r | |
115 | # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r | |
116 | # endif // IRSND_OCx\r | |
f50e01e7 | 117 | #elif defined (__AVR_ATmega48__) \\r |
118 | || defined (__AVR_ATmega88__) \\r | |
7644ac04 | 119 | || defined (__AVR_ATmega88P__) \\r |
f50e01e7 | 120 | || defined (__AVR_ATmega168__) \\r |
1f54e86c | 121 | || defined (__AVR_ATmega168P__) \\r |
08f2dd9d | 122 | || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5\r |
123 | # if IRSND_OCx == IRSND_OC2A // OC2A\r | |
124 | # define IRSND_PORT PORTB // port B\r | |
125 | # define IRSND_DDR DDRB // ddr B\r | |
126 | # define IRSND_BIT 3 // OC2A\r | |
127 | # elif IRSND_OCx == IRSND_OC2B // OC2B\r | |
128 | # define IRSND_PORT PORTD // port D\r | |
129 | # define IRSND_DDR DDRD // ddr D\r | |
130 | # define IRSND_BIT 3 // OC2B\r | |
131 | # elif IRSND_OCx == IRSND_OC0A // OC0A\r | |
132 | # define IRSND_PORT PORTB // port B\r | |
133 | # define IRSND_DDR DDRB // ddr B\r | |
134 | # define IRSND_BIT 6 // OC0A\r | |
135 | # elif IRSND_OCx == IRSND_OC0B // OC0B\r | |
136 | # define IRSND_PORT PORTD // port D\r | |
137 | # define IRSND_DDR DDRD // ddr D\r | |
138 | # define IRSND_BIT 5 // OC0B\r | |
139 | # else\r | |
140 | # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r | |
141 | # endif // IRSND_OCx\r | |
0f700c8e | 142 | #elif defined (__AVR_ATmega8515__) \r |
08f2dd9d | 143 | # if IRSND_OCx == IRSND_OC0 \r |
144 | # define IRSND_PORT PORTB // port B\r | |
145 | # define IRSND_DDR DDRB // ddr B\r | |
146 | # define IRSND_BIT 0 // OC0\r | |
147 | # elif IRSND_OCx == IRSND_OC1A \r | |
148 | # define IRSND_PORT PORTD // port D\r | |
149 | # define IRSND_DDR DDRD // ddr D\r | |
150 | # define IRSND_BIT 5 // OC1A\r | |
151 | # elif IRSND_OCx == IRSND_OC1B \r | |
152 | # define IRSND_PORT PORTE // port E\r | |
153 | # define IRSND_DDR DDRE // ddr E\r | |
154 | # define IRSND_BIT 2 // OC1E\r | |
155 | # else\r | |
156 | # error Wrong value for IRSND_OCx, choose IRSND_OC0, IRSND_OC1A, or IRSND_OC1B in irsndconfig.h\r | |
157 | # endif // IRSND_OCx\r | |
9c86ff1a | 158 | #elif defined (PIC_C18) //Microchip C18 compiler\r |
159 | //Nothing here to do here -> See irsndconfig.h\r | |
08f2dd9d | 160 | #elif defined (ARM_STM32) //STM32\r |
161 | //Nothing here to do here -> See irsndconfig.h\r | |
f50e01e7 | 162 | #else\r |
08f2dd9d | 163 | # if !defined (unix) && !defined (WIN32)\r |
164 | # error mikrocontroller not defined, please fill in definitions here.\r | |
165 | # endif // unix, WIN32\r | |
f50e01e7 | 166 | #endif // __AVR...\r |
167 | \r | |
9405f84a | 168 | #if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r |
9c86ff1a | 169 | typedef uint16_t IRSND_PAUSE_LEN;\r |
9405f84a | 170 | #else\r |
9c86ff1a | 171 | typedef uint8_t IRSND_PAUSE_LEN;\r |
9405f84a | 172 | #endif\r |
173 | \r | |
f50e01e7 | 174 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
175 | * IR timings\r | |
176 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
177 | */\r | |
4225a882 | 178 | #define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)\r |
179 | #define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)\r | |
180 | #define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)\r | |
181 | #define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)\r | |
182 | #define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)\r | |
a7054daf | 183 | #define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
184 | #define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
4225a882 | 185 | \r |
186 | #define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)\r | |
187 | #define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)\r | |
a7054daf | 188 | #define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r |
4225a882 | 189 | #define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)\r |
190 | #define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)\r | |
191 | #define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 192 | #define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 193 | \r |
194 | #define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)\r | |
195 | #define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)\r | |
196 | #define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)\r | |
197 | #define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)\r | |
198 | #define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 199 | #define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 200 | \r |
a7054daf | 201 | #define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
202 | #define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
5b437ff6 | 203 | \r |
4225a882 | 204 | #define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)\r |
205 | #define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)\r | |
206 | #define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)\r | |
207 | #define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)\r | |
208 | #define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 209 | #define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 210 | \r |
770a1a9d | 211 | #define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)\r |
212 | #define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)\r | |
213 | #define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)\r | |
214 | #define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)\r | |
215 | #define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)\r | |
216 | #define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r | |
217 | #define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
218 | \r | |
4225a882 | 219 | #define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)\r |
220 | #define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)\r | |
221 | #define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)\r | |
222 | #define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)\r | |
223 | #define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 224 | #define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 225 | \r |
226 | #define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r | |
227 | #define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r | |
a7054daf | 228 | #define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 229 | \r |
230 | #define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)\r | |
231 | #define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)\r | |
232 | #define RC6_TOGGLE_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_TOGGLE_BIT_TIME + 0.5)\r | |
233 | #define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)\r | |
a7054daf | 234 | #define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 235 | \r |
236 | #define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)\r | |
237 | #define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)\r | |
238 | #define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 239 | #define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
240 | #define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
4225a882 | 241 | \r |
beda975f | 242 | #define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)\r |
243 | #define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)\r | |
244 | #define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)\r | |
245 | #define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r | |
246 | #define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
247 | \r | |
4225a882 | 248 | #define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)\r |
249 | #define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)\r | |
250 | #define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)\r | |
251 | #define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)\r | |
252 | #define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 253 | #define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
4225a882 | 254 | \r |
255 | #define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)\r | |
256 | #define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)\r | |
257 | #define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)\r | |
258 | #define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)\r | |
259 | #define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)\r | |
260 | #define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)\r | |
a7054daf | 261 | #define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
262 | #define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
4225a882 | 263 | \r |
5481e9cd | 264 | #define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)\r |
265 | #define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)\r | |
266 | #define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)\r | |
267 | #define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)\r | |
268 | #define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)\r | |
269 | #define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)\r | |
270 | #define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)\r | |
271 | #define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)\r | |
272 | #define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)\r | |
273 | #define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)\r | |
274 | #define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)\r | |
a7054daf | 275 | #define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
5481e9cd | 276 | \r |
9c86ff1a | 277 | #define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)\r |
278 | #define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)\r | |
a7054daf | 279 | #define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
280 | #define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r | |
89e8cafb | 281 | #define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
a7054daf | 282 | \r |
a48187fa | 283 | #define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r |
284 | \r | |
02ccdb69 | 285 | #define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r |
286 | #define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r | |
287 | #define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
5b437ff6 | 288 | \r |
9c86ff1a | 289 | \r |
08f2dd9d | 290 | #ifdef PIC_C18 // PIC C18\r |
291 | # define IRSND_FREQ_TYPE uint8_t\r | |
292 | # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
293 | # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
294 | # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
295 | # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
296 | # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
297 | # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
298 | # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r | |
299 | #elif defined (ARM_STM32) // STM32\r | |
300 | # define IRSND_FREQ_TYPE uint32_t\r | |
301 | # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r | |
302 | # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r | |
303 | # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r | |
304 | # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r | |
305 | # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r | |
306 | # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r | |
307 | # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r | |
308 | #else // AVR\r | |
309 | # define IRSND_FREQ_TYPE uint8_t\r | |
310 | # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2) - 1)\r | |
311 | # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2) - 1)\r | |
312 | # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2) - 1)\r | |
313 | # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2) - 1)\r | |
314 | # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2) - 1)\r | |
315 | # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2) - 1)\r | |
316 | # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2) - 1)\r | |
9c86ff1a | 317 | #endif\r |
4225a882 | 318 | \r |
48664931 | 319 | #define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)\r |
320 | #define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)\r | |
321 | #define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)\r | |
322 | #define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)\r | |
323 | #define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)\r | |
324 | #define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
b5ea7869 | 325 | \r |
c7c9a4a1 | 326 | #define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)\r |
327 | #define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)\r | |
328 | #define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)\r | |
329 | #define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)\r | |
330 | #define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)\r | |
331 | #define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
332 | \r | |
c7a47e89 | 333 | #define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)\r |
334 | #define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)\r | |
335 | #define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r | |
336 | #define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)\r | |
337 | #define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)\r | |
338 | #define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)\r | |
339 | #define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
340 | \r | |
9405f84a | 341 | #define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)\r |
342 | #define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)\r | |
343 | #define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r | |
344 | #define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)\r | |
345 | #define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)\r | |
346 | #define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)\r | |
f50e01e7 | 347 | #define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r |
348 | \r | |
349 | #define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)\r | |
350 | #define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)\r | |
351 | #define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r | |
352 | #define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)\r | |
353 | #define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)\r | |
354 | #define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)\r | |
355 | #define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r | |
9405f84a | 356 | \r |
9c86ff1a | 357 | static volatile uint8_t irsnd_busy = 0;\r |
358 | static volatile uint8_t irsnd_protocol = 0;\r | |
359 | static volatile uint8_t irsnd_buffer[6] = {0};\r | |
360 | static volatile uint8_t irsnd_repeat = 0;\r | |
4225a882 | 361 | static volatile uint8_t irsnd_is_on = FALSE;\r |
362 | \r | |
f50e01e7 | 363 | #if IRSND_USE_CALLBACK == 1\r |
364 | static void (*irsnd_callback_ptr) (uint8_t);\r | |
365 | #endif // IRSND_USE_CALLBACK == 1\r | |
366 | \r | |
4225a882 | 367 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
368 | * Switch PWM on\r | |
369 | * @details Switches PWM on with a narrow spike on all 3 channels -> leds glowing\r | |
370 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
371 | */\r | |
372 | static void\r | |
373 | irsnd_on (void)\r | |
374 | {\r | |
375 | if (! irsnd_is_on)\r | |
376 | {\r | |
377 | #ifndef DEBUG\r | |
08f2dd9d | 378 | # if defined(PIC_C18) // PIC C18\r |
9c86ff1a | 379 | IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r |
08f2dd9d | 380 | # elif defined (ARM_STM32) // STM32\r |
acd29fb9 | 381 | TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r |
382 | TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r | |
383 | TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r | |
08f2dd9d | 384 | # else // AVR\r |
385 | # if IRSND_OCx == IRSND_OC2 // use OC2\r | |
1f54e86c | 386 | TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r |
08f2dd9d | 387 | # elif IRSND_OCx == IRSND_OC2A // use OC2A\r |
f50e01e7 | 388 | TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r |
08f2dd9d | 389 | # elif IRSND_OCx == IRSND_OC2B // use OC2B\r |
f50e01e7 | 390 | TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)\r |
08f2dd9d | 391 | # elif IRSND_OCx == IRSND_OC0 // use OC0\r |
1f54e86c | 392 | TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0\r |
08f2dd9d | 393 | # elif IRSND_OCx == IRSND_OC0A // use OC0A\r |
1f54e86c | 394 | TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A\r |
08f2dd9d | 395 | # elif IRSND_OCx == IRSND_OC0B // use OC0B\r |
1f54e86c | 396 | TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)\r |
08f2dd9d | 397 | # else\r |
398 | # error wrong value of IRSND_OCx\r | |
399 | # endif // IRSND_OCx\r | |
400 | # endif // C18\r | |
4225a882 | 401 | #endif // DEBUG\r |
f50e01e7 | 402 | \r |
403 | #if IRSND_USE_CALLBACK == 1\r | |
404 | if (irsnd_callback_ptr)\r | |
405 | {\r | |
406 | (*irsnd_callback_ptr) (TRUE);\r | |
407 | }\r | |
408 | #endif // IRSND_USE_CALLBACK == 1\r | |
409 | \r | |
4225a882 | 410 | irsnd_is_on = TRUE;\r |
411 | }\r | |
412 | }\r | |
413 | \r | |
414 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
415 | * Switch PWM off\r | |
416 | * @details Switches PWM off\r | |
417 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
418 | */\r | |
419 | static void\r | |
420 | irsnd_off (void)\r | |
421 | {\r | |
422 | if (irsnd_is_on)\r | |
423 | {\r | |
424 | #ifndef DEBUG\r | |
9c86ff1a | 425 | \r |
08f2dd9d | 426 | # if defined(PIC_C18) // PIC C18\r |
9c86ff1a | 427 | IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r |
08f2dd9d | 428 | # elif defined (ARM_STM32) // STM32\r |
acd29fb9 | 429 | TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r |
430 | TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r | |
431 | TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r | |
432 | TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r | |
08f2dd9d | 433 | # else //AVR\r |
9c86ff1a | 434 | \r |
08f2dd9d | 435 | # if IRSND_OCx == IRSND_OC2 // use OC2\r |
f50e01e7 | 436 | TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.\r |
08f2dd9d | 437 | # elif IRSND_OCx == IRSND_OC2A // use OC2A\r |
f50e01e7 | 438 | TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.\r |
08f2dd9d | 439 | # elif IRSND_OCx == IRSND_OC2B // use OC2B\r |
f50e01e7 | 440 | TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.\r |
08f2dd9d | 441 | # elif IRSND_OCx == IRSND_OC0 // use OC0\r |
1f54e86c | 442 | TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.\r |
08f2dd9d | 443 | # elif IRSND_OCx == IRSND_OC0A // use OC0A\r |
1f54e86c | 444 | TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.\r |
08f2dd9d | 445 | # elif IRSND_OCx == IRSND_OC0B // use OC0B\r |
1f54e86c | 446 | TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.\r |
08f2dd9d | 447 | # else\r |
448 | # error wrong value of IRSND_OCx\r | |
449 | # endif // IRSND_OCx\r | |
f50e01e7 | 450 | IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r |
08f2dd9d | 451 | # endif //C18\r |
4225a882 | 452 | #endif // DEBUG\r |
f50e01e7 | 453 | \r |
454 | #if IRSND_USE_CALLBACK == 1\r | |
455 | if (irsnd_callback_ptr)\r | |
456 | {\r | |
457 | (*irsnd_callback_ptr) (FALSE);\r | |
458 | }\r | |
459 | #endif // IRSND_USE_CALLBACK == 1\r | |
460 | \r | |
4225a882 | 461 | irsnd_is_on = FALSE;\r |
462 | }\r | |
463 | }\r | |
464 | \r | |
465 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
466 | * Set PWM frequency\r | |
467 | * @details sets pwm frequency\r | |
468 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
469 | */\r | |
470 | static void\r | |
08f2dd9d | 471 | irsnd_set_freq (IRSND_FREQ_TYPE freq)\r |
4225a882 | 472 | {\r |
473 | #ifndef DEBUG\r | |
08f2dd9d | 474 | # if defined(PIC_C18) // PIC C18\r |
475 | OpenPWM(freq); \r | |
476 | SetDCPWM( (uint16_t) freq * 2); // freq*2 = Duty cycles 50%\r | |
477 | # elif defined (ARM_STM32) // STM32\r | |
37b29f94 | 478 | static uint32_t TimeBaseFreq = 0;\r |
08f2dd9d | 479 | \r |
480 | if (TimeBaseFreq == 0)\r | |
481 | {\r | |
482 | RCC_ClocksTypeDef RCC_ClocksStructure;\r | |
483 | /* Get system clocks and store timer clock in variable */\r | |
484 | RCC_GetClocksFreq(&RCC_ClocksStructure);\r | |
485 | # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r | |
37b29f94 | 486 | if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r |
487 | {\r | |
488 | TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r | |
489 | }\r | |
490 | else\r | |
491 | {\r | |
492 | TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;\r | |
493 | }\r | |
08f2dd9d | 494 | # else\r |
37b29f94 | 495 | if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r |
496 | {\r | |
497 | TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r | |
498 | }\r | |
499 | else\r | |
500 | {\r | |
501 | TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;\r | |
502 | }\r | |
08f2dd9d | 503 | # endif\r |
504 | }\r | |
505 | \r | |
506 | freq = TimeBaseFreq/freq;\r | |
507 | \r | |
37b29f94 | 508 | /* Set frequency */\r |
acd29fb9 | 509 | TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r |
37b29f94 | 510 | /* Set duty cycle */\r |
511 | TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r | |
08f2dd9d | 512 | # else // AVR\r |
513 | \r | |
514 | # if IRSND_OCx == IRSND_OC2\r | |
515 | OCR2 = freq; // use register OCR2 for OC2\r | |
516 | # elif IRSND_OCx == IRSND_OC2A // use OC2A\r | |
517 | OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r | |
518 | # elif IRSND_OCx == IRSND_OC2B // use OC2B\r | |
519 | OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r | |
520 | # elif IRSND_OCx == IRSND_OC0 // use OC0\r | |
521 | OCR0 = freq; // use register OCR2 for OC2\r | |
522 | # elif IRSND_OCx == IRSND_OC0A // use OC0A\r | |
523 | OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r | |
524 | # elif IRSND_OCx == IRSND_OC0B // use OC0B\r | |
525 | OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r | |
526 | # else\r | |
527 | # error wrong value of IRSND_OCx\r | |
528 | # endif\r | |
529 | # endif //PIC_C18\r | |
4225a882 | 530 | #endif // DEBUG\r |
531 | }\r | |
532 | \r | |
533 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
534 | * Initialize the PWM\r | |
535 | * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels\r | |
536 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
537 | */\r | |
538 | void\r | |
539 | irsnd_init (void)\r | |
540 | {\r | |
541 | #ifndef DEBUG\r | |
08f2dd9d | 542 | # if defined(PIC_C18) // PIC C18\r |
543 | OpenTimer;\r | |
544 | irsnd_set_freq (IRSND_FREQ_36_KHZ); //default frequency\r | |
545 | IRSND_PIN = 1; //default PWM output pin off (0=PWM on, 1=PWM off)\r | |
546 | # elif defined (ARM_STM32) // STM32\r | |
37b29f94 | 547 | GPIO_InitTypeDef GPIO_InitStructure;\r |
548 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r | |
549 | TIM_OCInitTypeDef TIM_OCInitStructure;\r | |
08f2dd9d | 550 | \r |
551 | /* GPIOx clock enable */\r | |
552 | # if defined (ARM_STM32L1XX)\r | |
553 | RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r | |
554 | # elif defined (ARM_STM32F10X)\r | |
555 | RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r | |
556 | # elif defined (ARM_STM32F4XX)\r | |
557 | RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r | |
558 | # endif\r | |
559 | \r | |
560 | /* GPIO Configuration */\r | |
561 | GPIO_InitStructure.GPIO_Pin = IRSND_BIT;\r | |
562 | # if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)\r | |
563 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r | |
564 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r | |
565 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r | |
566 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r | |
567 | GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r | |
568 | GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);\r | |
569 | # elif defined (ARM_STM32F10X)\r | |
570 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r | |
571 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r | |
572 | GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r | |
573 | GPIO_PinRemapConfig(, ENABLE); // TODO: remapping required\r | |
574 | # endif\r | |
575 | \r | |
576 | /* TIMx clock enable */\r | |
577 | # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r | |
578 | RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r | |
579 | # else\r | |
580 | RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r | |
581 | # endif\r | |
08f2dd9d | 582 | \r |
37b29f94 | 583 | /* Time base configuration */\r |
acd29fb9 | 584 | TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r |
37b29f94 | 585 | TIM_TimeBaseStructure.TIM_Prescaler = 0;\r |
586 | TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r | |
587 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r | |
588 | TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r | |
589 | \r | |
590 | /* PWM1 Mode configuration */\r | |
591 | TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r | |
592 | TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r | |
acd29fb9 | 593 | TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r |
37b29f94 | 594 | TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r |
595 | TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r | |
596 | \r | |
597 | /* Preload configuration */\r | |
08f2dd9d | 598 | TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r |
acd29fb9 | 599 | TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r |
37b29f94 | 600 | \r |
acd29fb9 | 601 | irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r |
08f2dd9d | 602 | # else // AVR\r |
603 | IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r | |
604 | IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r | |
605 | \r | |
606 | # if IRSND_OCx == IRSND_OC2 // use OC2\r | |
607 | TCCR2 = (1<<WGM21); // CTC mode\r | |
608 | TCCR2 |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r | |
609 | # elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B\r | |
610 | TCCR2A = (1<<WGM21); // CTC mode\r | |
611 | TCCR2B |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r | |
612 | # elif IRSND_OCx == IRSND_OC0 // use OC0\r | |
613 | TCCR0 = (1<<WGM01); // CTC mode\r | |
614 | TCCR0 |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r | |
615 | # elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B\r | |
616 | TCCR0A = (1<<WGM01); // CTC mode\r | |
617 | TCCR0B |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r | |
618 | # else\r | |
619 | # error wrong value of IRSND_OCx\r | |
620 | # endif\r | |
621 | irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r | |
622 | # endif //PIC_C18\r | |
4225a882 | 623 | #endif // DEBUG\r |
624 | }\r | |
625 | \r | |
f50e01e7 | 626 | #if IRSND_USE_CALLBACK == 1\r |
627 | void\r | |
628 | irsnd_set_callback_ptr (void (*cb)(uint8_t))\r | |
629 | {\r | |
630 | irsnd_callback_ptr = cb;\r | |
631 | }\r | |
632 | #endif // IRSND_USE_CALLBACK == 1\r | |
633 | \r | |
4225a882 | 634 | uint8_t\r |
635 | irsnd_is_busy (void)\r | |
636 | {\r | |
637 | return irsnd_busy;\r | |
638 | }\r | |
639 | \r | |
640 | static uint16_t\r | |
641 | bitsrevervse (uint16_t x, uint8_t len)\r | |
642 | {\r | |
643 | uint16_t xx = 0;\r | |
644 | \r | |
645 | while(len)\r | |
646 | {\r | |
647 | xx <<= 1;\r | |
648 | if (x & 1)\r | |
649 | {\r | |
650 | xx |= 1;\r | |
651 | }\r | |
652 | x >>= 1;\r | |
653 | len--;\r | |
654 | }\r | |
655 | return xx;\r | |
656 | }\r | |
657 | \r | |
658 | \r | |
9547ee89 | 659 | #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r |
660 | static uint8_t sircs_additional_bitlen;\r | |
661 | #endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r | |
662 | \r | |
4225a882 | 663 | uint8_t\r |
879b06c2 | 664 | irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)\r |
4225a882 | 665 | {\r |
666 | #if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r | |
667 | static uint8_t toggle_bit_recs80;\r | |
668 | #endif\r | |
669 | #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r | |
670 | static uint8_t toggle_bit_recs80ext;\r | |
671 | #endif\r | |
672 | #if IRSND_SUPPORT_RC5_PROTOCOL == 1\r | |
673 | static uint8_t toggle_bit_rc5;\r | |
9547ee89 | 674 | #endif\r |
779fbc81 | 675 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r |
9547ee89 | 676 | static uint8_t toggle_bit_rc6;\r |
beda975f | 677 | #endif\r |
678 | #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r | |
679 | static uint8_t toggle_bit_thomson;\r | |
4225a882 | 680 | #endif\r |
681 | uint16_t address;\r | |
682 | uint16_t command;\r | |
683 | \r | |
879b06c2 | 684 | if (do_wait)\r |
4225a882 | 685 | {\r |
879b06c2 | 686 | while (irsnd_busy)\r |
687 | {\r | |
688 | // do nothing;\r | |
689 | }\r | |
690 | }\r | |
691 | else if (irsnd_busy)\r | |
692 | {\r | |
693 | return (FALSE);\r | |
4225a882 | 694 | }\r |
695 | \r | |
696 | irsnd_protocol = irmp_data_p->protocol;\r | |
beda975f | 697 | irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;\r |
4225a882 | 698 | \r |
699 | switch (irsnd_protocol)\r | |
700 | {\r | |
701 | #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r | |
702 | case IRMP_SIRCS_PROTOCOL:\r | |
703 | {\r | |
08f2dd9d | 704 | // uint8_t sircs_additional_command_len;\r |
9547ee89 | 705 | uint8_t sircs_additional_address_len;\r |
706 | \r | |
707 | sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen\r | |
708 | \r | |
709 | if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)\r | |
710 | {\r | |
08f2dd9d | 711 | // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;\r |
9547ee89 | 712 | sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);\r |
713 | }\r | |
714 | else\r | |
715 | {\r | |
08f2dd9d | 716 | // sircs_additional_command_len = sircs_additional_bitlen;\r |
9547ee89 | 717 | sircs_additional_address_len = 0;\r |
718 | }\r | |
4225a882 | 719 | \r |
9547ee89 | 720 | command = bitsrevervse (irmp_data_p->command, 15);\r |
721 | \r | |
722 | irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC\r | |
723 | irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****\r | |
724 | \r | |
725 | if (sircs_additional_address_len > 0)\r | |
726 | {\r | |
727 | address = bitsrevervse (irmp_data_p->address, 5);\r | |
728 | irsnd_buffer[1] |= (address & 0x0010) >> 4;\r | |
729 | irsnd_buffer[2] = (address & 0x000F) << 4;\r | |
730 | }\r | |
4225a882 | 731 | irsnd_busy = TRUE;\r |
732 | break;\r | |
733 | }\r | |
734 | #endif\r | |
735 | #if IRSND_SUPPORT_NEC_PROTOCOL == 1\r | |
46dd89b7 | 736 | case IRMP_APPLE_PROTOCOL:\r |
c7a47e89 | 737 | {\r |
738 | command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command\r | |
739 | address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)\r | |
740 | \r | |
741 | address = bitsrevervse (address, NEC_ADDRESS_LEN);\r | |
742 | command = bitsrevervse (command, NEC_COMMAND_LEN);\r | |
743 | \r | |
744 | irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command\r | |
745 | \r | |
7644ac04 | 746 | irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r |
747 | irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r | |
748 | irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r | |
749 | irsnd_buffer[3] = 0x8B; // 10001011 (id)\r | |
c7a47e89 | 750 | irsnd_busy = TRUE;\r |
751 | break;\r | |
752 | }\r | |
753 | case IRMP_NEC_PROTOCOL:\r | |
4225a882 | 754 | {\r |
755 | address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);\r | |
756 | command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);\r | |
757 | \r | |
4225a882 | 758 | irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r |
759 | irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r | |
760 | irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r | |
7644ac04 | 761 | irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r |
762 | irsnd_busy = TRUE;\r | |
763 | break;\r | |
764 | }\r | |
765 | #endif\r | |
766 | #if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r | |
767 | case IRMP_NEC16_PROTOCOL:\r | |
768 | {\r | |
769 | address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);\r | |
770 | command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);\r | |
46dd89b7 | 771 | \r |
7644ac04 | 772 | irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA\r |
773 | irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r | |
774 | irsnd_busy = TRUE;\r | |
775 | break;\r | |
776 | }\r | |
777 | #endif\r | |
778 | #if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r | |
779 | case IRMP_NEC42_PROTOCOL:\r | |
780 | {\r | |
781 | address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);\r | |
782 | command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);\r | |
783 | \r | |
784 | irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA\r | |
a48187fa | 785 | irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa\r |
7644ac04 | 786 | irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa\r |
787 | irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC\r | |
788 | irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc\r | |
789 | irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc\r | |
4225a882 | 790 | irsnd_busy = TRUE;\r |
791 | break;\r | |
792 | }\r | |
793 | #endif\r | |
794 | #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r | |
795 | case IRMP_SAMSUNG_PROTOCOL:\r | |
796 | {\r | |
797 | address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r | |
798 | command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);\r | |
799 | \r | |
4225a882 | 800 | irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r |
801 | irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r | |
802 | irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC\r | |
803 | irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc\r | |
804 | irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000\r | |
805 | irsnd_busy = TRUE;\r | |
806 | break;\r | |
807 | }\r | |
808 | case IRMP_SAMSUNG32_PROTOCOL:\r | |
809 | {\r | |
810 | address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r | |
811 | command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);\r | |
812 | \r | |
4225a882 | 813 | irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r |
814 | irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r | |
815 | irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r | |
816 | irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC\r | |
817 | irsnd_busy = TRUE;\r | |
818 | break;\r | |
819 | }\r | |
820 | #endif\r | |
821 | #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r | |
822 | case IRMP_MATSUSHITA_PROTOCOL:\r | |
823 | {\r | |
824 | address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);\r | |
825 | command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);\r | |
826 | \r | |
4225a882 | 827 | irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r |
828 | irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA\r | |
829 | irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA\r | |
830 | irsnd_busy = TRUE;\r | |
831 | break;\r | |
832 | }\r | |
833 | #endif\r | |
770a1a9d | 834 | #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r |
835 | case IRMP_KASEIKYO_PROTOCOL:\r | |
836 | {\r | |
837 | uint8_t xor;\r | |
0f700c8e | 838 | uint16_t genre2;\r |
770a1a9d | 839 | \r |
840 | address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);\r | |
841 | command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);\r | |
0f700c8e | 842 | genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);\r |
770a1a9d | 843 | \r |
844 | xor = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r | |
845 | \r | |
846 | irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r | |
847 | irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r | |
848 | irsnd_buffer[2] = xor << 4 | (command & 0x000F); // XXXXCCCC\r | |
0f700c8e | 849 | irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC\r |
770a1a9d | 850 | irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC\r |
851 | \r | |
852 | xor = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r | |
853 | \r | |
854 | irsnd_buffer[5] = xor;\r | |
855 | irsnd_busy = TRUE;\r | |
856 | break;\r | |
857 | }\r | |
858 | #endif\r | |
4225a882 | 859 | #if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r |
860 | case IRMP_RECS80_PROTOCOL:\r | |
861 | {\r | |
862 | toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x40;\r | |
863 | \r | |
4225a882 | 864 | irsnd_buffer[0] = 0x80 | toggle_bit_recs80 | ((irmp_data_p->address & 0x0007) << 3) |\r |
865 | ((irmp_data_p->command & 0x0038) >> 3); // STAAACCC\r | |
866 | irsnd_buffer[1] = (irmp_data_p->command & 0x07) << 5; // CCC00000\r | |
867 | irsnd_busy = TRUE;\r | |
868 | break;\r | |
869 | }\r | |
870 | #endif\r | |
871 | #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r | |
872 | case IRMP_RECS80EXT_PROTOCOL:\r | |
873 | {\r | |
874 | toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;\r | |
875 | \r | |
4225a882 | 876 | irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |\r |
877 | ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC\r | |
878 | irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000\r | |
879 | irsnd_busy = TRUE;\r | |
880 | break;\r | |
881 | }\r | |
882 | #endif\r | |
883 | #if IRSND_SUPPORT_RC5_PROTOCOL == 1\r | |
884 | case IRMP_RC5_PROTOCOL:\r | |
885 | {\r | |
886 | toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;\r | |
887 | \r | |
4225a882 | 888 | irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |\r |
889 | ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC\r | |
890 | irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000\r | |
891 | irsnd_busy = TRUE;\r | |
892 | break;\r | |
893 | }\r | |
894 | #endif\r | |
9547ee89 | 895 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1\r |
896 | case IRMP_RC6_PROTOCOL:\r | |
897 | {\r | |
898 | toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r | |
899 | \r | |
900 | irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000\r | |
901 | irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC\r | |
902 | irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC\r | |
903 | irsnd_busy = TRUE;\r | |
904 | break;\r | |
905 | }\r | |
906 | #endif\r | |
907 | #if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r | |
908 | case IRMP_RC6A_PROTOCOL:\r | |
909 | {\r | |
910 | toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r | |
911 | \r | |
912 | irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110\r | |
913 | irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA\r | |
914 | irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC\r | |
915 | irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r | |
916 | irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC\r | |
917 | irsnd_busy = TRUE;\r | |
918 | break;\r | |
919 | }\r | |
920 | #endif\r | |
4225a882 | 921 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r |
922 | case IRMP_DENON_PROTOCOL:\r | |
923 | {\r | |
d155e9ab | 924 | irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)\r |
925 | irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC\r | |
08f2dd9d | 926 | irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)\r |
927 | irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc\r | |
4225a882 | 928 | irsnd_busy = TRUE;\r |
929 | break;\r | |
930 | }\r | |
931 | #endif\r | |
beda975f | 932 | #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r |
933 | case IRMP_THOMSON_PROTOCOL:\r | |
934 | {\r | |
935 | toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;\r | |
936 | \r | |
937 | irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)\r | |
938 | irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC\r | |
939 | irsnd_busy = TRUE;\r | |
940 | break;\r | |
941 | }\r | |
942 | #endif\r | |
4225a882 | 943 | #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r |
944 | case IRMP_NUBERT_PROTOCOL:\r | |
945 | {\r | |
4225a882 | 946 | irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r |
947 | irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r | |
948 | irsnd_busy = TRUE;\r | |
949 | break;\r | |
950 | }\r | |
5481e9cd | 951 | #endif\r |
952 | #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r | |
953 | case IRMP_BANG_OLUFSEN_PROTOCOL:\r | |
954 | {\r | |
5481e9cd | 955 | irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC\r |
956 | irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC\r | |
957 | irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r | |
958 | irsnd_busy = TRUE;\r | |
959 | break;\r | |
960 | }\r | |
4225a882 | 961 | #endif\r |
5b437ff6 | 962 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r |
963 | case IRMP_GRUNDIG_PROTOCOL:\r | |
964 | {\r | |
965 | command = bitsrevervse (irmp_data_p->command, GRUNDIG_COMMAND_LEN);\r | |
966 | \r | |
d155e9ab | 967 | irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)\r |
968 | irsnd_buffer[1] = 0xC0; // 11\r | |
969 | irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)\r | |
970 | irsnd_buffer[3] = (command << 6) & 0xC0; // CC\r | |
971 | \r | |
972 | irsnd_busy = TRUE;\r | |
973 | break;\r | |
974 | }\r | |
975 | #endif\r | |
a48187fa | 976 | #if IRSND_SUPPORT_IR60_PROTOCOL == 1\r |
977 | case IRMP_IR60_PROTOCOL:\r | |
978 | {\r | |
979 | command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);\r | |
08f2dd9d | 980 | #if 0\r |
a48187fa | 981 | irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)\r |
982 | irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)\r | |
08f2dd9d | 983 | #else\r |
984 | irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)\r | |
985 | irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)\r | |
986 | #endif\r | |
a48187fa | 987 | \r |
988 | irsnd_busy = TRUE;\r | |
989 | break;\r | |
990 | }\r | |
991 | #endif\r | |
d155e9ab | 992 | #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
993 | case IRMP_NOKIA_PROTOCOL:\r | |
994 | {\r | |
995 | address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);\r | |
996 | command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);\r | |
997 | \r | |
998 | irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)\r | |
999 | irsnd_buffer[1] = 0xFF; // 11111111\r | |
1000 | irsnd_buffer[2] = 0x80; // 1\r | |
1001 | irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)\r | |
1002 | irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA\r | |
1003 | irsnd_buffer[5] = (address << 7); // A\r | |
5b437ff6 | 1004 | \r |
1005 | irsnd_busy = TRUE;\r | |
1006 | break;\r | |
1007 | }\r | |
1008 | #endif\r | |
a7054daf | 1009 | #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r |
1010 | case IRMP_SIEMENS_PROTOCOL:\r | |
1011 | {\r | |
1012 | irsnd_buffer[0] = ((irmp_data_p->address & 0x0FFF) >> 5); // SAAAAAAA\r | |
1013 | irsnd_buffer[1] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x7F) >> 5); // AAAAA0CC\r | |
9405f84a | 1014 | irsnd_buffer[2] = (irmp_data_p->command << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r |
1015 | \r | |
a7054daf | 1016 | irsnd_busy = TRUE;\r |
1017 | break;\r | |
1018 | }\r | |
b5ea7869 | 1019 | #endif\r |
48664931 | 1020 | #if IRSND_SUPPORT_FDC_PROTOCOL == 1\r |
1021 | case IRMP_FDC_PROTOCOL:\r | |
b5ea7869 | 1022 | {\r |
48664931 | 1023 | address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);\r |
1024 | command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);\r | |
b5ea7869 | 1025 | \r |
c7c9a4a1 | 1026 | irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA\r |
1027 | irsnd_buffer[1] = 0; // 00000000\r | |
1028 | irsnd_buffer[2] = 0; // 0000RRRR\r | |
1029 | irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC\r | |
1030 | irsnd_buffer[4] = ~(command & 0xFF); // cccccccc\r | |
1031 | irsnd_busy = TRUE;\r | |
1032 | break;\r | |
1033 | }\r | |
1034 | #endif\r | |
1035 | #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r | |
1036 | case IRMP_RCCAR_PROTOCOL:\r | |
1037 | {\r | |
1038 | address = bitsrevervse (irmp_data_p->address, 2); // A0 A1\r | |
1039 | command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V\r | |
1040 | \r | |
1041 | irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3\r | |
1042 | irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0\r | |
1043 | \r | |
b5ea7869 | 1044 | irsnd_busy = TRUE;\r |
1045 | break;\r | |
1046 | }\r | |
a7054daf | 1047 | #endif\r |
c7a47e89 | 1048 | #if IRSND_SUPPORT_JVC_PROTOCOL == 1\r |
1049 | case IRMP_JVC_PROTOCOL:\r | |
1050 | {\r | |
1051 | address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);\r | |
1052 | command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);\r | |
1053 | \r | |
1054 | irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC\r | |
1055 | irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r | |
1056 | \r | |
1057 | irsnd_busy = TRUE;\r | |
1058 | break;\r | |
1059 | }\r | |
1060 | #endif\r | |
9405f84a | 1061 | #if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r |
1062 | case IRMP_NIKON_PROTOCOL:\r | |
1063 | {\r | |
1064 | irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC\r | |
1065 | irsnd_busy = TRUE;\r | |
1066 | break;\r | |
1067 | }\r | |
f50e01e7 | 1068 | #endif\r |
1069 | #if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r | |
1070 | case IRMP_LEGO_PROTOCOL:\r | |
1071 | {\r | |
1072 | uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);\r | |
1073 | \r | |
1074 | irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r | |
1075 | irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc\r | |
1076 | \r | |
1077 | irsnd_protocol = IRMP_LEGO_PROTOCOL;\r | |
1078 | irsnd_busy = TRUE;\r | |
1079 | break;\r | |
1080 | }\r | |
9405f84a | 1081 | #endif\r |
4225a882 | 1082 | default:\r |
1083 | {\r | |
1084 | break;\r | |
1085 | }\r | |
1086 | }\r | |
1087 | \r | |
1088 | return irsnd_busy;\r | |
1089 | }\r | |
1090 | \r | |
beda975f | 1091 | void\r |
1092 | irsnd_stop (void)\r | |
1093 | {\r | |
acf7fb44 | 1094 | irsnd_repeat = 0;\r |
beda975f | 1095 | }\r |
1096 | \r | |
4225a882 | 1097 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
1098 | * ISR routine\r | |
1099 | * @details ISR routine, called 10000 times per second\r | |
1100 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
1101 | */\r | |
1102 | uint8_t\r | |
1103 | irsnd_ISR (void)\r | |
1104 | {\r | |
a48187fa | 1105 | static uint8_t send_trailer = FALSE;\r |
1106 | static uint8_t current_bit = 0xFF;\r | |
1107 | static uint8_t pulse_counter = 0;\r | |
1108 | static IRSND_PAUSE_LEN pause_counter = 0;\r | |
1109 | static uint8_t startbit_pulse_len = 0;\r | |
1110 | static IRSND_PAUSE_LEN startbit_pause_len = 0;\r | |
1111 | static uint8_t pulse_1_len = 0;\r | |
1112 | static uint8_t pause_1_len = 0;\r | |
1113 | static uint8_t pulse_0_len = 0;\r | |
1114 | static uint8_t pause_0_len = 0;\r | |
1115 | static uint8_t has_stop_bit = 0;\r | |
1116 | static uint8_t new_frame = TRUE;\r | |
1117 | static uint8_t complete_data_len = 0;\r | |
1118 | static uint8_t n_repeat_frames = 0; // number of repetition frames\r | |
1119 | static uint8_t n_auto_repetitions = 0; // number of auto_repetitions\r | |
1120 | static uint8_t auto_repetition_counter = 0; // auto_repetition counter\r | |
1121 | static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!\r | |
1122 | static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!\r | |
1123 | static uint8_t repeat_counter = 0; // repeat counter\r | |
1124 | static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!\r | |
1125 | static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!\r | |
5481e9cd | 1126 | #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r |
a48187fa | 1127 | static uint8_t last_bit_value;\r |
5481e9cd | 1128 | #endif\r |
a48187fa | 1129 | static uint8_t pulse_len = 0xFF;\r |
08f2dd9d | 1130 | static IRSND_PAUSE_LEN pause_len = 0xFF;\r |
4225a882 | 1131 | \r |
1132 | if (irsnd_busy)\r | |
1133 | {\r | |
1134 | if (current_bit == 0xFF && new_frame) // start of transmission...\r | |
1135 | {\r | |
a7054daf | 1136 | if (auto_repetition_counter > 0)\r |
4225a882 | 1137 | {\r |
a7054daf | 1138 | auto_repetition_pause_counter++;\r |
4225a882 | 1139 | \r |
08f2dd9d | 1140 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r |
1141 | if (repeat_frame_pause_len > 0) // frame repeat distance counts from beginning of 1st frame!\r | |
1142 | {\r | |
1143 | repeat_frame_pause_len--;\r | |
1144 | }\r | |
1145 | #endif\r | |
1146 | \r | |
a7054daf | 1147 | if (auto_repetition_pause_counter >= auto_repetition_pause_len)\r |
4225a882 | 1148 | {\r |
a7054daf | 1149 | auto_repetition_pause_counter = 0;\r |
4225a882 | 1150 | \r |
08f2dd9d | 1151 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r |
a48187fa | 1152 | if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame\r |
4225a882 | 1153 | {\r |
1154 | current_bit = 16;\r | |
1155 | complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;\r | |
1156 | }\r | |
08f2dd9d | 1157 | else\r |
1158 | #endif\r | |
1159 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r | |
1160 | if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame\r | |
5b437ff6 | 1161 | {\r |
1162 | current_bit = 15;\r | |
1163 | complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;\r | |
1164 | }\r | |
08f2dd9d | 1165 | else\r |
1166 | #endif\r | |
1167 | #if IRSND_SUPPORT_IR60_PROTOCOL == 1\r | |
1168 | if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame\r | |
a48187fa | 1169 | {\r |
1170 | current_bit = 7;\r | |
1171 | complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;\r | |
1172 | }\r | |
08f2dd9d | 1173 | else\r |
1174 | #endif\r | |
1175 | #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r | |
1176 | if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame\r | |
d155e9ab | 1177 | {\r |
a7054daf | 1178 | if (auto_repetition_counter + 1 < n_auto_repetitions)\r |
d155e9ab | 1179 | {\r |
1180 | current_bit = 23;\r | |
1181 | complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;\r | |
1182 | }\r | |
a7054daf | 1183 | else // nokia stop frame\r |
d155e9ab | 1184 | {\r |
1185 | current_bit = 0xFF;\r | |
1186 | complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r | |
1187 | }\r | |
1188 | }\r | |
08f2dd9d | 1189 | else\r |
1190 | #endif\r | |
1191 | {\r | |
1192 | ;\r | |
1193 | }\r | |
4225a882 | 1194 | }\r |
1195 | else\r | |
1196 | {\r | |
1197 | #ifdef DEBUG\r | |
1198 | if (irsnd_is_on)\r | |
1199 | {\r | |
1200 | putchar ('0');\r | |
1201 | }\r | |
1202 | else\r | |
1203 | {\r | |
1204 | putchar ('1');\r | |
1205 | }\r | |
1206 | #endif\r | |
1207 | return irsnd_busy;\r | |
1208 | }\r | |
1209 | }\r | |
beda975f | 1210 | #if 0\r |
a7054daf | 1211 | else if (repeat_counter > 0 && packet_repeat_pause_counter < repeat_frame_pause_len)\r |
beda975f | 1212 | #else\r |
1213 | else if (packet_repeat_pause_counter < repeat_frame_pause_len)\r | |
1214 | #endif\r | |
a7054daf | 1215 | {\r |
1216 | packet_repeat_pause_counter++;\r | |
1217 | \r | |
1218 | #ifdef DEBUG\r | |
1219 | if (irsnd_is_on)\r | |
1220 | {\r | |
1221 | putchar ('0');\r | |
1222 | }\r | |
1223 | else\r | |
1224 | {\r | |
1225 | putchar ('1');\r | |
1226 | }\r | |
1227 | #endif\r | |
1228 | return irsnd_busy;\r | |
1229 | }\r | |
4225a882 | 1230 | else\r |
1231 | {\r | |
0f700c8e | 1232 | if (send_trailer)\r |
1233 | {\r | |
1234 | irsnd_busy = FALSE;\r | |
6ab7d63c | 1235 | send_trailer = FALSE;\r |
0f700c8e | 1236 | return irsnd_busy;\r |
1237 | }\r | |
9c86ff1a | 1238 | \r |
a7054daf | 1239 | n_repeat_frames = irsnd_repeat;\r |
beda975f | 1240 | \r |
1241 | if (n_repeat_frames == IRSND_ENDLESS_REPETITION)\r | |
1242 | {\r | |
1243 | n_repeat_frames = 255;\r | |
1244 | }\r | |
1245 | \r | |
a7054daf | 1246 | packet_repeat_pause_counter = 0;\r |
1247 | pulse_counter = 0;\r | |
1248 | pause_counter = 0;\r | |
5481e9cd | 1249 | \r |
4225a882 | 1250 | switch (irsnd_protocol)\r |
1251 | {\r | |
1252 | #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r | |
1253 | case IRMP_SIRCS_PROTOCOL:\r | |
1254 | {\r | |
a7054daf | 1255 | startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;\r |
53c11f07 | 1256 | startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1257 | pulse_1_len = SIRCS_1_PULSE_LEN;\r |
53c11f07 | 1258 | pause_1_len = SIRCS_PAUSE_LEN - 1;\r |
a7054daf | 1259 | pulse_0_len = SIRCS_0_PULSE_LEN;\r |
53c11f07 | 1260 | pause_0_len = SIRCS_PAUSE_LEN - 1;\r |
a7054daf | 1261 | has_stop_bit = SIRCS_STOP_BIT;\r |
9547ee89 | 1262 | complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;\r |
a7054daf | 1263 | n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame\r |
1264 | auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause\r | |
1265 | repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1266 | irsnd_set_freq (IRSND_FREQ_40_KHZ);\r |
1267 | break;\r | |
1268 | }\r | |
1269 | #endif\r | |
1270 | #if IRSND_SUPPORT_NEC_PROTOCOL == 1\r | |
1271 | case IRMP_NEC_PROTOCOL:\r | |
1272 | {\r | |
a7054daf | 1273 | startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r |
1274 | \r | |
1275 | if (repeat_counter > 0)\r | |
1276 | {\r | |
53c11f07 | 1277 | startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1278 | complete_data_len = 0;\r |
1279 | }\r | |
1280 | else\r | |
1281 | {\r | |
53c11f07 | 1282 | startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1283 | complete_data_len = NEC_COMPLETE_DATA_LEN;\r |
1284 | }\r | |
1285 | \r | |
1286 | pulse_1_len = NEC_PULSE_LEN;\r | |
53c11f07 | 1287 | pause_1_len = NEC_1_PAUSE_LEN - 1;\r |
a7054daf | 1288 | pulse_0_len = NEC_PULSE_LEN;\r |
53c11f07 | 1289 | pause_0_len = NEC_0_PAUSE_LEN - 1;\r |
a7054daf | 1290 | has_stop_bit = NEC_STOP_BIT;\r |
1291 | n_auto_repetitions = 1; // 1 frame\r | |
1292 | auto_repetition_pause_len = 0;\r | |
1293 | repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1294 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1295 | break;\r | |
1296 | }\r | |
1297 | #endif\r | |
7644ac04 | 1298 | #if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r |
1299 | case IRMP_NEC16_PROTOCOL:\r | |
1300 | {\r | |
1301 | startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r | |
1302 | startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r | |
1303 | pulse_1_len = NEC_PULSE_LEN;\r | |
1304 | pause_1_len = NEC_1_PAUSE_LEN - 1;\r | |
1305 | pulse_0_len = NEC_PULSE_LEN;\r | |
1306 | pause_0_len = NEC_0_PAUSE_LEN - 1;\r | |
1307 | has_stop_bit = NEC_STOP_BIT;\r | |
1308 | complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit\r | |
1309 | n_auto_repetitions = 1; // 1 frame\r | |
1310 | auto_repetition_pause_len = 0;\r | |
1311 | repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r | |
1312 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1313 | break;\r | |
1314 | }\r | |
1315 | #endif\r | |
1316 | #if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r | |
1317 | case IRMP_NEC42_PROTOCOL:\r | |
1318 | {\r | |
1319 | startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r | |
1320 | startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r | |
1321 | pulse_1_len = NEC_PULSE_LEN;\r | |
1322 | pause_1_len = NEC_1_PAUSE_LEN - 1;\r | |
1323 | pulse_0_len = NEC_PULSE_LEN;\r | |
1324 | pause_0_len = NEC_0_PAUSE_LEN - 1;\r | |
1325 | has_stop_bit = NEC_STOP_BIT;\r | |
1326 | complete_data_len = NEC42_COMPLETE_DATA_LEN;\r | |
1327 | n_auto_repetitions = 1; // 1 frame\r | |
1328 | auto_repetition_pause_len = 0;\r | |
1329 | repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r | |
1330 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1331 | break;\r | |
1332 | }\r | |
1333 | #endif\r | |
4225a882 | 1334 | #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r |
1335 | case IRMP_SAMSUNG_PROTOCOL:\r | |
1336 | {\r | |
a7054daf | 1337 | startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r |
53c11f07 | 1338 | startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1339 | pulse_1_len = SAMSUNG_PULSE_LEN;\r |
53c11f07 | 1340 | pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r |
a7054daf | 1341 | pulse_0_len = SAMSUNG_PULSE_LEN;\r |
53c11f07 | 1342 | pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r |
a7054daf | 1343 | has_stop_bit = SAMSUNG_STOP_BIT;\r |
1344 | complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;\r | |
1345 | n_auto_repetitions = 1; // 1 frame\r | |
1346 | auto_repetition_pause_len = 0;\r | |
1347 | repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1348 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1349 | break;\r | |
1350 | }\r | |
1351 | \r | |
1352 | case IRMP_SAMSUNG32_PROTOCOL:\r | |
1353 | {\r | |
a7054daf | 1354 | startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r |
53c11f07 | 1355 | startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1356 | pulse_1_len = SAMSUNG_PULSE_LEN;\r |
53c11f07 | 1357 | pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r |
a7054daf | 1358 | pulse_0_len = SAMSUNG_PULSE_LEN;\r |
53c11f07 | 1359 | pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r |
a7054daf | 1360 | has_stop_bit = SAMSUNG_STOP_BIT;\r |
1361 | complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;\r | |
1362 | n_auto_repetitions = SAMSUNG32_FRAMES; // 2 frames\r | |
1363 | auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r | |
1364 | repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1365 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1366 | break;\r | |
1367 | }\r | |
1368 | #endif\r | |
1369 | #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r | |
1370 | case IRMP_MATSUSHITA_PROTOCOL:\r | |
1371 | {\r | |
a7054daf | 1372 | startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r |
53c11f07 | 1373 | startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1374 | pulse_1_len = MATSUSHITA_PULSE_LEN;\r |
53c11f07 | 1375 | pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r |
a7054daf | 1376 | pulse_0_len = MATSUSHITA_PULSE_LEN;\r |
53c11f07 | 1377 | pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r |
a7054daf | 1378 | has_stop_bit = MATSUSHITA_STOP_BIT;\r |
1379 | complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;\r | |
1380 | n_auto_repetitions = 1; // 1 frame\r | |
1381 | auto_repetition_pause_len = 0;\r | |
1382 | repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1383 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r |
1384 | break;\r | |
1385 | }\r | |
1386 | #endif\r | |
770a1a9d | 1387 | #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r |
1388 | case IRMP_KASEIKYO_PROTOCOL:\r | |
1389 | {\r | |
1390 | startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1391 | startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;\r |
770a1a9d | 1392 | pulse_1_len = KASEIKYO_PULSE_LEN;\r |
53c11f07 | 1393 | pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;\r |
770a1a9d | 1394 | pulse_0_len = KASEIKYO_PULSE_LEN;\r |
53c11f07 | 1395 | pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;\r |
770a1a9d | 1396 | has_stop_bit = KASEIKYO_STOP_BIT;\r |
1397 | complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;\r | |
1398 | n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame\r | |
1399 | auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause\r | |
1400 | repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;\r | |
1401 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1402 | break;\r | |
1403 | }\r | |
1404 | #endif\r | |
4225a882 | 1405 | #if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r |
1406 | case IRMP_RECS80_PROTOCOL:\r | |
1407 | {\r | |
a7054daf | 1408 | startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;\r |
53c11f07 | 1409 | startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1410 | pulse_1_len = RECS80_PULSE_LEN;\r |
53c11f07 | 1411 | pause_1_len = RECS80_1_PAUSE_LEN - 1;\r |
a7054daf | 1412 | pulse_0_len = RECS80_PULSE_LEN;\r |
53c11f07 | 1413 | pause_0_len = RECS80_0_PAUSE_LEN - 1;\r |
a7054daf | 1414 | has_stop_bit = RECS80_STOP_BIT;\r |
1415 | complete_data_len = RECS80_COMPLETE_DATA_LEN;\r | |
1416 | n_auto_repetitions = 1; // 1 frame\r | |
1417 | auto_repetition_pause_len = 0;\r | |
1418 | repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1419 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1420 | break;\r | |
1421 | }\r | |
1422 | #endif\r | |
1423 | #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r | |
1424 | case IRMP_RECS80EXT_PROTOCOL:\r | |
1425 | {\r | |
a7054daf | 1426 | startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;\r |
53c11f07 | 1427 | startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1428 | pulse_1_len = RECS80EXT_PULSE_LEN;\r |
53c11f07 | 1429 | pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;\r |
a7054daf | 1430 | pulse_0_len = RECS80EXT_PULSE_LEN;\r |
53c11f07 | 1431 | pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;\r |
a7054daf | 1432 | has_stop_bit = RECS80EXT_STOP_BIT;\r |
1433 | complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;\r | |
1434 | n_auto_repetitions = 1; // 1 frame\r | |
1435 | auto_repetition_pause_len = 0;\r | |
1436 | repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1437 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1438 | break;\r | |
1439 | }\r | |
1440 | #endif\r | |
1441 | #if IRSND_SUPPORT_RC5_PROTOCOL == 1\r | |
1442 | case IRMP_RC5_PROTOCOL:\r | |
1443 | {\r | |
a7054daf | 1444 | startbit_pulse_len = RC5_BIT_LEN;\r |
1445 | startbit_pause_len = RC5_BIT_LEN;\r | |
1446 | pulse_len = RC5_BIT_LEN;\r | |
1447 | pause_len = RC5_BIT_LEN;\r | |
1448 | has_stop_bit = RC5_STOP_BIT;\r | |
1449 | complete_data_len = RC5_COMPLETE_DATA_LEN;\r | |
1450 | n_auto_repetitions = 1; // 1 frame\r | |
1451 | auto_repetition_pause_len = 0;\r | |
1452 | repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1453 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r |
1454 | break;\r | |
1455 | }\r | |
1456 | #endif\r | |
9547ee89 | 1457 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1\r |
1458 | case IRMP_RC6_PROTOCOL:\r | |
1459 | {\r | |
1460 | startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1461 | startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r |
9547ee89 | 1462 | pulse_len = RC6_BIT_LEN;\r |
1463 | pause_len = RC6_BIT_LEN;\r | |
1464 | has_stop_bit = RC6_STOP_BIT;\r | |
1465 | complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;\r | |
1466 | n_auto_repetitions = 1; // 1 frame\r | |
1467 | auto_repetition_pause_len = 0;\r | |
1468 | repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r | |
1469 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r | |
1470 | break;\r | |
1471 | }\r | |
1472 | #endif\r | |
1473 | #if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r | |
1474 | case IRMP_RC6A_PROTOCOL:\r | |
1475 | {\r | |
1476 | startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1477 | startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r |
9547ee89 | 1478 | pulse_len = RC6_BIT_LEN;\r |
1479 | pause_len = RC6_BIT_LEN;\r | |
1480 | has_stop_bit = RC6_STOP_BIT;\r | |
1481 | complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;\r | |
1482 | n_auto_repetitions = 1; // 1 frame\r | |
1483 | auto_repetition_pause_len = 0;\r | |
1484 | repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r | |
1485 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r | |
1486 | break;\r | |
1487 | }\r | |
1488 | #endif\r | |
4225a882 | 1489 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r |
1490 | case IRMP_DENON_PROTOCOL:\r | |
1491 | {\r | |
a7054daf | 1492 | startbit_pulse_len = 0x00;\r |
1493 | startbit_pause_len = 0x00;\r | |
1494 | pulse_1_len = DENON_PULSE_LEN;\r | |
53c11f07 | 1495 | pause_1_len = DENON_1_PAUSE_LEN - 1;\r |
a7054daf | 1496 | pulse_0_len = DENON_PULSE_LEN;\r |
53c11f07 | 1497 | pause_0_len = DENON_0_PAUSE_LEN - 1;\r |
a7054daf | 1498 | has_stop_bit = DENON_STOP_BIT;\r |
1499 | complete_data_len = DENON_COMPLETE_DATA_LEN;\r | |
1500 | n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command\r | |
1501 | auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame\r | |
1502 | repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r | |
779fbc81 | 1503 | irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better\r |
4225a882 | 1504 | break;\r |
1505 | }\r | |
1506 | #endif\r | |
beda975f | 1507 | #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r |
1508 | case IRMP_THOMSON_PROTOCOL:\r | |
1509 | {\r | |
1510 | startbit_pulse_len = 0x00;\r | |
1511 | startbit_pause_len = 0x00;\r | |
1512 | pulse_1_len = THOMSON_PULSE_LEN;\r | |
1513 | pause_1_len = THOMSON_1_PAUSE_LEN - 1;\r | |
1514 | pulse_0_len = THOMSON_PULSE_LEN;\r | |
1515 | pause_0_len = THOMSON_0_PAUSE_LEN - 1;\r | |
1516 | has_stop_bit = THOMSON_STOP_BIT;\r | |
1517 | complete_data_len = THOMSON_COMPLETE_DATA_LEN;\r | |
1518 | n_auto_repetitions = THOMSON_FRAMES; // only 1 frame\r | |
1519 | auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;\r | |
1520 | repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r | |
1521 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1522 | break;\r | |
1523 | }\r | |
1524 | #endif\r | |
4225a882 | 1525 | #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r |
1526 | case IRMP_NUBERT_PROTOCOL:\r | |
1527 | {\r | |
a7054daf | 1528 | startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;\r |
53c11f07 | 1529 | startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;\r |
a7054daf | 1530 | pulse_1_len = NUBERT_1_PULSE_LEN;\r |
53c11f07 | 1531 | pause_1_len = NUBERT_1_PAUSE_LEN - 1;\r |
a7054daf | 1532 | pulse_0_len = NUBERT_0_PULSE_LEN;\r |
53c11f07 | 1533 | pause_0_len = NUBERT_0_PAUSE_LEN - 1;\r |
a7054daf | 1534 | has_stop_bit = NUBERT_STOP_BIT;\r |
1535 | complete_data_len = NUBERT_COMPLETE_DATA_LEN;\r | |
1536 | n_auto_repetitions = NUBERT_FRAMES; // 2 frames\r | |
1537 | auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r | |
1538 | repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;\r | |
4225a882 | 1539 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r |
1540 | break;\r | |
1541 | }\r | |
5481e9cd | 1542 | #endif\r |
1543 | #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r | |
1544 | case IRMP_BANG_OLUFSEN_PROTOCOL:\r | |
1545 | {\r | |
a7054daf | 1546 | startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;\r |
53c11f07 | 1547 | startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;\r |
a7054daf | 1548 | pulse_1_len = BANG_OLUFSEN_PULSE_LEN;\r |
53c11f07 | 1549 | pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;\r |
a7054daf | 1550 | pulse_0_len = BANG_OLUFSEN_PULSE_LEN;\r |
53c11f07 | 1551 | pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;\r |
a7054daf | 1552 | has_stop_bit = BANG_OLUFSEN_STOP_BIT;\r |
1553 | complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;\r | |
1554 | n_auto_repetitions = 1; // 1 frame\r | |
1555 | auto_repetition_pause_len = 0;\r | |
1556 | repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;\r | |
1557 | last_bit_value = 0;\r | |
5481e9cd | 1558 | irsnd_set_freq (IRSND_FREQ_455_KHZ);\r |
1559 | break;\r | |
1560 | }\r | |
5b437ff6 | 1561 | #endif\r |
1562 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r | |
1563 | case IRMP_GRUNDIG_PROTOCOL:\r | |
1564 | {\r | |
89e8cafb | 1565 | startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r |
1566 | startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r | |
1567 | pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1568 | pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1569 | has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r | |
a7054daf | 1570 | complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;\r |
1571 | n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames\r | |
1572 | auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r | |
a48187fa | 1573 | repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r |
d155e9ab | 1574 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
a48187fa | 1575 | break;\r |
1576 | }\r | |
1577 | #endif\r | |
1578 | #if IRSND_SUPPORT_IR60_PROTOCOL == 1\r | |
1579 | case IRMP_IR60_PROTOCOL:\r | |
1580 | {\r | |
1581 | startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1582 | startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r | |
1583 | pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1584 | pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1585 | has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r | |
1586 | complete_data_len = IR60_COMPLETE_DATA_LEN;\r | |
1587 | n_auto_repetitions = IR60_FRAMES; // 2 frames\r | |
1588 | auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r | |
1589 | repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r | |
1590 | irsnd_set_freq (IRSND_FREQ_30_KHZ);\r | |
d155e9ab | 1591 | break;\r |
1592 | }\r | |
1593 | #endif\r | |
1594 | #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r | |
1595 | case IRMP_NOKIA_PROTOCOL:\r | |
1596 | {\r | |
89e8cafb | 1597 | startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r |
1598 | startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r | |
1599 | pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1600 | pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
1601 | has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r | |
a7054daf | 1602 | complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r |
08f2dd9d | 1603 | n_auto_repetitions = NOKIA_FRAMES; // 2 frames\r |
1604 | auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause\r | |
1605 | repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r | |
d155e9ab | 1606 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
5b437ff6 | 1607 | break;\r |
1608 | }\r | |
a7054daf | 1609 | #endif\r |
1610 | #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r | |
1611 | case IRMP_SIEMENS_PROTOCOL:\r | |
1612 | {\r | |
1613 | startbit_pulse_len = SIEMENS_BIT_LEN;\r | |
1614 | startbit_pause_len = SIEMENS_BIT_LEN;\r | |
1615 | pulse_len = SIEMENS_BIT_LEN;\r | |
1616 | pause_len = SIEMENS_BIT_LEN;\r | |
02ccdb69 | 1617 | has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r |
a7054daf | 1618 | complete_data_len = SIEMENS_COMPLETE_DATA_LEN - 1;\r |
1619 | n_auto_repetitions = 1; // 1 frame\r | |
1620 | auto_repetition_pause_len = 0;\r | |
1621 | repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;\r | |
1622 | irsnd_set_freq (IRSND_FREQ_36_KHZ);\r | |
1623 | break;\r | |
1624 | }\r | |
b5ea7869 | 1625 | #endif\r |
48664931 | 1626 | #if IRSND_SUPPORT_FDC_PROTOCOL == 1\r |
1627 | case IRMP_FDC_PROTOCOL:\r | |
b5ea7869 | 1628 | {\r |
48664931 | 1629 | startbit_pulse_len = FDC_START_BIT_PULSE_LEN;\r |
53c11f07 | 1630 | startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;\r |
48664931 | 1631 | complete_data_len = FDC_COMPLETE_DATA_LEN;\r |
1632 | pulse_1_len = FDC_PULSE_LEN;\r | |
53c11f07 | 1633 | pause_1_len = FDC_1_PAUSE_LEN - 1;\r |
48664931 | 1634 | pulse_0_len = FDC_PULSE_LEN;\r |
53c11f07 | 1635 | pause_0_len = FDC_0_PAUSE_LEN - 1;\r |
48664931 | 1636 | has_stop_bit = FDC_STOP_BIT;\r |
b5ea7869 | 1637 | n_auto_repetitions = 1; // 1 frame\r |
1638 | auto_repetition_pause_len = 0;\r | |
48664931 | 1639 | repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;\r |
b5ea7869 | 1640 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r |
1641 | break;\r | |
1642 | }\r | |
c7c9a4a1 | 1643 | #endif\r |
1644 | #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r | |
1645 | case IRMP_RCCAR_PROTOCOL:\r | |
1646 | {\r | |
1647 | startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1648 | startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;\r |
c7c9a4a1 | 1649 | complete_data_len = RCCAR_COMPLETE_DATA_LEN;\r |
1650 | pulse_1_len = RCCAR_PULSE_LEN;\r | |
53c11f07 | 1651 | pause_1_len = RCCAR_1_PAUSE_LEN - 1;\r |
c7c9a4a1 | 1652 | pulse_0_len = RCCAR_PULSE_LEN;\r |
53c11f07 | 1653 | pause_0_len = RCCAR_0_PAUSE_LEN - 1;\r |
c7c9a4a1 | 1654 | has_stop_bit = RCCAR_STOP_BIT;\r |
1655 | n_auto_repetitions = 1; // 1 frame\r | |
1656 | auto_repetition_pause_len = 0;\r | |
1657 | repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;\r | |
1658 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1659 | break;\r | |
1660 | }\r | |
4225a882 | 1661 | #endif\r |
c7a47e89 | 1662 | #if IRSND_SUPPORT_JVC_PROTOCOL == 1\r |
1663 | case IRMP_JVC_PROTOCOL:\r | |
1664 | {\r | |
1665 | if (repeat_counter != 0) // skip start bit if repetition frame\r | |
1666 | {\r | |
1667 | current_bit = 0;\r | |
1668 | }\r | |
1669 | \r | |
1670 | startbit_pulse_len = JVC_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1671 | startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;\r |
c7a47e89 | 1672 | complete_data_len = JVC_COMPLETE_DATA_LEN;\r |
1673 | pulse_1_len = JVC_PULSE_LEN;\r | |
53c11f07 | 1674 | pause_1_len = JVC_1_PAUSE_LEN - 1;\r |
c7a47e89 | 1675 | pulse_0_len = JVC_PULSE_LEN;\r |
53c11f07 | 1676 | pause_0_len = JVC_0_PAUSE_LEN - 1;\r |
c7a47e89 | 1677 | has_stop_bit = JVC_STOP_BIT;\r |
1678 | n_auto_repetitions = 1; // 1 frame\r | |
1679 | auto_repetition_pause_len = 0;\r | |
1680 | repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;\r | |
1681 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
c7a47e89 | 1682 | break;\r |
1683 | }\r | |
1684 | #endif\r | |
9405f84a | 1685 | #if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r |
1686 | case IRMP_NIKON_PROTOCOL:\r | |
1687 | {\r | |
1688 | startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;\r | |
53c11f07 | 1689 | startbit_pause_len = 271 - 1; // NIKON_START_BIT_PAUSE_LEN;\r |
9405f84a | 1690 | complete_data_len = NIKON_COMPLETE_DATA_LEN;\r |
1691 | pulse_1_len = NIKON_PULSE_LEN;\r | |
53c11f07 | 1692 | pause_1_len = NIKON_1_PAUSE_LEN - 1;\r |
9405f84a | 1693 | pulse_0_len = NIKON_PULSE_LEN;\r |
53c11f07 | 1694 | pause_0_len = NIKON_0_PAUSE_LEN - 1;\r |
9405f84a | 1695 | has_stop_bit = NIKON_STOP_BIT;\r |
1696 | n_auto_repetitions = 1; // 1 frame\r | |
1697 | auto_repetition_pause_len = 0;\r | |
1698 | repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;\r | |
1699 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
9405f84a | 1700 | break;\r |
1701 | }\r | |
1702 | #endif\r | |
f50e01e7 | 1703 | #if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r |
1704 | case IRMP_LEGO_PROTOCOL:\r | |
1705 | {\r | |
1706 | startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;\r | |
1707 | startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;\r | |
1708 | complete_data_len = LEGO_COMPLETE_DATA_LEN;\r | |
1709 | pulse_1_len = LEGO_PULSE_LEN;\r | |
1710 | pause_1_len = LEGO_1_PAUSE_LEN - 1;\r | |
1711 | pulse_0_len = LEGO_PULSE_LEN;\r | |
1712 | pause_0_len = LEGO_0_PAUSE_LEN - 1;\r | |
1713 | has_stop_bit = LEGO_STOP_BIT;\r | |
1714 | n_auto_repetitions = 1; // 1 frame\r | |
1715 | auto_repetition_pause_len = 0;\r | |
1716 | repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;\r | |
1717 | irsnd_set_freq (IRSND_FREQ_38_KHZ);\r | |
1718 | break;\r | |
1719 | }\r | |
1720 | #endif\r | |
4225a882 | 1721 | default:\r |
1722 | {\r | |
1723 | irsnd_busy = FALSE;\r | |
1724 | break;\r | |
1725 | }\r | |
1726 | }\r | |
1727 | }\r | |
1728 | }\r | |
1729 | \r | |
1730 | if (irsnd_busy)\r | |
1731 | {\r | |
1732 | new_frame = FALSE;\r | |
a7054daf | 1733 | \r |
4225a882 | 1734 | switch (irsnd_protocol)\r |
1735 | {\r | |
1736 | #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r | |
1737 | case IRMP_SIRCS_PROTOCOL:\r | |
1738 | #endif\r | |
1739 | #if IRSND_SUPPORT_NEC_PROTOCOL == 1\r | |
1740 | case IRMP_NEC_PROTOCOL:\r | |
1741 | #endif\r | |
7644ac04 | 1742 | #if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r |
1743 | case IRMP_NEC16_PROTOCOL:\r | |
1744 | #endif\r | |
1745 | #if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r | |
1746 | case IRMP_NEC42_PROTOCOL:\r | |
1747 | #endif\r | |
4225a882 | 1748 | #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r |
1749 | case IRMP_SAMSUNG_PROTOCOL:\r | |
1750 | case IRMP_SAMSUNG32_PROTOCOL:\r | |
1751 | #endif\r | |
1752 | #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r | |
1753 | case IRMP_MATSUSHITA_PROTOCOL:\r | |
1754 | #endif\r | |
770a1a9d | 1755 | #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r |
1756 | case IRMP_KASEIKYO_PROTOCOL:\r | |
1757 | #endif\r | |
4225a882 | 1758 | #if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r |
1759 | case IRMP_RECS80_PROTOCOL:\r | |
1760 | #endif\r | |
1761 | #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r | |
1762 | case IRMP_RECS80EXT_PROTOCOL:\r | |
1763 | #endif\r | |
1764 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r | |
1765 | case IRMP_DENON_PROTOCOL:\r | |
1766 | #endif\r | |
beda975f | 1767 | #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r |
1768 | case IRMP_THOMSON_PROTOCOL:\r | |
1769 | #endif\r | |
4225a882 | 1770 | #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r |
1771 | case IRMP_NUBERT_PROTOCOL:\r | |
5481e9cd | 1772 | #endif\r |
1773 | #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r | |
1774 | case IRMP_BANG_OLUFSEN_PROTOCOL:\r | |
4225a882 | 1775 | #endif\r |
c7c9a4a1 | 1776 | #if IRSND_SUPPORT_FDC_PROTOCOL == 1\r |
48664931 | 1777 | case IRMP_FDC_PROTOCOL:\r |
b5ea7869 | 1778 | #endif\r |
c7c9a4a1 | 1779 | #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r |
1780 | case IRMP_RCCAR_PROTOCOL:\r | |
1781 | #endif\r | |
c7a47e89 | 1782 | #if IRSND_SUPPORT_JVC_PROTOCOL == 1\r |
1783 | case IRMP_JVC_PROTOCOL:\r | |
1784 | #endif\r | |
9405f84a | 1785 | #if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r |
1786 | case IRMP_NIKON_PROTOCOL:\r | |
1787 | #endif\r | |
f50e01e7 | 1788 | #if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r |
1789 | case IRMP_LEGO_PROTOCOL:\r | |
1790 | #endif\r | |
a7054daf | 1791 | \r |
1792 | \r | |
7644ac04 | 1793 | #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \\r |
1794 | IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || \\r | |
770a1a9d | 1795 | IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \\r |
c7a47e89 | 1796 | IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || \\r |
beda975f | 1797 | IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 \r |
4225a882 | 1798 | {\r |
08f2dd9d | 1799 | #if IRSND_SUPPORT_DENON_PROTOCOL == 1\r |
1800 | if (irsnd_protocol == IRMP_DENON_PROTOCOL)\r | |
1801 | {\r | |
1802 | if (auto_repetition_pause_len > 0) // 2nd frame distance counts from beginning of 1st frame!\r | |
1803 | {\r | |
1804 | auto_repetition_pause_len--;\r | |
1805 | }\r | |
1806 | \r | |
1807 | if (repeat_frame_pause_len > 0) // frame repeat distance counts from beginning of 1st frame!\r | |
1808 | {\r | |
1809 | repeat_frame_pause_len--;\r | |
1810 | }\r | |
1811 | }\r | |
1812 | #endif\r | |
1813 | \r | |
5481e9cd | 1814 | if (pulse_counter == 0)\r |
4225a882 | 1815 | {\r |
5481e9cd | 1816 | if (current_bit == 0xFF) // send start bit\r |
1817 | {\r | |
1818 | pulse_len = startbit_pulse_len;\r | |
1819 | pause_len = startbit_pause_len;\r | |
1820 | }\r | |
1821 | else if (current_bit < complete_data_len) // send n'th bit\r | |
4225a882 | 1822 | {\r |
5481e9cd | 1823 | #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r |
1824 | if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)\r | |
4225a882 | 1825 | {\r |
5481e9cd | 1826 | if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits\r |
1827 | {\r | |
1828 | pulse_len = SAMSUNG_PULSE_LEN;\r | |
1829 | pause_len = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ?\r | |
53c11f07 | 1830 | (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r |
5481e9cd | 1831 | }\r |
1832 | else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)\r | |
1833 | {\r | |
1834 | pulse_len = SAMSUNG_PULSE_LEN;\r | |
53c11f07 | 1835 | pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r |
5481e9cd | 1836 | }\r |
1837 | else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit\r | |
1838 | {\r | |
1839 | uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r | |
1840 | \r | |
1841 | pulse_len = SAMSUNG_PULSE_LEN;\r | |
1842 | pause_len = (irsnd_buffer[cur_bit / 8] & (1<<(7-(cur_bit % 8)))) ?\r | |
53c11f07 | 1843 | (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r |
5481e9cd | 1844 | }\r |
4225a882 | 1845 | }\r |
5481e9cd | 1846 | else\r |
1847 | #endif\r | |
1848 | \r | |
7644ac04 | 1849 | #if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r |
1850 | if (irsnd_protocol == IRMP_NEC16_PROTOCOL)\r | |
1851 | {\r | |
1852 | if (current_bit < NEC16_ADDRESS_LEN) // send address bits\r | |
1853 | {\r | |
1854 | pulse_len = NEC_PULSE_LEN;\r | |
1855 | pause_len = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ?\r | |
1856 | (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r | |
1857 | }\r | |
1858 | else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)\r | |
1859 | {\r | |
1860 | pulse_len = NEC_PULSE_LEN;\r | |
1861 | pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r | |
1862 | }\r | |
1863 | else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit\r | |
1864 | {\r | |
1865 | uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r | |
1866 | \r | |
1867 | pulse_len = NEC_PULSE_LEN;\r | |
1868 | pause_len = (irsnd_buffer[cur_bit / 8] & (1<<(7-(cur_bit % 8)))) ?\r | |
1869 | (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r | |
1870 | }\r | |
1871 | }\r | |
1872 | else\r | |
1873 | #endif\r | |
1874 | \r | |
5481e9cd | 1875 | #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r |
1876 | if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)\r | |
4225a882 | 1877 | {\r |
5481e9cd | 1878 | if (current_bit == 0) // send 2nd start bit\r |
1879 | {\r | |
1880 | pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r | |
53c11f07 | 1881 | pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r |
5481e9cd | 1882 | }\r |
1883 | else if (current_bit == 1) // send 3rd start bit\r | |
1884 | {\r | |
1885 | pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;\r | |
53c11f07 | 1886 | pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;\r |
5481e9cd | 1887 | }\r |
1888 | else if (current_bit == 2) // send 4th start bit\r | |
1889 | {\r | |
1890 | pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r | |
53c11f07 | 1891 | pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r |
5481e9cd | 1892 | }\r |
1893 | else if (current_bit == 19) // send trailer bit\r | |
1894 | {\r | |
1895 | pulse_len = BANG_OLUFSEN_PULSE_LEN;\r | |
53c11f07 | 1896 | pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;\r |
5481e9cd | 1897 | }\r |
1898 | else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit\r | |
1899 | {\r | |
1900 | uint8_t cur_bit_value = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? 1 : 0;\r | |
1901 | pulse_len = BANG_OLUFSEN_PULSE_LEN;\r | |
1902 | \r | |
1903 | if (cur_bit_value == last_bit_value)\r | |
1904 | {\r | |
53c11f07 | 1905 | pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;\r |
5481e9cd | 1906 | }\r |
1907 | else\r | |
1908 | {\r | |
53c11f07 | 1909 | pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);\r |
5481e9cd | 1910 | last_bit_value = cur_bit_value;\r |
1911 | }\r | |
1912 | }\r | |
4225a882 | 1913 | }\r |
5481e9cd | 1914 | else\r |
1915 | #endif\r | |
1916 | if (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8))))\r | |
4225a882 | 1917 | {\r |
5481e9cd | 1918 | pulse_len = pulse_1_len;\r |
1919 | pause_len = pause_1_len;\r | |
1920 | }\r | |
1921 | else\r | |
1922 | {\r | |
1923 | pulse_len = pulse_0_len;\r | |
1924 | pause_len = pause_0_len;\r | |
4225a882 | 1925 | }\r |
1926 | }\r | |
5481e9cd | 1927 | else if (has_stop_bit) // send stop bit\r |
4225a882 | 1928 | {\r |
1929 | pulse_len = pulse_0_len;\r | |
4225a882 | 1930 | \r |
a7054daf | 1931 | if (auto_repetition_counter < n_auto_repetitions)\r |
5481e9cd | 1932 | {\r |
1933 | pause_len = pause_0_len;\r | |
1934 | }\r | |
1935 | else\r | |
1936 | {\r | |
1937 | pause_len = 255; // last frame: pause of 255\r | |
1938 | }\r | |
4225a882 | 1939 | }\r |
1940 | }\r | |
1941 | \r | |
1942 | if (pulse_counter < pulse_len)\r | |
1943 | {\r | |
1944 | if (pulse_counter == 0)\r | |
1945 | {\r | |
1946 | irsnd_on ();\r | |
1947 | }\r | |
1948 | pulse_counter++;\r | |
1949 | }\r | |
1950 | else if (pause_counter < pause_len)\r | |
1951 | {\r | |
1952 | if (pause_counter == 0)\r | |
1953 | {\r | |
1954 | irsnd_off ();\r | |
1955 | }\r | |
1956 | pause_counter++;\r | |
1957 | }\r | |
1958 | else\r | |
1959 | {\r | |
1960 | current_bit++;\r | |
1961 | \r | |
1962 | if (current_bit >= complete_data_len + has_stop_bit)\r | |
1963 | {\r | |
1964 | current_bit = 0xFF;\r | |
a7054daf | 1965 | auto_repetition_counter++;\r |
4225a882 | 1966 | \r |
a7054daf | 1967 | if (auto_repetition_counter == n_auto_repetitions)\r |
4225a882 | 1968 | {\r |
1969 | irsnd_busy = FALSE;\r | |
a7054daf | 1970 | auto_repetition_counter = 0;\r |
4225a882 | 1971 | }\r |
1972 | new_frame = TRUE;\r | |
1973 | }\r | |
1974 | \r | |
1975 | pulse_counter = 0;\r | |
1976 | pause_counter = 0;\r | |
1977 | }\r | |
1978 | break;\r | |
1979 | }\r | |
a7054daf | 1980 | #endif\r |
1981 | \r | |
4225a882 | 1982 | #if IRSND_SUPPORT_RC5_PROTOCOL == 1\r |
1983 | case IRMP_RC5_PROTOCOL:\r | |
a7054daf | 1984 | #endif\r |
9547ee89 | 1985 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1\r |
1986 | case IRMP_RC6_PROTOCOL:\r | |
1987 | #endif\r | |
1988 | #if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r | |
1989 | case IRMP_RC6A_PROTOCOL:\r | |
1990 | #endif\r | |
a7054daf | 1991 | #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r |
1992 | case IRMP_SIEMENS_PROTOCOL:\r | |
1993 | #endif\r | |
1994 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r | |
1995 | case IRMP_GRUNDIG_PROTOCOL:\r | |
1996 | #endif\r | |
a48187fa | 1997 | #if IRSND_SUPPORT_IR60_PROTOCOL == 1\r |
1998 | case IRMP_IR60_PROTOCOL:\r | |
1999 | #endif\r | |
a7054daf | 2000 | #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
2001 | case IRMP_NOKIA_PROTOCOL:\r | |
2002 | #endif\r | |
4225a882 | 2003 | \r |
9547ee89 | 2004 | #if IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r |
a48187fa | 2005 | IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
a7054daf | 2006 | {\r |
2007 | if (pulse_counter == pulse_len && pause_counter == pause_len)\r | |
4225a882 | 2008 | {\r |
a7054daf | 2009 | current_bit++;\r |
4225a882 | 2010 | \r |
a7054daf | 2011 | if (current_bit >= complete_data_len)\r |
4225a882 | 2012 | {\r |
a7054daf | 2013 | current_bit = 0xFF;\r |
2014 | \r | |
a48187fa | 2015 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
2016 | if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r | |
4225a882 | 2017 | {\r |
a7054daf | 2018 | auto_repetition_counter++;\r |
2019 | \r | |
2020 | if (repeat_counter > 0)\r | |
2021 | { // set 117 msec pause time\r | |
89e8cafb | 2022 | auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;\r |
a7054daf | 2023 | }\r |
2024 | \r | |
2025 | if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame\r | |
2026 | {\r | |
2027 | n_auto_repetitions++; // increment number of auto repetitions\r | |
2028 | repeat_counter++;\r | |
2029 | }\r | |
2030 | else if (auto_repetition_counter == n_auto_repetitions)\r | |
2031 | {\r | |
2032 | irsnd_busy = FALSE;\r | |
2033 | auto_repetition_counter = 0;\r | |
2034 | }\r | |
4225a882 | 2035 | }\r |
a7054daf | 2036 | else\r |
2037 | #endif\r | |
4225a882 | 2038 | {\r |
a7054daf | 2039 | irsnd_busy = FALSE;\r |
4225a882 | 2040 | }\r |
4225a882 | 2041 | \r |
4225a882 | 2042 | new_frame = TRUE;\r |
2043 | irsnd_off ();\r | |
2044 | }\r | |
2045 | \r | |
2046 | pulse_counter = 0;\r | |
2047 | pause_counter = 0;\r | |
2048 | }\r | |
5b437ff6 | 2049 | \r |
a7054daf | 2050 | if (! new_frame)\r |
5b437ff6 | 2051 | {\r |
a7054daf | 2052 | uint8_t first_pulse;\r |
5b437ff6 | 2053 | \r |
a48187fa | 2054 | #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
2055 | if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r | |
5b437ff6 | 2056 | {\r |
a7054daf | 2057 | if (current_bit == 0xFF || // start bit of start-frame\r |
2058 | (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)\r | |
a48187fa | 2059 | (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)\r |
a7054daf | 2060 | (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)\r |
5b437ff6 | 2061 | {\r |
a7054daf | 2062 | pulse_len = startbit_pulse_len;\r |
2063 | pause_len = startbit_pause_len;\r | |
2064 | first_pulse = TRUE;\r | |
5b437ff6 | 2065 | }\r |
a7054daf | 2066 | else // send n'th bit\r |
5b437ff6 | 2067 | {\r |
89e8cafb | 2068 | pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r |
2069 | pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r | |
a7054daf | 2070 | first_pulse = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? TRUE : FALSE;\r |
5b437ff6 | 2071 | }\r |
5b437ff6 | 2072 | }\r |
9547ee89 | 2073 | else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||\r |
2074 | // irsnd_protocol == IRMP_SIEMENS_PROTOCOL)\r | |
a7054daf | 2075 | #endif\r |
5b437ff6 | 2076 | {\r |
a7054daf | 2077 | if (current_bit == 0xFF) // 1 start bit\r |
2078 | {\r | |
9547ee89 | 2079 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r |
2080 | if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r | |
2081 | {\r | |
2082 | pulse_len = startbit_pulse_len;\r | |
2083 | pause_len = startbit_pause_len;\r | |
2084 | }\r | |
2085 | #endif\r | |
a7054daf | 2086 | first_pulse = TRUE;\r |
2087 | }\r | |
2088 | else // send n'th bit\r | |
2089 | {\r | |
9547ee89 | 2090 | #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r |
2091 | if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r | |
2092 | {\r | |
2093 | pulse_len = RC6_BIT_LEN;\r | |
2094 | pause_len = RC6_BIT_LEN;\r | |
2095 | \r | |
2096 | if (irsnd_protocol == IRMP_RC6_PROTOCOL)\r | |
2097 | {\r | |
2098 | if (current_bit == 4) // toggle bit (double len)\r | |
2099 | {\r | |
2100 | pulse_len = 2 * RC6_BIT_LEN;\r | |
2101 | pause_len = 2 * RC6_BIT_LEN;\r | |
2102 | }\r | |
2103 | }\r | |
2104 | else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)\r | |
2105 | {\r | |
2106 | if (current_bit == 4) // toggle bit (double len)\r | |
2107 | {\r | |
2108 | pulse_len = 2 * RC6_BIT_LEN + RC6_BIT_LEN; // hack!\r | |
2109 | pause_len = 2 * RC6_BIT_LEN;\r | |
2110 | }\r | |
2111 | else if (current_bit == 5) // toggle bit (double len)\r | |
2112 | {\r | |
2113 | pause_len = 2 * RC6_BIT_LEN;\r | |
2114 | }\r | |
2115 | }\r | |
2116 | }\r | |
2117 | #endif\r | |
a7054daf | 2118 | first_pulse = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? TRUE : FALSE;\r |
2119 | }\r | |
5b437ff6 | 2120 | \r |
a7054daf | 2121 | if (irsnd_protocol == IRMP_RC5_PROTOCOL)\r |
2122 | {\r | |
2123 | first_pulse = first_pulse ? FALSE : TRUE;\r | |
2124 | }\r | |
2125 | }\r | |
5b437ff6 | 2126 | \r |
2127 | if (first_pulse)\r | |
2128 | {\r | |
a7054daf | 2129 | if (pulse_counter < pulse_len)\r |
5b437ff6 | 2130 | {\r |
2131 | if (pulse_counter == 0)\r | |
2132 | {\r | |
2133 | irsnd_on ();\r | |
2134 | }\r | |
2135 | pulse_counter++;\r | |
2136 | }\r | |
a7054daf | 2137 | else // if (pause_counter < pause_len)\r |
5b437ff6 | 2138 | {\r |
2139 | if (pause_counter == 0)\r | |
2140 | {\r | |
2141 | irsnd_off ();\r | |
2142 | }\r | |
2143 | pause_counter++;\r | |
2144 | }\r | |
5b437ff6 | 2145 | }\r |
2146 | else\r | |
2147 | {\r | |
a7054daf | 2148 | if (pause_counter < pause_len)\r |
5b437ff6 | 2149 | {\r |
2150 | if (pause_counter == 0)\r | |
2151 | {\r | |
2152 | irsnd_off ();\r | |
2153 | }\r | |
2154 | pause_counter++;\r | |
2155 | }\r | |
a7054daf | 2156 | else // if (pulse_counter < pulse_len)\r |
5b437ff6 | 2157 | {\r |
2158 | if (pulse_counter == 0)\r | |
2159 | {\r | |
2160 | irsnd_on ();\r | |
2161 | }\r | |
2162 | pulse_counter++;\r | |
2163 | }\r | |
5b437ff6 | 2164 | }\r |
2165 | }\r | |
2166 | break;\r | |
2167 | }\r | |
9547ee89 | 2168 | #endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||\r |
a48187fa | 2169 | // IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r |
5b437ff6 | 2170 | \r |
4225a882 | 2171 | default:\r |
2172 | {\r | |
2173 | irsnd_busy = FALSE;\r | |
2174 | break;\r | |
2175 | }\r | |
2176 | }\r | |
2177 | }\r | |
a7054daf | 2178 | \r |
2179 | if (! irsnd_busy)\r | |
2180 | {\r | |
2181 | if (repeat_counter < n_repeat_frames)\r | |
2182 | {\r | |
c7c9a4a1 | 2183 | #if IRSND_SUPPORT_FDC_PROTOCOL == 1\r |
2184 | if (irsnd_protocol == IRMP_FDC_PROTOCOL)\r | |
2185 | {\r | |
2186 | irsnd_buffer[2] |= 0x0F;\r | |
2187 | }\r | |
2188 | #endif\r | |
a7054daf | 2189 | repeat_counter++;\r |
2190 | irsnd_busy = TRUE;\r | |
2191 | }\r | |
2192 | else\r | |
2193 | {\r | |
9c86ff1a | 2194 | irsnd_busy = TRUE; //Rainer\r |
0f700c8e | 2195 | send_trailer = TRUE;\r |
a7054daf | 2196 | n_repeat_frames = 0;\r |
2197 | repeat_counter = 0;\r | |
2198 | }\r | |
2199 | }\r | |
4225a882 | 2200 | }\r |
2201 | \r | |
2202 | #ifdef DEBUG\r | |
2203 | if (irsnd_is_on)\r | |
2204 | {\r | |
2205 | putchar ('0');\r | |
2206 | }\r | |
2207 | else\r | |
2208 | {\r | |
2209 | putchar ('1');\r | |
2210 | }\r | |
2211 | #endif\r | |
2212 | \r | |
2213 | return irsnd_busy;\r | |
2214 | }\r | |
2215 | \r | |
2216 | #ifdef DEBUG\r | |
2217 | \r | |
2218 | // main function - for unix/linux + windows only!\r | |
2219 | // AVR: see main.c!\r | |
2220 | // Compile it under linux with:\r | |
2221 | // cc irsnd.c -o irsnd\r | |
2222 | //\r | |
2223 | // usage: ./irsnd protocol hex-address hex-command >filename\r | |
2224 | \r | |
2225 | int\r | |
2226 | main (int argc, char ** argv)\r | |
2227 | {\r | |
4225a882 | 2228 | int protocol;\r |
2229 | int address;\r | |
2230 | int command;\r | |
4225a882 | 2231 | IRMP_DATA irmp_data;\r |
2232 | \r | |
a7054daf | 2233 | if (argc != 4 && argc != 5)\r |
4225a882 | 2234 | {\r |
a7054daf | 2235 | fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);\r |
4225a882 | 2236 | return 1;\r |
2237 | }\r | |
2238 | \r | |
2239 | if (sscanf (argv[1], "%d", &protocol) == 1 &&\r | |
2240 | sscanf (argv[2], "%x", &address) == 1 &&\r | |
2241 | sscanf (argv[3], "%x", &command) == 1)\r | |
2242 | {\r | |
2243 | irmp_data.protocol = protocol;\r | |
2244 | irmp_data.address = address;\r | |
2245 | irmp_data.command = command;\r | |
2246 | \r | |
a7054daf | 2247 | if (argc == 5)\r |
2248 | {\r | |
2249 | irmp_data.flags = atoi (argv[4]);\r | |
2250 | }\r | |
2251 | else\r | |
2252 | {\r | |
2253 | irmp_data.flags = 0;\r | |
2254 | }\r | |
2255 | \r | |
4225a882 | 2256 | irsnd_init ();\r |
2257 | \r | |
879b06c2 | 2258 | (void) irsnd_send_data (&irmp_data, TRUE);\r |
4225a882 | 2259 | \r |
a7054daf | 2260 | while (irsnd_busy)\r |
2261 | {\r | |
2262 | irsnd_ISR ();\r | |
2263 | }\r | |
beda975f | 2264 | \r |
4225a882 | 2265 | putchar ('\n');\r |
2266 | }\r | |
2267 | else\r | |
2268 | {\r | |
2269 | fprintf (stderr, "%s: wrong arguments\n", argv[0]);\r | |
2270 | return 1;\r | |
2271 | }\r | |
2272 | return 0;\r | |
2273 | }\r | |
2274 | \r | |
2275 | #endif // DEBUG\r |