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Version 2.2.2: STM32 port of IRSND.
[irmp.git] / irsnd.c
CommitLineData
4225a882 1/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
2 * @file irsnd.c\r
3 *\r
08f2dd9d 4 * Copyright (c) 2010-2012 Frank Meyer - frank(at)fli4l.de\r
4225a882 5 *\r
7644ac04 6 * Supported mikrocontrollers:\r
7 *\r
476267f4 8 * ATtiny45, ATtiny85\r
9 * ATtiny84\r
7644ac04 10 * ATmega8, ATmega16, ATmega32\r
11 * ATmega162\r
12 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284\r
13 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r
14 *\r
acd29fb9 15 * $Id: irsnd.c,v 1.56 2012/06/05 12:00:46 fm Exp $\r
5481e9cd 16 *\r
4225a882 17 * This program is free software; you can redistribute it and/or modify\r
18 * it under the terms of the GNU General Public License as published by\r
19 * the Free Software Foundation; either version 2 of the License, or\r
20 * (at your option) any later version.\r
21 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
22 */\r
23\r
4225a882 24#include "irsnd.h"\r
25\r
1f54e86c 26/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
27 * ATtiny pin definition of OC0A / OC0B\r
28 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B\r
29 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
30 */\r
08f2dd9d 31#if defined (__AVR_ATtiny84__) // ATtiny84 uses OC0A = PB2 or OC0B = PA7\r
32# if IRSND_OCx == IRSND_OC0A // OC0A\r
33# define IRSND_PORT PORTB // port B\r
34# define IRSND_DDR DDRB // ddr B\r
35# define IRSND_BIT 2 // OC0A\r
36# elif IRSND_OCx == IRSND_OC0B // OC0B\r
37# define IRSND_PORT PORTA // port A\r
38# define IRSND_DDR DDRA // ddr A\r
39# define IRSND_BIT 7 // OC0B\r
40# else\r
41# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
42# endif // IRSND_OCx\r
43#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1\r
44# if IRSND_OCx == IRSND_OC0A // OC0A\r
45# define IRSND_PORT PORTB // port B\r
46# define IRSND_DDR DDRB // ddr B\r
47# define IRSND_BIT 0 // OC0A\r
48# elif IRSND_OCx == IRSND_OC0B // OC0B\r
49# define IRSND_PORT PORTB // port B\r
50# define IRSND_DDR DDRB // ddr B\r
51# define IRSND_BIT 1 // OC0B\r
52# else\r
53# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
54# endif // IRSND_OCx\r
55#elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3\r
56# if IRSND_OCx == IRSND_OC2 // OC0A\r
57# define IRSND_PORT PORTB // port B\r
58# define IRSND_DDR DDRB // ddr B\r
59# define IRSND_BIT 3 // OC0A\r
60# else\r
61# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
62# endif // IRSND_OCx\r
63#elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC2 = PD7\r
64# if IRSND_OCx == IRSND_OC2 // OC2\r
65# define IRSND_PORT PORTD // port D\r
66# define IRSND_DDR DDRD // ddr D\r
67# define IRSND_BIT 7 // OC2\r
68# else\r
69# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
70# endif // IRSND_OCx\r
71#elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0\r
72# if IRSND_OCx == IRSND_OC2 // OC2\r
73# define IRSND_PORT PORTB // port B\r
74# define IRSND_DDR DDRB // ddr B\r
75# define IRSND_BIT 1 // OC2\r
76# elif IRSND_OCx == IRSND_OC0 // OC0\r
77# define IRSND_PORT PORTB // port B\r
78# define IRSND_DDR DDRB // ddr B\r
79# define IRSND_BIT 0 // OC0\r
80# else\r
81# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r
82# endif // IRSND_OCx\r
f50e01e7 83#elif defined (__AVR_ATmega164__) \\r
84 || defined (__AVR_ATmega324__) \\r
85 || defined (__AVR_ATmega644__) \\r
86 || defined (__AVR_ATmega644P__) \\r
0f700c8e 87 || defined (__AVR_ATmega1284__) \\r
08f2dd9d 88 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4\r
89# if IRSND_OCx == IRSND_OC2A // OC2A\r
90# define IRSND_PORT PORTD // port D\r
91# define IRSND_DDR DDRD // ddr D\r
92# define IRSND_BIT 7 // OC2A\r
93# elif IRSND_OCx == IRSND_OC2B // OC2B\r
94# define IRSND_PORT PORTD // port D\r
95# define IRSND_DDR DDRD // ddr D\r
96# define IRSND_BIT 6 // OC2B\r
97# elif IRSND_OCx == IRSND_OC0A // OC0A\r
98# define IRSND_PORT PORTB // port B\r
99# define IRSND_DDR DDRB // ddr B\r
100# define IRSND_BIT 3 // OC0A\r
101# elif IRSND_OCx == IRSND_OC0B // OC0B\r
102# define IRSND_PORT PORTB // port B\r
103# define IRSND_DDR DDRB // ddr B\r
104# define IRSND_BIT 4 // OC0B\r
105# else\r
106# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
107# endif // IRSND_OCx\r
f50e01e7 108#elif defined (__AVR_ATmega48__) \\r
109 || defined (__AVR_ATmega88__) \\r
7644ac04 110 || defined (__AVR_ATmega88P__) \\r
f50e01e7 111 || defined (__AVR_ATmega168__) \\r
1f54e86c 112 || defined (__AVR_ATmega168P__) \\r
08f2dd9d 113 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5\r
114# if IRSND_OCx == IRSND_OC2A // OC2A\r
115# define IRSND_PORT PORTB // port B\r
116# define IRSND_DDR DDRB // ddr B\r
117# define IRSND_BIT 3 // OC2A\r
118# elif IRSND_OCx == IRSND_OC2B // OC2B\r
119# define IRSND_PORT PORTD // port D\r
120# define IRSND_DDR DDRD // ddr D\r
121# define IRSND_BIT 3 // OC2B\r
122# elif IRSND_OCx == IRSND_OC0A // OC0A\r
123# define IRSND_PORT PORTB // port B\r
124# define IRSND_DDR DDRB // ddr B\r
125# define IRSND_BIT 6 // OC0A\r
126# elif IRSND_OCx == IRSND_OC0B // OC0B\r
127# define IRSND_PORT PORTD // port D\r
128# define IRSND_DDR DDRD // ddr D\r
129# define IRSND_BIT 5 // OC0B\r
130# else\r
131# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
132# endif // IRSND_OCx\r
0f700c8e 133#elif defined (__AVR_ATmega8515__) \r
08f2dd9d 134# if IRSND_OCx == IRSND_OC0 \r
135# define IRSND_PORT PORTB // port B\r
136# define IRSND_DDR DDRB // ddr B\r
137# define IRSND_BIT 0 // OC0\r
138# elif IRSND_OCx == IRSND_OC1A \r
139# define IRSND_PORT PORTD // port D\r
140# define IRSND_DDR DDRD // ddr D\r
141# define IRSND_BIT 5 // OC1A\r
142# elif IRSND_OCx == IRSND_OC1B \r
143# define IRSND_PORT PORTE // port E\r
144# define IRSND_DDR DDRE // ddr E\r
145# define IRSND_BIT 2 // OC1E\r
146# else\r
147# error Wrong value for IRSND_OCx, choose IRSND_OC0, IRSND_OC1A, or IRSND_OC1B in irsndconfig.h\r
148# endif // IRSND_OCx\r
9c86ff1a 149#elif defined (PIC_C18) //Microchip C18 compiler\r
150 //Nothing here to do here -> See irsndconfig.h\r
08f2dd9d 151#elif defined (ARM_STM32) //STM32\r
152 //Nothing here to do here -> See irsndconfig.h\r
f50e01e7 153#else\r
08f2dd9d 154# if !defined (unix) && !defined (WIN32)\r
155# error mikrocontroller not defined, please fill in definitions here.\r
156# endif // unix, WIN32\r
f50e01e7 157#endif // __AVR...\r
158\r
9405f84a 159#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
9c86ff1a 160 typedef uint16_t IRSND_PAUSE_LEN;\r
9405f84a 161#else\r
9c86ff1a 162 typedef uint8_t IRSND_PAUSE_LEN;\r
9405f84a 163#endif\r
164\r
f50e01e7 165/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
166 * IR timings\r
167 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
168 */\r
4225a882 169#define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)\r
170#define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)\r
171#define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)\r
172#define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)\r
173#define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)\r
a7054daf 174#define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
175#define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 176\r
177#define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)\r
178#define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)\r
a7054daf 179#define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
4225a882 180#define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)\r
181#define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)\r
182#define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)\r
a7054daf 183#define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 184\r
185#define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)\r
186#define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)\r
187#define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)\r
188#define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)\r
189#define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)\r
a7054daf 190#define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 191\r
a7054daf 192#define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
193#define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 194\r
4225a882 195#define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)\r
196#define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)\r
197#define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)\r
198#define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)\r
199#define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)\r
a7054daf 200#define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 201\r
770a1a9d 202#define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)\r
203#define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)\r
204#define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)\r
205#define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)\r
206#define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)\r
207#define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
208#define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
209\r
4225a882 210#define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)\r
211#define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)\r
212#define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)\r
213#define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)\r
214#define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)\r
a7054daf 215#define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 216\r
217#define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
218#define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
a7054daf 219#define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 220\r
221#define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)\r
222#define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)\r
223#define RC6_TOGGLE_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_TOGGLE_BIT_TIME + 0.5)\r
224#define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)\r
a7054daf 225#define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 226\r
227#define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)\r
228#define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)\r
229#define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)\r
a7054daf 230#define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
231#define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 232\r
beda975f 233#define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)\r
234#define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)\r
235#define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)\r
236#define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
237#define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
238\r
4225a882 239#define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)\r
240#define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)\r
241#define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)\r
242#define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)\r
243#define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)\r
a7054daf 244#define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 245\r
246#define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)\r
247#define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)\r
248#define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)\r
249#define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)\r
250#define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)\r
251#define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)\r
a7054daf 252#define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
253#define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 254\r
5481e9cd 255#define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)\r
256#define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)\r
257#define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)\r
258#define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)\r
259#define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)\r
260#define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)\r
261#define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)\r
262#define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)\r
263#define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)\r
264#define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)\r
265#define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)\r
a7054daf 266#define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5481e9cd 267\r
9c86ff1a 268#define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)\r
269#define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)\r
a7054daf 270#define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
271#define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
89e8cafb 272#define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
a7054daf 273\r
a48187fa 274#define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
275\r
02ccdb69 276#define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
277#define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
278#define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 279\r
9c86ff1a 280\r
08f2dd9d 281#ifdef PIC_C18 // PIC C18\r
282# define IRSND_FREQ_TYPE uint8_t\r
283# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
284# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
285# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
286# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
287# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
288# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
289# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
290#elif defined (ARM_STM32) // STM32\r
291# define IRSND_FREQ_TYPE uint32_t\r
292# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
293# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
294# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
295# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
296# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
297# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
298# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
299#else // AVR\r
300# define IRSND_FREQ_TYPE uint8_t\r
301# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2) - 1)\r
302# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2) - 1)\r
303# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2) - 1)\r
304# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2) - 1)\r
305# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2) - 1)\r
306# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2) - 1)\r
307# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2) - 1)\r
9c86ff1a 308#endif\r
4225a882 309\r
48664931 310#define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)\r
311#define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)\r
312#define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)\r
313#define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)\r
314#define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)\r
315#define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
b5ea7869 316\r
c7c9a4a1 317#define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)\r
318#define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)\r
319#define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)\r
320#define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)\r
321#define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)\r
322#define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
323\r
c7a47e89 324#define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)\r
325#define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)\r
326#define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
327#define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)\r
328#define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)\r
329#define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)\r
330#define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
331\r
9405f84a 332#define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)\r
333#define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)\r
334#define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
335#define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)\r
336#define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)\r
337#define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)\r
f50e01e7 338#define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
339\r
340#define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)\r
341#define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)\r
342#define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
343#define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)\r
344#define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)\r
345#define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)\r
346#define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
9405f84a 347\r
9c86ff1a 348static volatile uint8_t irsnd_busy = 0;\r
349static volatile uint8_t irsnd_protocol = 0;\r
350static volatile uint8_t irsnd_buffer[6] = {0};\r
351static volatile uint8_t irsnd_repeat = 0;\r
4225a882 352static volatile uint8_t irsnd_is_on = FALSE;\r
353\r
f50e01e7 354#if IRSND_USE_CALLBACK == 1\r
355static void (*irsnd_callback_ptr) (uint8_t);\r
356#endif // IRSND_USE_CALLBACK == 1\r
357\r
4225a882 358/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
359 * Switch PWM on\r
360 * @details Switches PWM on with a narrow spike on all 3 channels -> leds glowing\r
361 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
362 */\r
363static void\r
364irsnd_on (void)\r
365{\r
366 if (! irsnd_is_on)\r
367 {\r
368#ifndef DEBUG\r
08f2dd9d 369# if defined(PIC_C18) // PIC C18\r
9c86ff1a 370 IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
08f2dd9d 371# elif defined (ARM_STM32) // STM32\r
acd29fb9 372 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
373 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
374 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r
08f2dd9d 375# else // AVR\r
376# if IRSND_OCx == IRSND_OC2 // use OC2\r
1f54e86c 377 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r
08f2dd9d 378# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
f50e01e7 379 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r
08f2dd9d 380# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
f50e01e7 381 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)\r
08f2dd9d 382# elif IRSND_OCx == IRSND_OC0 // use OC0\r
1f54e86c 383 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0\r
08f2dd9d 384# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
1f54e86c 385 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A\r
08f2dd9d 386# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
1f54e86c 387 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)\r
08f2dd9d 388# else\r
389# error wrong value of IRSND_OCx\r
390# endif // IRSND_OCx\r
391# endif // C18\r
4225a882 392#endif // DEBUG\r
f50e01e7 393\r
394#if IRSND_USE_CALLBACK == 1\r
395 if (irsnd_callback_ptr)\r
396 {\r
397 (*irsnd_callback_ptr) (TRUE);\r
398 }\r
399#endif // IRSND_USE_CALLBACK == 1\r
400\r
4225a882 401 irsnd_is_on = TRUE;\r
402 }\r
403}\r
404\r
405/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
406 * Switch PWM off\r
407 * @details Switches PWM off\r
408 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
409 */\r
410static void\r
411irsnd_off (void)\r
412{\r
413 if (irsnd_is_on)\r
414 {\r
415#ifndef DEBUG\r
9c86ff1a 416 \r
08f2dd9d 417# if defined(PIC_C18) // PIC C18\r
9c86ff1a 418 IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
08f2dd9d 419# elif defined (ARM_STM32) // STM32\r
acd29fb9 420 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r
421 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r
422 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
423 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r
08f2dd9d 424# else //AVR\r
9c86ff1a 425\r
08f2dd9d 426# if IRSND_OCx == IRSND_OC2 // use OC2\r
f50e01e7 427 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.\r
08f2dd9d 428# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
f50e01e7 429 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.\r
08f2dd9d 430# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
f50e01e7 431 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.\r
08f2dd9d 432# elif IRSND_OCx == IRSND_OC0 // use OC0\r
1f54e86c 433 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.\r
08f2dd9d 434# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
1f54e86c 435 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.\r
08f2dd9d 436# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
1f54e86c 437 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.\r
08f2dd9d 438# else\r
439# error wrong value of IRSND_OCx\r
440# endif // IRSND_OCx\r
f50e01e7 441 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
08f2dd9d 442# endif //C18\r
4225a882 443#endif // DEBUG\r
f50e01e7 444\r
445#if IRSND_USE_CALLBACK == 1\r
446 if (irsnd_callback_ptr)\r
447 {\r
448 (*irsnd_callback_ptr) (FALSE);\r
449 }\r
450#endif // IRSND_USE_CALLBACK == 1\r
451\r
4225a882 452 irsnd_is_on = FALSE;\r
453 }\r
454}\r
455\r
456/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
457 * Set PWM frequency\r
458 * @details sets pwm frequency\r
459 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
460 */\r
461static void\r
08f2dd9d 462irsnd_set_freq (IRSND_FREQ_TYPE freq)\r
4225a882 463{\r
464#ifndef DEBUG\r
08f2dd9d 465# if defined(PIC_C18) // PIC C18\r
466 OpenPWM(freq); \r
467 SetDCPWM( (uint16_t) freq * 2); // freq*2 = Duty cycles 50%\r
468# elif defined (ARM_STM32) // STM32\r
37b29f94 469 static uint32_t TimeBaseFreq = 0;\r
08f2dd9d 470\r
471 if (TimeBaseFreq == 0)\r
472 {\r
473 RCC_ClocksTypeDef RCC_ClocksStructure;\r
474 /* Get system clocks and store timer clock in variable */\r
475 RCC_GetClocksFreq(&RCC_ClocksStructure);\r
476# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
37b29f94 477 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
478 {\r
479 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r
480 }\r
481 else\r
482 {\r
483 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;\r
484 }\r
08f2dd9d 485# else\r
37b29f94 486 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
487 {\r
488 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r
489 }\r
490 else\r
491 {\r
492 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;\r
493 }\r
08f2dd9d 494# endif\r
495 }\r
496\r
497 freq = TimeBaseFreq/freq;\r
498\r
37b29f94 499 /* Set frequency */\r
acd29fb9 500 TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
37b29f94 501 /* Set duty cycle */\r
502 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
08f2dd9d 503# else // AVR\r
504\r
505# if IRSND_OCx == IRSND_OC2\r
506 OCR2 = freq; // use register OCR2 for OC2\r
507# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
508 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
509# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
510 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
511# elif IRSND_OCx == IRSND_OC0 // use OC0\r
512 OCR0 = freq; // use register OCR2 for OC2\r
513# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
514 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
515# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
516 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
517# else\r
518# error wrong value of IRSND_OCx\r
519# endif\r
520# endif //PIC_C18\r
4225a882 521#endif // DEBUG\r
522}\r
523\r
524/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
525 * Initialize the PWM\r
526 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels\r
527 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
528 */\r
529void\r
530irsnd_init (void)\r
531{\r
532#ifndef DEBUG\r
08f2dd9d 533# if defined(PIC_C18) // PIC C18\r
534 OpenTimer;\r
535 irsnd_set_freq (IRSND_FREQ_36_KHZ); //default frequency\r
536 IRSND_PIN = 1; //default PWM output pin off (0=PWM on, 1=PWM off)\r
537# elif defined (ARM_STM32) // STM32\r
37b29f94 538 GPIO_InitTypeDef GPIO_InitStructure;\r
539 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
540 TIM_OCInitTypeDef TIM_OCInitStructure;\r
08f2dd9d 541\r
542 /* GPIOx clock enable */\r
543# if defined (ARM_STM32L1XX)\r
544 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
545# elif defined (ARM_STM32F10X)\r
546 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
547# elif defined (ARM_STM32F4XX)\r
548 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
549# endif\r
550\r
551 /* GPIO Configuration */\r
552 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;\r
553# if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)\r
554 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
555 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
556 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
557 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
558 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
559 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);\r
560# elif defined (ARM_STM32F10X)\r
561 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
562 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
563 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
564 GPIO_PinRemapConfig(, ENABLE); // TODO: remapping required\r
565# endif\r
566\r
567 /* TIMx clock enable */\r
568# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
569 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
570# else\r
571 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
572# endif\r
08f2dd9d 573\r
37b29f94 574 /* Time base configuration */\r
acd29fb9 575 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r
37b29f94 576 TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
577 TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
578 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
579 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r
580\r
581 /* PWM1 Mode configuration */\r
582 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
583 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
acd29fb9 584 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
37b29f94 585 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
586 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
587\r
588 /* Preload configuration */\r
08f2dd9d 589 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
acd29fb9 590 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
37b29f94 591\r
acd29fb9 592 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r
08f2dd9d 593# else // AVR\r
594 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
595 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
596\r
597# if IRSND_OCx == IRSND_OC2 // use OC2\r
598 TCCR2 = (1<<WGM21); // CTC mode\r
599 TCCR2 |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
600# elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B\r
601 TCCR2A = (1<<WGM21); // CTC mode\r
602 TCCR2B |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
603# elif IRSND_OCx == IRSND_OC0 // use OC0\r
604 TCCR0 = (1<<WGM01); // CTC mode\r
605 TCCR0 |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r
606# elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B\r
607 TCCR0A = (1<<WGM01); // CTC mode\r
608 TCCR0B |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r
609# else\r
610# error wrong value of IRSND_OCx\r
611# endif\r
612 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
613# endif //PIC_C18\r
4225a882 614#endif // DEBUG\r
615}\r
616\r
f50e01e7 617#if IRSND_USE_CALLBACK == 1\r
618void\r
619irsnd_set_callback_ptr (void (*cb)(uint8_t))\r
620{\r
621 irsnd_callback_ptr = cb;\r
622}\r
623#endif // IRSND_USE_CALLBACK == 1\r
624\r
4225a882 625uint8_t\r
626irsnd_is_busy (void)\r
627{\r
628 return irsnd_busy;\r
629}\r
630\r
631static uint16_t\r
632bitsrevervse (uint16_t x, uint8_t len)\r
633{\r
634 uint16_t xx = 0;\r
635\r
636 while(len)\r
637 {\r
638 xx <<= 1;\r
639 if (x & 1)\r
640 {\r
641 xx |= 1;\r
642 }\r
643 x >>= 1;\r
644 len--;\r
645 }\r
646 return xx;\r
647}\r
648\r
649\r
9547ee89 650#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
651static uint8_t sircs_additional_bitlen;\r
652#endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
653\r
4225a882 654uint8_t\r
879b06c2 655irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)\r
4225a882 656{\r
657#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
658 static uint8_t toggle_bit_recs80;\r
659#endif\r
660#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
661 static uint8_t toggle_bit_recs80ext;\r
662#endif\r
663#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
664 static uint8_t toggle_bit_rc5;\r
9547ee89 665#endif\r
779fbc81 666#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
9547ee89 667 static uint8_t toggle_bit_rc6;\r
beda975f 668#endif\r
669#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
670 static uint8_t toggle_bit_thomson;\r
4225a882 671#endif\r
672 uint16_t address;\r
673 uint16_t command;\r
674\r
879b06c2 675 if (do_wait)\r
4225a882 676 {\r
879b06c2 677 while (irsnd_busy)\r
678 {\r
679 // do nothing;\r
680 }\r
681 }\r
682 else if (irsnd_busy)\r
683 {\r
684 return (FALSE);\r
4225a882 685 }\r
686\r
687 irsnd_protocol = irmp_data_p->protocol;\r
beda975f 688 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;\r
4225a882 689\r
690 switch (irsnd_protocol)\r
691 {\r
692#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
693 case IRMP_SIRCS_PROTOCOL:\r
694 {\r
08f2dd9d 695 // uint8_t sircs_additional_command_len;\r
9547ee89 696 uint8_t sircs_additional_address_len;\r
697\r
698 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen\r
699\r
700 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)\r
701 {\r
08f2dd9d 702 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;\r
9547ee89 703 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);\r
704 }\r
705 else\r
706 {\r
08f2dd9d 707 // sircs_additional_command_len = sircs_additional_bitlen;\r
9547ee89 708 sircs_additional_address_len = 0;\r
709 }\r
4225a882 710\r
9547ee89 711 command = bitsrevervse (irmp_data_p->command, 15);\r
712\r
713 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC\r
714 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****\r
715\r
716 if (sircs_additional_address_len > 0)\r
717 {\r
718 address = bitsrevervse (irmp_data_p->address, 5);\r
719 irsnd_buffer[1] |= (address & 0x0010) >> 4;\r
720 irsnd_buffer[2] = (address & 0x000F) << 4;\r
721 }\r
4225a882 722 irsnd_busy = TRUE;\r
723 break;\r
724 }\r
725#endif\r
726#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
46dd89b7 727 case IRMP_APPLE_PROTOCOL:\r
c7a47e89 728 {\r
729 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command\r
730 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)\r
731\r
732 address = bitsrevervse (address, NEC_ADDRESS_LEN);\r
733 command = bitsrevervse (command, NEC_COMMAND_LEN);\r
734\r
735 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command\r
736\r
7644ac04 737 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
738 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
739 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
740 irsnd_buffer[3] = 0x8B; // 10001011 (id)\r
c7a47e89 741 irsnd_busy = TRUE;\r
742 break;\r
743 }\r
744 case IRMP_NEC_PROTOCOL:\r
4225a882 745 {\r
746 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);\r
747 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);\r
748\r
4225a882 749 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
750 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
751 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
7644ac04 752 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
753 irsnd_busy = TRUE;\r
754 break;\r
755 }\r
756#endif\r
757#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
758 case IRMP_NEC16_PROTOCOL:\r
759 {\r
760 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);\r
761 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);\r
46dd89b7 762\r
7644ac04 763 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA\r
764 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
765 irsnd_busy = TRUE;\r
766 break;\r
767 }\r
768#endif\r
769#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
770 case IRMP_NEC42_PROTOCOL:\r
771 {\r
772 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);\r
773 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);\r
774\r
775 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA\r
a48187fa 776 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa\r
7644ac04 777 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa\r
778 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC\r
779 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc\r
780 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc\r
4225a882 781 irsnd_busy = TRUE;\r
782 break;\r
783 }\r
784#endif\r
785#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
786 case IRMP_SAMSUNG_PROTOCOL:\r
787 {\r
788 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
789 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);\r
790\r
4225a882 791 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
792 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
793 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC\r
794 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc\r
795 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000\r
796 irsnd_busy = TRUE;\r
797 break;\r
798 }\r
799 case IRMP_SAMSUNG32_PROTOCOL:\r
800 {\r
801 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
802 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);\r
803\r
4225a882 804 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
805 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
806 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
807 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC\r
808 irsnd_busy = TRUE;\r
809 break;\r
810 }\r
811#endif\r
812#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
813 case IRMP_MATSUSHITA_PROTOCOL:\r
814 {\r
815 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);\r
816 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);\r
817\r
4225a882 818 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
819 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA\r
820 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA\r
821 irsnd_busy = TRUE;\r
822 break;\r
823 }\r
824#endif\r
770a1a9d 825#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
826 case IRMP_KASEIKYO_PROTOCOL:\r
827 {\r
828 uint8_t xor;\r
0f700c8e 829 uint16_t genre2;\r
770a1a9d 830\r
831 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);\r
832 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);\r
0f700c8e 833 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);\r
770a1a9d 834\r
835 xor = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r
836\r
837 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
838 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
839 irsnd_buffer[2] = xor << 4 | (command & 0x000F); // XXXXCCCC\r
0f700c8e 840 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC\r
770a1a9d 841 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
842\r
843 xor = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r
844\r
845 irsnd_buffer[5] = xor;\r
846 irsnd_busy = TRUE;\r
847 break;\r
848 }\r
849#endif\r
4225a882 850#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
851 case IRMP_RECS80_PROTOCOL:\r
852 {\r
853 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x40;\r
854\r
4225a882 855 irsnd_buffer[0] = 0x80 | toggle_bit_recs80 | ((irmp_data_p->address & 0x0007) << 3) |\r
856 ((irmp_data_p->command & 0x0038) >> 3); // STAAACCC\r
857 irsnd_buffer[1] = (irmp_data_p->command & 0x07) << 5; // CCC00000\r
858 irsnd_busy = TRUE;\r
859 break;\r
860 }\r
861#endif\r
862#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
863 case IRMP_RECS80EXT_PROTOCOL:\r
864 {\r
865 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;\r
866\r
4225a882 867 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |\r
868 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC\r
869 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000\r
870 irsnd_busy = TRUE;\r
871 break;\r
872 }\r
873#endif\r
874#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
875 case IRMP_RC5_PROTOCOL:\r
876 {\r
877 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;\r
878\r
4225a882 879 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |\r
880 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC\r
881 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000\r
882 irsnd_busy = TRUE;\r
883 break;\r
884 }\r
885#endif\r
9547ee89 886#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
887 case IRMP_RC6_PROTOCOL:\r
888 {\r
889 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
890\r
891 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000\r
892 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC\r
893 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC\r
894 irsnd_busy = TRUE;\r
895 break;\r
896 }\r
897#endif\r
898#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
899 case IRMP_RC6A_PROTOCOL:\r
900 {\r
901 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
902\r
903 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110\r
904 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA\r
905 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC\r
906 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
907 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC\r
908 irsnd_busy = TRUE;\r
909 break;\r
910 }\r
911#endif\r
4225a882 912#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
913 case IRMP_DENON_PROTOCOL:\r
914 {\r
d155e9ab 915 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)\r
916 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC\r
08f2dd9d 917 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)\r
918 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc\r
4225a882 919 irsnd_busy = TRUE;\r
920 break;\r
921 }\r
922#endif\r
beda975f 923#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
924 case IRMP_THOMSON_PROTOCOL:\r
925 {\r
926 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;\r
927\r
928 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)\r
929 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC\r
930 irsnd_busy = TRUE;\r
931 break;\r
932 }\r
933#endif\r
4225a882 934#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
935 case IRMP_NUBERT_PROTOCOL:\r
936 {\r
4225a882 937 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
938 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
939 irsnd_busy = TRUE;\r
940 break;\r
941 }\r
5481e9cd 942#endif\r
943#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
944 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
945 {\r
5481e9cd 946 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC\r
947 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC\r
948 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
949 irsnd_busy = TRUE;\r
950 break;\r
951 }\r
4225a882 952#endif\r
5b437ff6 953#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
954 case IRMP_GRUNDIG_PROTOCOL:\r
955 {\r
956 command = bitsrevervse (irmp_data_p->command, GRUNDIG_COMMAND_LEN);\r
957\r
d155e9ab 958 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)\r
959 irsnd_buffer[1] = 0xC0; // 11\r
960 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)\r
961 irsnd_buffer[3] = (command << 6) & 0xC0; // CC\r
962\r
963 irsnd_busy = TRUE;\r
964 break;\r
965 }\r
966#endif\r
a48187fa 967#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
968 case IRMP_IR60_PROTOCOL:\r
969 {\r
970 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);\r
08f2dd9d 971#if 0\r
a48187fa 972 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)\r
973 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)\r
08f2dd9d 974#else\r
975 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)\r
976 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)\r
977#endif\r
a48187fa 978\r
979 irsnd_busy = TRUE;\r
980 break;\r
981 }\r
982#endif\r
d155e9ab 983#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
984 case IRMP_NOKIA_PROTOCOL:\r
985 {\r
986 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);\r
987 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);\r
988\r
989 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)\r
990 irsnd_buffer[1] = 0xFF; // 11111111\r
991 irsnd_buffer[2] = 0x80; // 1\r
992 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)\r
993 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA\r
994 irsnd_buffer[5] = (address << 7); // A\r
5b437ff6 995\r
996 irsnd_busy = TRUE;\r
997 break;\r
998 }\r
999#endif\r
a7054daf 1000#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
1001 case IRMP_SIEMENS_PROTOCOL:\r
1002 {\r
1003 irsnd_buffer[0] = ((irmp_data_p->address & 0x0FFF) >> 5); // SAAAAAAA\r
1004 irsnd_buffer[1] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x7F) >> 5); // AAAAA0CC\r
9405f84a 1005 irsnd_buffer[2] = (irmp_data_p->command << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r
1006\r
a7054daf 1007 irsnd_busy = TRUE;\r
1008 break;\r
1009 }\r
b5ea7869 1010#endif\r
48664931 1011#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
1012 case IRMP_FDC_PROTOCOL:\r
b5ea7869 1013 {\r
48664931 1014 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);\r
1015 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);\r
b5ea7869 1016\r
c7c9a4a1 1017 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA\r
1018 irsnd_buffer[1] = 0; // 00000000\r
1019 irsnd_buffer[2] = 0; // 0000RRRR\r
1020 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC\r
1021 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc\r
1022 irsnd_busy = TRUE;\r
1023 break;\r
1024 }\r
1025#endif\r
1026#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
1027 case IRMP_RCCAR_PROTOCOL:\r
1028 {\r
1029 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1\r
1030 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V\r
1031\r
1032 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3\r
1033 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0\r
1034 \r
b5ea7869 1035 irsnd_busy = TRUE;\r
1036 break;\r
1037 }\r
a7054daf 1038#endif\r
c7a47e89 1039#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
1040 case IRMP_JVC_PROTOCOL:\r
1041 {\r
1042 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);\r
1043 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);\r
1044\r
1045 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC\r
1046 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
1047\r
1048 irsnd_busy = TRUE;\r
1049 break;\r
1050 }\r
1051#endif\r
9405f84a 1052#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
1053 case IRMP_NIKON_PROTOCOL:\r
1054 {\r
1055 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC\r
1056 irsnd_busy = TRUE;\r
1057 break;\r
1058 }\r
f50e01e7 1059#endif\r
1060#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
1061 case IRMP_LEGO_PROTOCOL:\r
1062 {\r
1063 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);\r
1064\r
1065 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
1066 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc\r
1067\r
1068 irsnd_protocol = IRMP_LEGO_PROTOCOL;\r
1069 irsnd_busy = TRUE;\r
1070 break;\r
1071 }\r
9405f84a 1072#endif\r
4225a882 1073 default:\r
1074 {\r
1075 break;\r
1076 }\r
1077 }\r
1078\r
1079 return irsnd_busy;\r
1080}\r
1081\r
beda975f 1082void\r
1083irsnd_stop (void)\r
1084{\r
acf7fb44 1085 irsnd_repeat = 0;\r
beda975f 1086}\r
1087\r
4225a882 1088/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
1089 * ISR routine\r
1090 * @details ISR routine, called 10000 times per second\r
1091 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
1092 */\r
1093uint8_t\r
1094irsnd_ISR (void)\r
1095{\r
a48187fa 1096 static uint8_t send_trailer = FALSE;\r
1097 static uint8_t current_bit = 0xFF;\r
1098 static uint8_t pulse_counter = 0;\r
1099 static IRSND_PAUSE_LEN pause_counter = 0;\r
1100 static uint8_t startbit_pulse_len = 0;\r
1101 static IRSND_PAUSE_LEN startbit_pause_len = 0;\r
1102 static uint8_t pulse_1_len = 0;\r
1103 static uint8_t pause_1_len = 0;\r
1104 static uint8_t pulse_0_len = 0;\r
1105 static uint8_t pause_0_len = 0;\r
1106 static uint8_t has_stop_bit = 0;\r
1107 static uint8_t new_frame = TRUE;\r
1108 static uint8_t complete_data_len = 0;\r
1109 static uint8_t n_repeat_frames = 0; // number of repetition frames\r
1110 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions\r
1111 static uint8_t auto_repetition_counter = 0; // auto_repetition counter\r
1112 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!\r
1113 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!\r
1114 static uint8_t repeat_counter = 0; // repeat counter\r
1115 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!\r
1116 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!\r
5481e9cd 1117#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
a48187fa 1118 static uint8_t last_bit_value;\r
5481e9cd 1119#endif\r
a48187fa 1120 static uint8_t pulse_len = 0xFF;\r
08f2dd9d 1121 static IRSND_PAUSE_LEN pause_len = 0xFF;\r
4225a882 1122\r
1123 if (irsnd_busy)\r
1124 {\r
1125 if (current_bit == 0xFF && new_frame) // start of transmission...\r
1126 {\r
a7054daf 1127 if (auto_repetition_counter > 0)\r
4225a882 1128 {\r
a7054daf 1129 auto_repetition_pause_counter++;\r
4225a882 1130\r
08f2dd9d 1131#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
1132 if (repeat_frame_pause_len > 0) // frame repeat distance counts from beginning of 1st frame!\r
1133 {\r
1134 repeat_frame_pause_len--;\r
1135 }\r
1136#endif\r
1137\r
a7054daf 1138 if (auto_repetition_pause_counter >= auto_repetition_pause_len)\r
4225a882 1139 {\r
a7054daf 1140 auto_repetition_pause_counter = 0;\r
4225a882 1141\r
08f2dd9d 1142#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
a48187fa 1143 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame\r
4225a882 1144 {\r
1145 current_bit = 16;\r
1146 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;\r
1147 }\r
08f2dd9d 1148 else\r
1149#endif\r
1150#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
1151 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame\r
5b437ff6 1152 {\r
1153 current_bit = 15;\r
1154 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;\r
1155 }\r
08f2dd9d 1156 else\r
1157#endif\r
1158#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
1159 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame\r
a48187fa 1160 {\r
1161 current_bit = 7;\r
1162 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;\r
1163 }\r
08f2dd9d 1164 else\r
1165#endif\r
1166#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
1167 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame\r
d155e9ab 1168 {\r
a7054daf 1169 if (auto_repetition_counter + 1 < n_auto_repetitions)\r
d155e9ab 1170 {\r
1171 current_bit = 23;\r
1172 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;\r
1173 }\r
a7054daf 1174 else // nokia stop frame\r
d155e9ab 1175 {\r
1176 current_bit = 0xFF;\r
1177 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
1178 }\r
1179 }\r
08f2dd9d 1180 else\r
1181#endif\r
1182 {\r
1183 ;\r
1184 }\r
4225a882 1185 }\r
1186 else\r
1187 {\r
1188#ifdef DEBUG\r
1189 if (irsnd_is_on)\r
1190 {\r
1191 putchar ('0');\r
1192 }\r
1193 else\r
1194 {\r
1195 putchar ('1');\r
1196 }\r
1197#endif\r
1198 return irsnd_busy;\r
1199 }\r
1200 }\r
beda975f 1201#if 0\r
a7054daf 1202 else if (repeat_counter > 0 && packet_repeat_pause_counter < repeat_frame_pause_len)\r
beda975f 1203#else\r
1204 else if (packet_repeat_pause_counter < repeat_frame_pause_len)\r
1205#endif\r
a7054daf 1206 {\r
1207 packet_repeat_pause_counter++;\r
1208\r
1209#ifdef DEBUG\r
1210 if (irsnd_is_on)\r
1211 {\r
1212 putchar ('0');\r
1213 }\r
1214 else\r
1215 {\r
1216 putchar ('1');\r
1217 }\r
1218#endif\r
1219 return irsnd_busy;\r
1220 }\r
4225a882 1221 else\r
1222 {\r
0f700c8e 1223 if (send_trailer)\r
1224 {\r
1225 irsnd_busy = FALSE;\r
6ab7d63c 1226 send_trailer = FALSE;\r
0f700c8e 1227 return irsnd_busy;\r
1228 }\r
9c86ff1a 1229 \r
a7054daf 1230 n_repeat_frames = irsnd_repeat;\r
beda975f 1231\r
1232 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)\r
1233 {\r
1234 n_repeat_frames = 255;\r
1235 }\r
1236\r
a7054daf 1237 packet_repeat_pause_counter = 0;\r
1238 pulse_counter = 0;\r
1239 pause_counter = 0;\r
5481e9cd 1240\r
4225a882 1241 switch (irsnd_protocol)\r
1242 {\r
1243#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
1244 case IRMP_SIRCS_PROTOCOL:\r
1245 {\r
a7054daf 1246 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;\r
53c11f07 1247 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1248 pulse_1_len = SIRCS_1_PULSE_LEN;\r
53c11f07 1249 pause_1_len = SIRCS_PAUSE_LEN - 1;\r
a7054daf 1250 pulse_0_len = SIRCS_0_PULSE_LEN;\r
53c11f07 1251 pause_0_len = SIRCS_PAUSE_LEN - 1;\r
a7054daf 1252 has_stop_bit = SIRCS_STOP_BIT;\r
9547ee89 1253 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;\r
a7054daf 1254 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame\r
1255 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause\r
1256 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1257 irsnd_set_freq (IRSND_FREQ_40_KHZ);\r
1258 break;\r
1259 }\r
1260#endif\r
1261#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
1262 case IRMP_NEC_PROTOCOL:\r
1263 {\r
a7054daf 1264 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1265\r
1266 if (repeat_counter > 0)\r
1267 {\r
53c11f07 1268 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1269 complete_data_len = 0;\r
1270 }\r
1271 else\r
1272 {\r
53c11f07 1273 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1274 complete_data_len = NEC_COMPLETE_DATA_LEN;\r
1275 }\r
1276\r
1277 pulse_1_len = NEC_PULSE_LEN;\r
53c11f07 1278 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
a7054daf 1279 pulse_0_len = NEC_PULSE_LEN;\r
53c11f07 1280 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
a7054daf 1281 has_stop_bit = NEC_STOP_BIT;\r
1282 n_auto_repetitions = 1; // 1 frame\r
1283 auto_repetition_pause_len = 0;\r
1284 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1285 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1286 break;\r
1287 }\r
1288#endif\r
7644ac04 1289#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
1290 case IRMP_NEC16_PROTOCOL:\r
1291 {\r
1292 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1293 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1294 pulse_1_len = NEC_PULSE_LEN;\r
1295 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1296 pulse_0_len = NEC_PULSE_LEN;\r
1297 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1298 has_stop_bit = NEC_STOP_BIT;\r
1299 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit\r
1300 n_auto_repetitions = 1; // 1 frame\r
1301 auto_repetition_pause_len = 0;\r
1302 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1303 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1304 break;\r
1305 }\r
1306#endif\r
1307#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
1308 case IRMP_NEC42_PROTOCOL:\r
1309 {\r
1310 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1311 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1312 pulse_1_len = NEC_PULSE_LEN;\r
1313 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1314 pulse_0_len = NEC_PULSE_LEN;\r
1315 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1316 has_stop_bit = NEC_STOP_BIT;\r
1317 complete_data_len = NEC42_COMPLETE_DATA_LEN;\r
1318 n_auto_repetitions = 1; // 1 frame\r
1319 auto_repetition_pause_len = 0;\r
1320 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1321 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1322 break;\r
1323 }\r
1324#endif\r
4225a882 1325#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
1326 case IRMP_SAMSUNG_PROTOCOL:\r
1327 {\r
a7054daf 1328 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
53c11f07 1329 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1330 pulse_1_len = SAMSUNG_PULSE_LEN;\r
53c11f07 1331 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
a7054daf 1332 pulse_0_len = SAMSUNG_PULSE_LEN;\r
53c11f07 1333 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
a7054daf 1334 has_stop_bit = SAMSUNG_STOP_BIT;\r
1335 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;\r
1336 n_auto_repetitions = 1; // 1 frame\r
1337 auto_repetition_pause_len = 0;\r
1338 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1339 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1340 break;\r
1341 }\r
1342\r
1343 case IRMP_SAMSUNG32_PROTOCOL:\r
1344 {\r
a7054daf 1345 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
53c11f07 1346 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1347 pulse_1_len = SAMSUNG_PULSE_LEN;\r
53c11f07 1348 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
a7054daf 1349 pulse_0_len = SAMSUNG_PULSE_LEN;\r
53c11f07 1350 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
a7054daf 1351 has_stop_bit = SAMSUNG_STOP_BIT;\r
1352 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;\r
1353 n_auto_repetitions = SAMSUNG32_FRAMES; // 2 frames\r
1354 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r
1355 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1356 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1357 break;\r
1358 }\r
1359#endif\r
1360#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
1361 case IRMP_MATSUSHITA_PROTOCOL:\r
1362 {\r
a7054daf 1363 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
53c11f07 1364 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1365 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
53c11f07 1366 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r
a7054daf 1367 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
53c11f07 1368 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r
a7054daf 1369 has_stop_bit = MATSUSHITA_STOP_BIT;\r
1370 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;\r
1371 n_auto_repetitions = 1; // 1 frame\r
1372 auto_repetition_pause_len = 0;\r
1373 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1374 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1375 break;\r
1376 }\r
1377#endif\r
770a1a9d 1378#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
1379 case IRMP_KASEIKYO_PROTOCOL:\r
1380 {\r
1381 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;\r
53c11f07 1382 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;\r
770a1a9d 1383 pulse_1_len = KASEIKYO_PULSE_LEN;\r
53c11f07 1384 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;\r
770a1a9d 1385 pulse_0_len = KASEIKYO_PULSE_LEN;\r
53c11f07 1386 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;\r
770a1a9d 1387 has_stop_bit = KASEIKYO_STOP_BIT;\r
1388 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;\r
1389 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame\r
1390 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause\r
1391 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;\r
1392 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1393 break;\r
1394 }\r
1395#endif\r
4225a882 1396#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
1397 case IRMP_RECS80_PROTOCOL:\r
1398 {\r
a7054daf 1399 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;\r
53c11f07 1400 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1401 pulse_1_len = RECS80_PULSE_LEN;\r
53c11f07 1402 pause_1_len = RECS80_1_PAUSE_LEN - 1;\r
a7054daf 1403 pulse_0_len = RECS80_PULSE_LEN;\r
53c11f07 1404 pause_0_len = RECS80_0_PAUSE_LEN - 1;\r
a7054daf 1405 has_stop_bit = RECS80_STOP_BIT;\r
1406 complete_data_len = RECS80_COMPLETE_DATA_LEN;\r
1407 n_auto_repetitions = 1; // 1 frame\r
1408 auto_repetition_pause_len = 0;\r
1409 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1410 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1411 break;\r
1412 }\r
1413#endif\r
1414#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
1415 case IRMP_RECS80EXT_PROTOCOL:\r
1416 {\r
a7054daf 1417 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;\r
53c11f07 1418 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1419 pulse_1_len = RECS80EXT_PULSE_LEN;\r
53c11f07 1420 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;\r
a7054daf 1421 pulse_0_len = RECS80EXT_PULSE_LEN;\r
53c11f07 1422 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;\r
a7054daf 1423 has_stop_bit = RECS80EXT_STOP_BIT;\r
1424 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;\r
1425 n_auto_repetitions = 1; // 1 frame\r
1426 auto_repetition_pause_len = 0;\r
1427 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1428 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1429 break;\r
1430 }\r
1431#endif\r
1432#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
1433 case IRMP_RC5_PROTOCOL:\r
1434 {\r
a7054daf 1435 startbit_pulse_len = RC5_BIT_LEN;\r
1436 startbit_pause_len = RC5_BIT_LEN;\r
1437 pulse_len = RC5_BIT_LEN;\r
1438 pause_len = RC5_BIT_LEN;\r
1439 has_stop_bit = RC5_STOP_BIT;\r
1440 complete_data_len = RC5_COMPLETE_DATA_LEN;\r
1441 n_auto_repetitions = 1; // 1 frame\r
1442 auto_repetition_pause_len = 0;\r
1443 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1444 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1445 break;\r
1446 }\r
1447#endif\r
9547ee89 1448#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
1449 case IRMP_RC6_PROTOCOL:\r
1450 {\r
1451 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
53c11f07 1452 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
9547ee89 1453 pulse_len = RC6_BIT_LEN;\r
1454 pause_len = RC6_BIT_LEN;\r
1455 has_stop_bit = RC6_STOP_BIT;\r
1456 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;\r
1457 n_auto_repetitions = 1; // 1 frame\r
1458 auto_repetition_pause_len = 0;\r
1459 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
1460 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1461 break;\r
1462 }\r
1463#endif\r
1464#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
1465 case IRMP_RC6A_PROTOCOL:\r
1466 {\r
1467 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
53c11f07 1468 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
9547ee89 1469 pulse_len = RC6_BIT_LEN;\r
1470 pause_len = RC6_BIT_LEN;\r
1471 has_stop_bit = RC6_STOP_BIT;\r
1472 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;\r
1473 n_auto_repetitions = 1; // 1 frame\r
1474 auto_repetition_pause_len = 0;\r
1475 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
1476 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1477 break;\r
1478 }\r
1479#endif\r
4225a882 1480#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
1481 case IRMP_DENON_PROTOCOL:\r
1482 {\r
a7054daf 1483 startbit_pulse_len = 0x00;\r
1484 startbit_pause_len = 0x00;\r
1485 pulse_1_len = DENON_PULSE_LEN;\r
53c11f07 1486 pause_1_len = DENON_1_PAUSE_LEN - 1;\r
a7054daf 1487 pulse_0_len = DENON_PULSE_LEN;\r
53c11f07 1488 pause_0_len = DENON_0_PAUSE_LEN - 1;\r
a7054daf 1489 has_stop_bit = DENON_STOP_BIT;\r
1490 complete_data_len = DENON_COMPLETE_DATA_LEN;\r
1491 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command\r
1492 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame\r
1493 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r
779fbc81 1494 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better\r
4225a882 1495 break;\r
1496 }\r
1497#endif\r
beda975f 1498#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
1499 case IRMP_THOMSON_PROTOCOL:\r
1500 {\r
1501 startbit_pulse_len = 0x00;\r
1502 startbit_pause_len = 0x00;\r
1503 pulse_1_len = THOMSON_PULSE_LEN;\r
1504 pause_1_len = THOMSON_1_PAUSE_LEN - 1;\r
1505 pulse_0_len = THOMSON_PULSE_LEN;\r
1506 pause_0_len = THOMSON_0_PAUSE_LEN - 1;\r
1507 has_stop_bit = THOMSON_STOP_BIT;\r
1508 complete_data_len = THOMSON_COMPLETE_DATA_LEN;\r
1509 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame\r
1510 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;\r
1511 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r
1512 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1513 break;\r
1514 }\r
1515#endif\r
4225a882 1516#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
1517 case IRMP_NUBERT_PROTOCOL:\r
1518 {\r
a7054daf 1519 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;\r
53c11f07 1520 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;\r
a7054daf 1521 pulse_1_len = NUBERT_1_PULSE_LEN;\r
53c11f07 1522 pause_1_len = NUBERT_1_PAUSE_LEN - 1;\r
a7054daf 1523 pulse_0_len = NUBERT_0_PULSE_LEN;\r
53c11f07 1524 pause_0_len = NUBERT_0_PAUSE_LEN - 1;\r
a7054daf 1525 has_stop_bit = NUBERT_STOP_BIT;\r
1526 complete_data_len = NUBERT_COMPLETE_DATA_LEN;\r
1527 n_auto_repetitions = NUBERT_FRAMES; // 2 frames\r
1528 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
1529 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;\r
4225a882 1530 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1531 break;\r
1532 }\r
5481e9cd 1533#endif\r
1534#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
1535 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
1536 {\r
a7054daf 1537 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;\r
53c11f07 1538 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;\r
a7054daf 1539 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;\r
53c11f07 1540 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;\r
a7054daf 1541 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;\r
53c11f07 1542 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;\r
a7054daf 1543 has_stop_bit = BANG_OLUFSEN_STOP_BIT;\r
1544 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;\r
1545 n_auto_repetitions = 1; // 1 frame\r
1546 auto_repetition_pause_len = 0;\r
1547 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;\r
1548 last_bit_value = 0;\r
5481e9cd 1549 irsnd_set_freq (IRSND_FREQ_455_KHZ);\r
1550 break;\r
1551 }\r
5b437ff6 1552#endif\r
1553#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
1554 case IRMP_GRUNDIG_PROTOCOL:\r
1555 {\r
89e8cafb 1556 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1557 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
1558 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1559 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1560 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
a7054daf 1561 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;\r
1562 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames\r
1563 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
a48187fa 1564 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
d155e9ab 1565 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
a48187fa 1566 break;\r
1567 }\r
1568#endif\r
1569#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
1570 case IRMP_IR60_PROTOCOL:\r
1571 {\r
1572 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1573 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
1574 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1575 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1576 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
1577 complete_data_len = IR60_COMPLETE_DATA_LEN;\r
1578 n_auto_repetitions = IR60_FRAMES; // 2 frames\r
1579 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
1580 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
1581 irsnd_set_freq (IRSND_FREQ_30_KHZ);\r
d155e9ab 1582 break;\r
1583 }\r
1584#endif\r
1585#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
1586 case IRMP_NOKIA_PROTOCOL:\r
1587 {\r
89e8cafb 1588 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1589 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
1590 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1591 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
1592 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
a7054daf 1593 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
08f2dd9d 1594 n_auto_repetitions = NOKIA_FRAMES; // 2 frames\r
1595 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause\r
1596 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
d155e9ab 1597 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
5b437ff6 1598 break;\r
1599 }\r
a7054daf 1600#endif\r
1601#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
1602 case IRMP_SIEMENS_PROTOCOL:\r
1603 {\r
1604 startbit_pulse_len = SIEMENS_BIT_LEN;\r
1605 startbit_pause_len = SIEMENS_BIT_LEN;\r
1606 pulse_len = SIEMENS_BIT_LEN;\r
1607 pause_len = SIEMENS_BIT_LEN;\r
02ccdb69 1608 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
a7054daf 1609 complete_data_len = SIEMENS_COMPLETE_DATA_LEN - 1;\r
1610 n_auto_repetitions = 1; // 1 frame\r
1611 auto_repetition_pause_len = 0;\r
1612 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;\r
1613 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1614 break;\r
1615 }\r
b5ea7869 1616#endif\r
48664931 1617#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
1618 case IRMP_FDC_PROTOCOL:\r
b5ea7869 1619 {\r
48664931 1620 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;\r
53c11f07 1621 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;\r
48664931 1622 complete_data_len = FDC_COMPLETE_DATA_LEN;\r
1623 pulse_1_len = FDC_PULSE_LEN;\r
53c11f07 1624 pause_1_len = FDC_1_PAUSE_LEN - 1;\r
48664931 1625 pulse_0_len = FDC_PULSE_LEN;\r
53c11f07 1626 pause_0_len = FDC_0_PAUSE_LEN - 1;\r
48664931 1627 has_stop_bit = FDC_STOP_BIT;\r
b5ea7869 1628 n_auto_repetitions = 1; // 1 frame\r
1629 auto_repetition_pause_len = 0;\r
48664931 1630 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;\r
b5ea7869 1631 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1632 break;\r
1633 }\r
c7c9a4a1 1634#endif\r
1635#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
1636 case IRMP_RCCAR_PROTOCOL:\r
1637 {\r
1638 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;\r
53c11f07 1639 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;\r
c7c9a4a1 1640 complete_data_len = RCCAR_COMPLETE_DATA_LEN;\r
1641 pulse_1_len = RCCAR_PULSE_LEN;\r
53c11f07 1642 pause_1_len = RCCAR_1_PAUSE_LEN - 1;\r
c7c9a4a1 1643 pulse_0_len = RCCAR_PULSE_LEN;\r
53c11f07 1644 pause_0_len = RCCAR_0_PAUSE_LEN - 1;\r
c7c9a4a1 1645 has_stop_bit = RCCAR_STOP_BIT;\r
1646 n_auto_repetitions = 1; // 1 frame\r
1647 auto_repetition_pause_len = 0;\r
1648 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;\r
1649 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1650 break;\r
1651 }\r
4225a882 1652#endif\r
c7a47e89 1653#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
1654 case IRMP_JVC_PROTOCOL:\r
1655 {\r
1656 if (repeat_counter != 0) // skip start bit if repetition frame\r
1657 {\r
1658 current_bit = 0;\r
1659 }\r
1660\r
1661 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;\r
53c11f07 1662 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;\r
c7a47e89 1663 complete_data_len = JVC_COMPLETE_DATA_LEN;\r
1664 pulse_1_len = JVC_PULSE_LEN;\r
53c11f07 1665 pause_1_len = JVC_1_PAUSE_LEN - 1;\r
c7a47e89 1666 pulse_0_len = JVC_PULSE_LEN;\r
53c11f07 1667 pause_0_len = JVC_0_PAUSE_LEN - 1;\r
c7a47e89 1668 has_stop_bit = JVC_STOP_BIT;\r
1669 n_auto_repetitions = 1; // 1 frame\r
1670 auto_repetition_pause_len = 0;\r
1671 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;\r
1672 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
c7a47e89 1673 break;\r
1674 }\r
1675#endif\r
9405f84a 1676#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
1677 case IRMP_NIKON_PROTOCOL:\r
1678 {\r
1679 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;\r
53c11f07 1680 startbit_pause_len = 271 - 1; // NIKON_START_BIT_PAUSE_LEN;\r
9405f84a 1681 complete_data_len = NIKON_COMPLETE_DATA_LEN;\r
1682 pulse_1_len = NIKON_PULSE_LEN;\r
53c11f07 1683 pause_1_len = NIKON_1_PAUSE_LEN - 1;\r
9405f84a 1684 pulse_0_len = NIKON_PULSE_LEN;\r
53c11f07 1685 pause_0_len = NIKON_0_PAUSE_LEN - 1;\r
9405f84a 1686 has_stop_bit = NIKON_STOP_BIT;\r
1687 n_auto_repetitions = 1; // 1 frame\r
1688 auto_repetition_pause_len = 0;\r
1689 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;\r
1690 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
9405f84a 1691 break;\r
1692 }\r
1693#endif\r
f50e01e7 1694#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
1695 case IRMP_LEGO_PROTOCOL:\r
1696 {\r
1697 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;\r
1698 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;\r
1699 complete_data_len = LEGO_COMPLETE_DATA_LEN;\r
1700 pulse_1_len = LEGO_PULSE_LEN;\r
1701 pause_1_len = LEGO_1_PAUSE_LEN - 1;\r
1702 pulse_0_len = LEGO_PULSE_LEN;\r
1703 pause_0_len = LEGO_0_PAUSE_LEN - 1;\r
1704 has_stop_bit = LEGO_STOP_BIT;\r
1705 n_auto_repetitions = 1; // 1 frame\r
1706 auto_repetition_pause_len = 0;\r
1707 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;\r
1708 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1709 break;\r
1710 }\r
1711#endif\r
4225a882 1712 default:\r
1713 {\r
1714 irsnd_busy = FALSE;\r
1715 break;\r
1716 }\r
1717 }\r
1718 }\r
1719 }\r
1720\r
1721 if (irsnd_busy)\r
1722 {\r
1723 new_frame = FALSE;\r
a7054daf 1724\r
4225a882 1725 switch (irsnd_protocol)\r
1726 {\r
1727#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
1728 case IRMP_SIRCS_PROTOCOL:\r
1729#endif\r
1730#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
1731 case IRMP_NEC_PROTOCOL:\r
1732#endif\r
7644ac04 1733#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
1734 case IRMP_NEC16_PROTOCOL:\r
1735#endif\r
1736#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
1737 case IRMP_NEC42_PROTOCOL:\r
1738#endif\r
4225a882 1739#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
1740 case IRMP_SAMSUNG_PROTOCOL:\r
1741 case IRMP_SAMSUNG32_PROTOCOL:\r
1742#endif\r
1743#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
1744 case IRMP_MATSUSHITA_PROTOCOL:\r
1745#endif\r
770a1a9d 1746#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
1747 case IRMP_KASEIKYO_PROTOCOL:\r
1748#endif\r
4225a882 1749#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
1750 case IRMP_RECS80_PROTOCOL:\r
1751#endif\r
1752#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
1753 case IRMP_RECS80EXT_PROTOCOL:\r
1754#endif\r
1755#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
1756 case IRMP_DENON_PROTOCOL:\r
1757#endif\r
beda975f 1758#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
1759 case IRMP_THOMSON_PROTOCOL:\r
1760#endif\r
4225a882 1761#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
1762 case IRMP_NUBERT_PROTOCOL:\r
5481e9cd 1763#endif\r
1764#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
1765 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
4225a882 1766#endif\r
c7c9a4a1 1767#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
48664931 1768 case IRMP_FDC_PROTOCOL:\r
b5ea7869 1769#endif\r
c7c9a4a1 1770#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
1771 case IRMP_RCCAR_PROTOCOL:\r
1772#endif\r
c7a47e89 1773#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
1774 case IRMP_JVC_PROTOCOL:\r
1775#endif\r
9405f84a 1776#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
1777 case IRMP_NIKON_PROTOCOL:\r
1778#endif\r
f50e01e7 1779#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
1780 case IRMP_LEGO_PROTOCOL:\r
1781#endif\r
a7054daf 1782\r
1783\r
7644ac04 1784#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \\r
1785 IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || \\r
770a1a9d 1786 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \\r
c7a47e89 1787 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || \\r
beda975f 1788 IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 \r
4225a882 1789 {\r
08f2dd9d 1790#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
1791 if (irsnd_protocol == IRMP_DENON_PROTOCOL)\r
1792 {\r
1793 if (auto_repetition_pause_len > 0) // 2nd frame distance counts from beginning of 1st frame!\r
1794 {\r
1795 auto_repetition_pause_len--;\r
1796 }\r
1797\r
1798 if (repeat_frame_pause_len > 0) // frame repeat distance counts from beginning of 1st frame!\r
1799 {\r
1800 repeat_frame_pause_len--;\r
1801 }\r
1802 }\r
1803#endif\r
1804\r
5481e9cd 1805 if (pulse_counter == 0)\r
4225a882 1806 {\r
5481e9cd 1807 if (current_bit == 0xFF) // send start bit\r
1808 {\r
1809 pulse_len = startbit_pulse_len;\r
1810 pause_len = startbit_pause_len;\r
1811 }\r
1812 else if (current_bit < complete_data_len) // send n'th bit\r
4225a882 1813 {\r
5481e9cd 1814#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
1815 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)\r
4225a882 1816 {\r
5481e9cd 1817 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits\r
1818 {\r
1819 pulse_len = SAMSUNG_PULSE_LEN;\r
1820 pause_len = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ?\r
53c11f07 1821 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
5481e9cd 1822 }\r
1823 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)\r
1824 {\r
1825 pulse_len = SAMSUNG_PULSE_LEN;\r
53c11f07 1826 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
5481e9cd 1827 }\r
1828 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit\r
1829 {\r
1830 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
1831\r
1832 pulse_len = SAMSUNG_PULSE_LEN;\r
1833 pause_len = (irsnd_buffer[cur_bit / 8] & (1<<(7-(cur_bit % 8)))) ?\r
53c11f07 1834 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
5481e9cd 1835 }\r
4225a882 1836 }\r
5481e9cd 1837 else\r
1838#endif\r
1839\r
7644ac04 1840#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
1841 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)\r
1842 {\r
1843 if (current_bit < NEC16_ADDRESS_LEN) // send address bits\r
1844 {\r
1845 pulse_len = NEC_PULSE_LEN;\r
1846 pause_len = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ?\r
1847 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
1848 }\r
1849 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)\r
1850 {\r
1851 pulse_len = NEC_PULSE_LEN;\r
1852 pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1853 }\r
1854 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit\r
1855 {\r
1856 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
1857\r
1858 pulse_len = NEC_PULSE_LEN;\r
1859 pause_len = (irsnd_buffer[cur_bit / 8] & (1<<(7-(cur_bit % 8)))) ?\r
1860 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
1861 }\r
1862 }\r
1863 else\r
1864#endif\r
1865\r
5481e9cd 1866#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
1867 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)\r
4225a882 1868 {\r
5481e9cd 1869 if (current_bit == 0) // send 2nd start bit\r
1870 {\r
1871 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
53c11f07 1872 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
5481e9cd 1873 }\r
1874 else if (current_bit == 1) // send 3rd start bit\r
1875 {\r
1876 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;\r
53c11f07 1877 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;\r
5481e9cd 1878 }\r
1879 else if (current_bit == 2) // send 4th start bit\r
1880 {\r
1881 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
53c11f07 1882 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
5481e9cd 1883 }\r
1884 else if (current_bit == 19) // send trailer bit\r
1885 {\r
1886 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
53c11f07 1887 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;\r
5481e9cd 1888 }\r
1889 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit\r
1890 {\r
1891 uint8_t cur_bit_value = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? 1 : 0;\r
1892 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
1893\r
1894 if (cur_bit_value == last_bit_value)\r
1895 {\r
53c11f07 1896 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;\r
5481e9cd 1897 }\r
1898 else\r
1899 {\r
53c11f07 1900 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);\r
5481e9cd 1901 last_bit_value = cur_bit_value;\r
1902 }\r
1903 }\r
4225a882 1904 }\r
5481e9cd 1905 else\r
1906#endif\r
1907 if (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8))))\r
4225a882 1908 {\r
5481e9cd 1909 pulse_len = pulse_1_len;\r
1910 pause_len = pause_1_len;\r
1911 }\r
1912 else\r
1913 {\r
1914 pulse_len = pulse_0_len;\r
1915 pause_len = pause_0_len;\r
4225a882 1916 }\r
1917 }\r
5481e9cd 1918 else if (has_stop_bit) // send stop bit\r
4225a882 1919 {\r
1920 pulse_len = pulse_0_len;\r
4225a882 1921\r
a7054daf 1922 if (auto_repetition_counter < n_auto_repetitions)\r
5481e9cd 1923 {\r
1924 pause_len = pause_0_len;\r
1925 }\r
1926 else\r
1927 {\r
1928 pause_len = 255; // last frame: pause of 255\r
1929 }\r
4225a882 1930 }\r
1931 }\r
1932\r
1933 if (pulse_counter < pulse_len)\r
1934 {\r
1935 if (pulse_counter == 0)\r
1936 {\r
1937 irsnd_on ();\r
1938 }\r
1939 pulse_counter++;\r
1940 }\r
1941 else if (pause_counter < pause_len)\r
1942 {\r
1943 if (pause_counter == 0)\r
1944 {\r
1945 irsnd_off ();\r
1946 }\r
1947 pause_counter++;\r
1948 }\r
1949 else\r
1950 {\r
1951 current_bit++;\r
1952\r
1953 if (current_bit >= complete_data_len + has_stop_bit)\r
1954 {\r
1955 current_bit = 0xFF;\r
a7054daf 1956 auto_repetition_counter++;\r
4225a882 1957\r
a7054daf 1958 if (auto_repetition_counter == n_auto_repetitions)\r
4225a882 1959 {\r
1960 irsnd_busy = FALSE;\r
a7054daf 1961 auto_repetition_counter = 0;\r
4225a882 1962 }\r
1963 new_frame = TRUE;\r
1964 }\r
1965\r
1966 pulse_counter = 0;\r
1967 pause_counter = 0;\r
1968 }\r
1969 break;\r
1970 }\r
a7054daf 1971#endif\r
1972\r
4225a882 1973#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
1974 case IRMP_RC5_PROTOCOL:\r
a7054daf 1975#endif\r
9547ee89 1976#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
1977 case IRMP_RC6_PROTOCOL:\r
1978#endif\r
1979#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
1980 case IRMP_RC6A_PROTOCOL:\r
1981#endif\r
a7054daf 1982#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
1983 case IRMP_SIEMENS_PROTOCOL:\r
1984#endif\r
1985#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
1986 case IRMP_GRUNDIG_PROTOCOL:\r
1987#endif\r
a48187fa 1988#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
1989 case IRMP_IR60_PROTOCOL:\r
1990#endif\r
a7054daf 1991#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
1992 case IRMP_NOKIA_PROTOCOL:\r
1993#endif\r
4225a882 1994\r
9547ee89 1995#if IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r
a48187fa 1996 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
a7054daf 1997 {\r
1998 if (pulse_counter == pulse_len && pause_counter == pause_len)\r
4225a882 1999 {\r
a7054daf 2000 current_bit++;\r
4225a882 2001\r
a7054daf 2002 if (current_bit >= complete_data_len)\r
4225a882 2003 {\r
a7054daf 2004 current_bit = 0xFF;\r
2005\r
a48187fa 2006#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
2007 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
4225a882 2008 {\r
a7054daf 2009 auto_repetition_counter++;\r
2010\r
2011 if (repeat_counter > 0)\r
2012 { // set 117 msec pause time\r
89e8cafb 2013 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;\r
a7054daf 2014 }\r
2015\r
2016 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame\r
2017 {\r
2018 n_auto_repetitions++; // increment number of auto repetitions\r
2019 repeat_counter++;\r
2020 }\r
2021 else if (auto_repetition_counter == n_auto_repetitions)\r
2022 {\r
2023 irsnd_busy = FALSE;\r
2024 auto_repetition_counter = 0;\r
2025 }\r
4225a882 2026 }\r
a7054daf 2027 else\r
2028#endif\r
4225a882 2029 {\r
a7054daf 2030 irsnd_busy = FALSE;\r
4225a882 2031 }\r
4225a882 2032\r
4225a882 2033 new_frame = TRUE;\r
2034 irsnd_off ();\r
2035 }\r
2036\r
2037 pulse_counter = 0;\r
2038 pause_counter = 0;\r
2039 }\r
5b437ff6 2040\r
a7054daf 2041 if (! new_frame)\r
5b437ff6 2042 {\r
a7054daf 2043 uint8_t first_pulse;\r
5b437ff6 2044\r
a48187fa 2045#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
2046 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
5b437ff6 2047 {\r
a7054daf 2048 if (current_bit == 0xFF || // start bit of start-frame\r
2049 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)\r
a48187fa 2050 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)\r
a7054daf 2051 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)\r
5b437ff6 2052 {\r
a7054daf 2053 pulse_len = startbit_pulse_len;\r
2054 pause_len = startbit_pause_len;\r
2055 first_pulse = TRUE;\r
5b437ff6 2056 }\r
a7054daf 2057 else // send n'th bit\r
5b437ff6 2058 {\r
89e8cafb 2059 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2060 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
a7054daf 2061 first_pulse = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? TRUE : FALSE;\r
5b437ff6 2062 }\r
5b437ff6 2063 }\r
9547ee89 2064 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||\r
2065 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL)\r
a7054daf 2066#endif\r
5b437ff6 2067 {\r
a7054daf 2068 if (current_bit == 0xFF) // 1 start bit\r
2069 {\r
9547ee89 2070#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
2071 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2072 {\r
2073 pulse_len = startbit_pulse_len;\r
2074 pause_len = startbit_pause_len;\r
2075 }\r
2076#endif\r
a7054daf 2077 first_pulse = TRUE;\r
2078 }\r
2079 else // send n'th bit\r
2080 {\r
9547ee89 2081#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
2082 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2083 {\r
2084 pulse_len = RC6_BIT_LEN;\r
2085 pause_len = RC6_BIT_LEN;\r
2086\r
2087 if (irsnd_protocol == IRMP_RC6_PROTOCOL)\r
2088 {\r
2089 if (current_bit == 4) // toggle bit (double len)\r
2090 {\r
2091 pulse_len = 2 * RC6_BIT_LEN;\r
2092 pause_len = 2 * RC6_BIT_LEN;\r
2093 }\r
2094 }\r
2095 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2096 {\r
2097 if (current_bit == 4) // toggle bit (double len)\r
2098 {\r
2099 pulse_len = 2 * RC6_BIT_LEN + RC6_BIT_LEN; // hack!\r
2100 pause_len = 2 * RC6_BIT_LEN;\r
2101 }\r
2102 else if (current_bit == 5) // toggle bit (double len)\r
2103 {\r
2104 pause_len = 2 * RC6_BIT_LEN;\r
2105 }\r
2106 }\r
2107 }\r
2108#endif\r
a7054daf 2109 first_pulse = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? TRUE : FALSE;\r
2110 }\r
5b437ff6 2111\r
a7054daf 2112 if (irsnd_protocol == IRMP_RC5_PROTOCOL)\r
2113 {\r
2114 first_pulse = first_pulse ? FALSE : TRUE;\r
2115 }\r
2116 }\r
5b437ff6 2117\r
2118 if (first_pulse)\r
2119 {\r
a7054daf 2120 if (pulse_counter < pulse_len)\r
5b437ff6 2121 {\r
2122 if (pulse_counter == 0)\r
2123 {\r
2124 irsnd_on ();\r
2125 }\r
2126 pulse_counter++;\r
2127 }\r
a7054daf 2128 else // if (pause_counter < pause_len)\r
5b437ff6 2129 {\r
2130 if (pause_counter == 0)\r
2131 {\r
2132 irsnd_off ();\r
2133 }\r
2134 pause_counter++;\r
2135 }\r
5b437ff6 2136 }\r
2137 else\r
2138 {\r
a7054daf 2139 if (pause_counter < pause_len)\r
5b437ff6 2140 {\r
2141 if (pause_counter == 0)\r
2142 {\r
2143 irsnd_off ();\r
2144 }\r
2145 pause_counter++;\r
2146 }\r
a7054daf 2147 else // if (pulse_counter < pulse_len)\r
5b437ff6 2148 {\r
2149 if (pulse_counter == 0)\r
2150 {\r
2151 irsnd_on ();\r
2152 }\r
2153 pulse_counter++;\r
2154 }\r
5b437ff6 2155 }\r
2156 }\r
2157 break;\r
2158 }\r
9547ee89 2159#endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||\r
a48187fa 2160 // IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
5b437ff6 2161\r
4225a882 2162 default:\r
2163 {\r
2164 irsnd_busy = FALSE;\r
2165 break;\r
2166 }\r
2167 }\r
2168 }\r
a7054daf 2169\r
2170 if (! irsnd_busy)\r
2171 {\r
2172 if (repeat_counter < n_repeat_frames)\r
2173 {\r
c7c9a4a1 2174#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
2175 if (irsnd_protocol == IRMP_FDC_PROTOCOL)\r
2176 {\r
2177 irsnd_buffer[2] |= 0x0F;\r
2178 }\r
2179#endif\r
a7054daf 2180 repeat_counter++;\r
2181 irsnd_busy = TRUE;\r
2182 }\r
2183 else\r
2184 {\r
9c86ff1a 2185 irsnd_busy = TRUE; //Rainer\r
0f700c8e 2186 send_trailer = TRUE;\r
a7054daf 2187 n_repeat_frames = 0;\r
2188 repeat_counter = 0;\r
2189 }\r
2190 }\r
4225a882 2191 }\r
2192\r
2193#ifdef DEBUG\r
2194 if (irsnd_is_on)\r
2195 {\r
2196 putchar ('0');\r
2197 }\r
2198 else\r
2199 {\r
2200 putchar ('1');\r
2201 }\r
2202#endif\r
2203\r
2204 return irsnd_busy;\r
2205}\r
2206\r
2207#ifdef DEBUG\r
2208\r
2209// main function - for unix/linux + windows only!\r
2210// AVR: see main.c!\r
2211// Compile it under linux with:\r
2212// cc irsnd.c -o irsnd\r
2213//\r
2214// usage: ./irsnd protocol hex-address hex-command >filename\r
2215\r
2216int\r
2217main (int argc, char ** argv)\r
2218{\r
4225a882 2219 int protocol;\r
2220 int address;\r
2221 int command;\r
4225a882 2222 IRMP_DATA irmp_data;\r
2223\r
a7054daf 2224 if (argc != 4 && argc != 5)\r
4225a882 2225 {\r
a7054daf 2226 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);\r
4225a882 2227 return 1;\r
2228 }\r
2229\r
2230 if (sscanf (argv[1], "%d", &protocol) == 1 &&\r
2231 sscanf (argv[2], "%x", &address) == 1 &&\r
2232 sscanf (argv[3], "%x", &command) == 1)\r
2233 {\r
2234 irmp_data.protocol = protocol;\r
2235 irmp_data.address = address;\r
2236 irmp_data.command = command;\r
2237\r
a7054daf 2238 if (argc == 5)\r
2239 {\r
2240 irmp_data.flags = atoi (argv[4]);\r
2241 }\r
2242 else\r
2243 {\r
2244 irmp_data.flags = 0;\r
2245 }\r
2246\r
4225a882 2247 irsnd_init ();\r
2248\r
879b06c2 2249 (void) irsnd_send_data (&irmp_data, TRUE);\r
4225a882 2250\r
a7054daf 2251 while (irsnd_busy)\r
2252 {\r
2253 irsnd_ISR ();\r
2254 }\r
beda975f 2255\r
4225a882 2256 putchar ('\n');\r
2257 }\r
2258 else\r
2259 {\r
2260 fprintf (stderr, "%s: wrong arguments\n", argv[0]);\r
2261 return 1;\r
2262 }\r
2263 return 0;\r
2264}\r
2265\r
2266#endif // DEBUG\r
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)