Version 2.2.2: STM32 port of IRSND.

git-svn-id: svn://mikrocontroller.net/irmp@100 aeb2e35e-bfc4-4214-b83c-9e8de998ed28

diff --git a/README.txt b/README.txt
index 72bd165c55f5431608fb3243d56b81302bd43f95..91f1256a0caa76bed154c4aea870988e21119d06 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -2,7 +2,7 @@ IRMP - Infrared Multi Protocol Decoder
 --------------------------------------\r
 \r
 Version IRMP:  2.2.2 25.05.2012\r
-Version IRSND: 2.2.1 24.05.2012\r
+Version IRSND: 2.2.2 05.06.2012\r
 \r
 Dokumentation:\r
  \r

diff --git a/irmpextlog.c b/irmpextlog.c
index 482a18d3e1a0862d8601df10af83f5bf9baa83b7..7637351bbf44cbcaf1dcd0a7a369a4ee3270fc45 100644 (file)
--- a/irmpextlog.c
+++ b/irmpextlog.c
@@ -1,7 +1,7 @@
 /*---------------------------------------------------------------------------------------------------------------------------------------------------\r
  * irmpextlog.c - external logging\r
  *\r
- * $Id: irmpextlog.c,v 1.2 2012/02/27 09:04:21 fm Exp $\r
+ * $Id: irmpextlog.c,v 1.3 2012/06/05 12:00:46 fm Exp $\r
  *\r
  * If you cannot use the internal UART logging routine, adapt the\r
  * source below for your application. The following implementation\r
@@ -13,7 +13,7 @@
  * (at your option) any later version.\r
  *---------------------------------------------------------------------------------------------------------------------------------------------------\r
  */\r
-#include "irmpconfig.h"\r
+#include "irmp.h"\r
 \r
 #if IRMP_EXT_LOGGING == 1\r
 \r

diff --git a/irsnd.c b/irsnd.c
index 9fe95d71f89d0073e42ca5ee8a001dc9d62238c7..efdc93d56794d7e5becb6391f30fec8eb79e83fb 100644 (file)
--- a/irsnd.c
+++ b/irsnd.c
@@ -12,7 +12,7 @@
  * ATmega164, ATmega324, ATmega644,  ATmega644P, ATmega1284\r
  * ATmega88,  ATmega88P, ATmega168,  ATmega168P, ATmega328P\r
  *\r
- * $Id: irsnd.c,v 1.55 2012/05/24 06:55:11 fm Exp $\r
+ * $Id: irsnd.c,v 1.56 2012/06/05 12:00:46 fm Exp $\r
  *\r
  * This program is free software; you can redistribute it and/or modify\r
  * it under the terms of the GNU General Public License as published by\r
@@ -369,8 +369,9 @@ irsnd_on (void)
 #  if defined(PIC_C18)                                  // PIC C18\r
         IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
 #  elif defined (ARM_STM32)                             // STM32\r
-        IRSND_TIMER->CCER |= (uint16_t)TIM_CCER_CC1E;\r
-        TIM_Cmd(IRSND_TIMER, ENABLE);                   // TIMx enable counter\r
+        TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
+        TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable);      // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+        TIM_Cmd(IRSND_TIMER, ENABLE);                   // enable counter\r
 #  else                                                 // AVR\r
 #    if   IRSND_OCx == IRSND_OC2                        // use OC2\r
         TCCR2 |= (1<<COM20)|(1<<WGM21);                 // toggle OC2 on compare match,  clear Timer 2 at compare match OCR2\r
@@ -416,8 +417,10 @@ irsnd_off (void)
 #  if defined(PIC_C18)                                  // PIC C18\r
         IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
 #  elif defined (ARM_STM32)                             // STM32\r
-        IRSND_TIMER->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
-        TIM_Cmd(IRSND_TIMER, DISABLE);                  // TIMx enable counter\r
+        TIM_Cmd(IRSND_TIMER, DISABLE);                  // disable counter\r
+        TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive);   // force output inactive\r
+        TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable);      // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+        TIM_SetCounter(IRSND_TIMER, 0);                 // reset counter value\r
 #  else //AVR\r
 \r
 #    if   IRSND_OCx == IRSND_OC2                        // use OC2\r
@@ -494,7 +497,7 @@ irsnd_set_freq (IRSND_FREQ_TYPE freq)
          freq = TimeBaseFreq/freq;\r
 \r
          /* Set frequency */\r
-         TIM_SetAutoreload(IRSND_TIMER, freq);\r
+         TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
          /* Set duty cycle */\r
          TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
 #  else                                                                                     // AVR\r
@@ -569,7 +572,7 @@ irsnd_init (void)
 #    endif\r
 \r
         /* Time base configuration */\r
-        TIM_TimeBaseStructure.TIM_Period = 0;   // will be initialized later\r
+        TIM_TimeBaseStructure.TIM_Period = -1;     // set dummy value (don't set to 0), will be initialized later\r
         TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
         TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
         TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
@@ -578,15 +581,15 @@ irsnd_init (void)
         /* PWM1 Mode configuration */\r
         TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
         TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
-        TIM_OCInitStructure.TIM_Pulse = 0;      // will be initialized later\r
+        TIM_OCInitStructure.TIM_Pulse = 0;         // will be initialized later\r
         TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
         TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
 \r
         /* Preload configuration */\r
-        TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
         TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
+        TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
 \r
-        irsnd_set_freq (IRSND_FREQ_36_KHZ);                                         // default frequency\r
+        irsnd_set_freq (IRSND_FREQ_36_KHZ);                                         // set default frequency\r
 #  else                                                                             // AVR\r
         IRSND_PORT &= ~(1<<IRSND_BIT);                                              // set IRSND_BIT to low\r
         IRSND_DDR |= (1<<IRSND_BIT);                                                // set IRSND_BIT to output\r

diff --git a/irsnd.h b/irsnd.h
index 88f6d314c165a87ef21e2a84b6b00f63d27e69b1..46ecdde4604b4a663e9f55f1b7ee4af4de326105 100644 (file)
--- a/irsnd.h
+++ b/irsnd.h
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2010-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irsnd.h,v 1.12 2012/05/23 12:26:26 fm Exp $\r
+ * $Id: irsnd.h,v 1.13 2012/06/05 12:00:46 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -37,6 +37,7 @@
 #  endif\r
 #  define IRSND_BIT                             CONCAT(GPIO_Pin_, IRSND_BIT_NUMBER)\r
 #  define IRSND_TIMER                           CONCAT(TIM, IRSND_TIMER_NUMBER)\r
+#  define IRSND_TIMER_CHANNEL                   CONCAT(TIM_Channel_, IRSND_TIMER_CHANNEL_NUMBER)\r
 #  if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
 #    define IRSND_TIMER_RCC                     CONCAT(RCC_APB1Periph_TIM, IRSND_TIMER_NUMBER)\r
 #  elif (IRSND_TIMER_NUMBER == 1) || ((IRSND_TIMER_NUMBER >= 8) && (IRSND_TIMER_NUMBER <= 11))\r

diff --git a/irsndconfig.h b/irsndconfig.h
index 9c08c64aed73cceac8a33276c2a24ebfd08d3e5c..96037ce4c60a37cfcf1aa3437006a8dcee7423f7 100644 (file)
--- a/irsndconfig.h
+++ b/irsndconfig.h
@@ -5,7 +5,7 @@
  *\r
  * Copyright (c) 2010-2011 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irsndconfig.h,v 1.37 2012/05/24 06:55:11 fm Exp $\r
+ * $Id: irsndconfig.h,v 1.38 2012/06/05 12:00:46 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -110,7 +110,7 @@
 #  define IRSND_PORT_LETTER                     A\r
 #  define IRSND_BIT_NUMBER                      6\r
 #  define IRSND_TIMER_NUMBER                    10\r
-#  define IRSND_TIMER_CHANNEL                   1                       // only channel 1 can be used at the moment, others won't work\r
+#  define IRSND_TIMER_CHANNEL_NUMBER            1                       // only channel 1 can be used at the moment, others won't work\r
 \r
 /*---------------------------------------------------------------------------------------------------------------------------------------------------\r
  * Other target system\r