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[irmp.git] / irsnd.c
1 /*---------------------------------------------------------------------------------------------------------------------------------------------------
2 * @file irsnd.c
3 *
4 * Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de
5 *
6 * Supported AVR mikrocontrollers:
7 *
8 * ATtiny87, ATtiny167
9 * ATtiny45, ATtiny85
10 * ATtiny44 ATtiny84
11 * ATtiny2313 ATtiny4313
12 * ATmega8, ATmega16, ATmega32
13 * ATmega162
14 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P
15 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P
16 *
17 * $Id: irsnd.c,v 1.103 2017/02/17 09:13:06 fm Exp $
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *---------------------------------------------------------------------------------------------------------------------------------------------------
24 */
25
26 #include "irsnd.h"
27
28 #ifndef F_CPU
29 # error F_CPU unkown
30 #endif
31
32 /*---------------------------------------------------------------------------------------------------------------------------------------------------
33 * ATtiny pin definition of OC0A / OC0B
34 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B
35 *---------------------------------------------------------------------------------------------------------------------------------------------------
36 */
37 #if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7
38 # if IRSND_OCx == IRSND_OC0A // OC0A
39 # define IRSND_PORT_LETTER B
40 # define IRSND_BIT_NUMBER 2
41 # elif IRSND_OCx == IRSND_OC0B // OC0B
42 # define IRSND_PORT_LETTER A
43 # define IRSND_BIT_NUMBER 7
44 # else
45 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
46 # endif // IRSND_OCx
47
48 #elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1
49 # if IRSND_OCx == IRSND_OC0A // OC0A
50 # define IRSND_PORT_LETTER B
51 # define IRSND_BIT_NUMBER 0
52 # elif IRSND_OCx == IRSND_OC0B // OC0B
53 # define IRSND_PORT_LETTER B
54 # define IRSND_BIT_NUMBER 1
55 # else
56 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
57 # endif // IRSND_OCx
58
59 #elif defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny4313__) // ATtiny2313/4313 uses OC0A = PB2 or OC0B = PD5
60 # if IRSND_OCx == IRSND_OC0A // OC0A
61 # define IRSND_PORT_LETTER B
62 # define IRSND_BIT_NUMBER 2
63 # elif IRSND_OCx == IRSND_OC0B // OC0B
64 # define IRSND_PORT_LETTER D
65 # define IRSND_BIT_NUMBER 5
66 # else
67 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
68 # endif // IRSND_OCx
69
70 #elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2
71 # if IRSND_OCx == IRSND_OC0A // OC0A
72 # define IRSND_PORT_LETTER A
73 # define IRSND_BIT_NUMBER 2
74 # else
75 # error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h
76 # endif // IRSND_OCx
77
78 #elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3
79 # if IRSND_OCx == IRSND_OC2 // OC2
80 # define IRSND_PORT_LETTER B
81 # define IRSND_BIT_NUMBER 3
82 # else
83 # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h
84 # endif // IRSND_OCx
85 #elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC0 = PB3 or OC2 = PD7
86 # if IRSND_OCx == IRSND_OC2 // OC2
87 # define IRSND_PORT_LETTER D
88 # define IRSND_BIT_NUMBER 7
89 # elif IRSND_OCx == IRSND_OC0 // OC0
90 # define IRSND_PORT_LETTER B
91 # define IRSND_BIT_NUMBER 3
92 # else
93 # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
94 # endif // IRSND_OCx
95
96 #elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0
97 # if IRSND_OCx == IRSND_OC2 // OC2
98 # define IRSND_PORT_LETTER B
99 # define IRSND_BIT_NUMBER 1
100 # elif IRSND_OCx == IRSND_OC0 // OC0
101 # define IRSND_PORT_LETTER B
102 # define IRSND_BIT_NUMBER 0
103 # else
104 # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
105 # endif // IRSND_OCx
106
107 #elif defined (__AVR_ATmega164__) \
108 || defined (__AVR_ATmega324__) \
109 || defined (__AVR_ATmega644__) \
110 || defined (__AVR_ATmega644P__) \
111 || defined (__AVR_ATmega1284__) \
112 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4
113 # if IRSND_OCx == IRSND_OC2A // OC2A
114 # define IRSND_PORT_LETTER D
115 # define IRSND_BIT_NUMBER 7
116 # elif IRSND_OCx == IRSND_OC2B // OC2B
117 # define IRSND_PORT_LETTER D
118 # define IRSND_BIT_NUMBER 6
119 # elif IRSND_OCx == IRSND_OC0A // OC0A
120 # define IRSND_PORT_LETTER B
121 # define IRSND_BIT_NUMBER 3
122 # elif IRSND_OCx == IRSND_OC0B // OC0B
123 # define IRSND_PORT_LETTER B
124 # define IRSND_BIT_NUMBER 4
125 # else
126 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
127 # endif // IRSND_OCx
128
129 #elif defined (__AVR_ATmega48__) \
130 || defined (__AVR_ATmega88__) \
131 || defined (__AVR_ATmega88P__) \
132 || defined (__AVR_ATmega168__) \
133 || defined (__AVR_ATmega168P__) \
134 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5
135 # if IRSND_OCx == IRSND_OC2A // OC2A
136 # define IRSND_PORT_LETTER B
137 # define IRSND_BIT_NUMBER 3
138 # elif IRSND_OCx == IRSND_OC2B // OC2B
139 # define IRSND_PORT_LETTER D
140 # define IRSND_BIT_NUMBER 3
141 # elif IRSND_OCx == IRSND_OC0A // OC0A
142 # define IRSND_PORT_LETTER D
143 # define IRSND_BIT_NUMBER 6
144 # elif IRSND_OCx == IRSND_OC0B // OC0B
145 # define IRSND_PORT_LETTER D
146 # define IRSND_BIT_NUMBER 5
147 # else
148 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
149 # endif // IRSND_OCx
150
151 #elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2
152 # if IRSND_OCx == IRSND_OC0
153 # define IRSND_PORT_LETTER B
154 # define IRSND_BIT_NUMBER 0
155 # elif IRSND_OCx == IRSND_OC1A
156 # define IRSND_PORT_LETTER D
157 # define IRSND_BIT_NUMBER 5
158 # elif IRSND_OCx == IRSND_OC1B
159 # define IRSND_PORT_LETTER E
160 # define IRSND_BIT_NUMBER 2
161 # endif // IRSND_OCx
162
163 #elif defined (__AVR_XMEGA__) // ATxmega
164 # if IRSND_OCx == IRSND_XMEGA_OC0A
165 # define IRSND_BIT_NUMBER 0
166 # elif IRSND_OCx == IRSND_XMEGA_OC0B
167 # define IRSND_BIT_NUMBER 1
168 # elif IRSND_OCx == IRSND_XMEGA_OC0C
169 # define IRSND_BIT_NUMBER 2
170 # elif IRSND_OCx == IRSND_XMEGA_OC0D
171 # define IRSND_BIT_NUMBER 3
172 # elif IRSND_OCx == IRSND_XMEGA_OC1A
173 # define IRSND_BIT_NUMBER 4
174 # elif IRSND_OCx == IRSND_XMEGA_OC1B
175 # define IRSND_BIT_NUMBER 5
176 # else
177 # error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h
178 # endif // IRSND_OCx
179
180 #elif defined (PIC_C18) // Microchip C18 compiler
181 //Nothing here to do here -> See irsndconfig.h
182 #elif defined (ARM_STM32) // STM32
183 //Nothing here to do here -> See irsndconfig.h
184 #elif defined(LIBOPENCM3)
185 //Nothing here to do here -> See irsndconfig.h
186 #elif defined (__xtensa__) // ESP8266
187 //Nothing here to do here -> See irsndconfig.h
188
189 /*---------------------------------------------------------------------------------------------------------------------------------------------------
190 * Macro digitalPinHasPWM bothers PIC_C18 compiler, but why?
191 *
192 * #elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3
193 * # if !digitalPinHasPWM(IRSND_PIN)
194 * # error need pin with PWM output.
195 * # endif
196 *---------------------------------------------------------------------------------------------------------------------------------------------------
197 */
198 #else
199 # if !defined (unix) && !defined (WIN32)
200 # error mikrocontroller not defined, please fill in definitions here.
201 # endif // unix, WIN32
202 #endif // __AVR...
203
204 #if defined(__AVR_XMEGA__)
205 # define _CONCAT(a,b) a##b
206 # define CONCAT(a,b) _CONCAT(a,b)
207 # define IRSND_PORT IRSND_PORT_PRE.OUT
208 # define IRSND_DDR IRSND_PORT_PRE.DIR
209 # define IRSND_PIN IRSND_PORT_PRE.IN
210 # define IRSND_BIT IRSND_BIT_NUMBER
211 #elif defined(ATMEL_AVR)
212 # define _CONCAT(a,b) a##b
213 # define CONCAT(a,b) _CONCAT(a,b)
214 # define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)
215 # define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)
216 # define IRSND_BIT IRSND_BIT_NUMBER
217 #endif
218
219 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
220 typedef uint16_t IRSND_PAUSE_LEN;
221 #else
222 typedef uint8_t IRSND_PAUSE_LEN;
223 #endif
224
225 /*---------------------------------------------------------------------------------------------------------------------------------------------------
226 * IR timings
227 *---------------------------------------------------------------------------------------------------------------------------------------------------
228 */
229 #define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)
230 #define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)
231 #define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)
232 #define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)
233 #define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)
234 #define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
235 #define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
236
237 #define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)
238 #define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)
239 #define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
240 #define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)
241 #define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)
242 #define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)
243 #define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
244
245 #define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)
246 #define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)
247 #define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)
248 #define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)
249 #define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)
250 #define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
251
252 #define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
253 #define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
254
255 #define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
256 #define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
257
258 #define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)
259 #define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)
260 #define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)
261 #define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)
262 #define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)
263 #define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
264
265 #define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)
266 #define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)
267 #define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)
268 #define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)
269 #define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)
270 #define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
271 #define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
272
273 #define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)
274 #define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)
275 #define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)
276 #define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)
277 #define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)
278 #define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
279 #define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
280
281 #define MITSU_HEAVY_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PULSE_TIME + 0.5)
282 #define MITSU_HEAVY_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PAUSE_TIME + 0.5)
283 #define MITSU_HEAVY_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_PULSE_TIME + 0.5)
284 #define MITSU_HEAVY_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_1_PAUSE_TIME + 0.5)
285 #define MITSU_HEAVY_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_0_PAUSE_TIME + 0.5)
286 #define MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MITSU_HEAVY_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
287
288 #define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)
289 #define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)
290 #define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)
291 #define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)
292 #define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)
293 #define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
294
295 #define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
296 #define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
297 #define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
298
299 #define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)
300 #define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)
301 #define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)
302 #define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)
303 #define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)
304 #define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
305
306 #define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)
307 #define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)
308 #define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)
309 #define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
310 #define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
311
312 #define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)
313 #define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)
314 #define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)
315 #define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
316 #define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
317
318 #define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)
319 #define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)
320 #define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)
321 #define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)
322 #define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)
323 #define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
324
325 #define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)
326 #define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)
327 #define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)
328 #define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)
329 #define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)
330 #define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
331 #define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
332
333 #define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)
334 #define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)
335 #define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)
336 #define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)
337 #define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)
338 #define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
339 #define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
340
341 #define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)
342 #define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)
343 #define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)
344 #define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)
345 #define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)
346 #define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)
347 #define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
348 #define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
349
350 #define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)
351 #define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)
352 #define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)
353 #define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)
354 #define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)
355 #define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)
356 #define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
357 #define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
358
359 #define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)
360 #define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)
361 #define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)
362 #define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)
363 #define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)
364 #define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)
365 #define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
366 #define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
367
368 #define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)
369 #define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)
370 #define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)
371 #define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)
372 #define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)
373 #define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)
374 #define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)
375 #define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)
376 #define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)
377 #define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)
378 #define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)
379 #define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
380
381 #define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)
382 #define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)
383 #define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
384 #define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
385 #define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
386
387 #define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
388
389 #define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
390 #define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
391 #define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
392
393 #define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
394 #define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)
395 #define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
396 #define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)
397 #define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
398
399 #ifdef PIC_C18 // PIC C18
400 # define IRSND_FREQ_TYPE uint8_t
401 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
402 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
403 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
404 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
405 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
406 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
407 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
408 #elif defined (ARM_STM32) // STM32
409 # define IRSND_FREQ_TYPE uint32_t
410 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
411 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
412 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
413 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
414 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
415 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
416 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
417 #elif defined(LIBOPENCM3)
418 # define IRSND_FREQ_TYPE uint32_t
419 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
420 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
421 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
422 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
423 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
424 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
425 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
426 #elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
427 # define IRSND_FREQ_TYPE float
428 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
429 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
430 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
431 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
432 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
433 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
434 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
435 #elif defined (__xtensa__) // ESP8266
436 # define IRSND_FREQ_TYPE float
437 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
438 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
439 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
440 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
441 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
442 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
443 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
444 #else // AVR
445 # if F_CPU >= 16000000L
446 # define AVR_PRESCALER 8
447 # else
448 # define AVR_PRESCALER 1
449 # endif
450 # define IRSND_FREQ_TYPE uint8_t
451 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)
452 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)
453 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)
454 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)
455 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)
456 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)
457 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)
458 #endif
459
460 #define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)
461 #define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)
462 #define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)
463 #define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)
464 #define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)
465 #define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
466
467 #define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)
468 #define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)
469 #define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)
470 #define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)
471 #define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)
472 #define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
473
474 #define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)
475 #define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)
476 #define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
477 #define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)
478 #define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)
479 #define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)
480 #define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
481
482 #define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)
483 #define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)
484 #define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)
485 #define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)
486 #define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)
487 #define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)
488 #define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
489
490 #define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)
491 #define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)
492 #define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)
493 #define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)
494 #define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)
495 #define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)
496 #define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
497
498 #define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)
499 #define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)
500 #define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)
501 #define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)
502 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
503 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
504
505 #define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)
506 #define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)
507 #define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)
508 #define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)
509 #define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)
510 #define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)
511 #define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
512
513 #define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)
514 #define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)
515 #define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)
516 #define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)
517 #define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)
518 #define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)
519 #define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
520
521 #define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)
522 #define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)
523 #define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)
524 #define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)
525 #define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)
526 #define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)
527 #define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
528
529 static volatile uint8_t irsnd_busy = 0;
530 static volatile uint8_t irsnd_protocol = 0;
531 static volatile uint8_t irsnd_buffer[11] = {0};
532 static volatile uint8_t irsnd_repeat = 0;
533 static volatile uint8_t irsnd_is_on = FALSE;
534
535 #if IRSND_USE_CALLBACK == 1
536 static void (*irsnd_callback_ptr) (uint8_t);
537 #endif // IRSND_USE_CALLBACK == 1
538
539 /*---------------------------------------------------------------------------------------------------------------------------------------------------
540 * Switch PWM on
541 *---------------------------------------------------------------------------------------------------------------------------------------------------
542 */
543 static void
544 irsnd_on (void)
545 {
546 if (! irsnd_is_on)
547 {
548 #ifndef ANALYZE
549 # if defined(PIC_C18) // PIC C18
550 PWMon();
551 // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)
552
553 # elif defined (ARM_STM32) // STM32
554 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode
555 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
556 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter
557
558 # elif defined (LIBOPENCM3) // STM32 whit libopencm3
559 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_PWM1);
560
561 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
562 analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%
563
564 # elif defined (__xtensa__) // ESP8266 (Arduino)
565 analogWrite(IRSND_PIN, 33 * 1023 / 100); // pwm 33%
566
567 # elif defined (__AVR_XMEGA__)
568 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
569 XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A
570 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
571 XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B
572 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
573 XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C
574 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
575 XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D
576 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
577 XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A
578 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
579 XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B
580 # else
581 # error wrong value of IRSND_OCx
582 # endif // IRSND_OCx
583
584 # else // AVR
585 # if IRSND_OCx == IRSND_OC2 // use OC2
586 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2
587 # elif IRSND_OCx == IRSND_OC2A // use OC2A
588 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A
589 # elif IRSND_OCx == IRSND_OC2B // use OC2B
590 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)
591 # elif IRSND_OCx == IRSND_OC0 // use OC0
592 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0
593 # elif IRSND_OCx == IRSND_OC0A // use OC0A
594 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A
595 # elif IRSND_OCx == IRSND_OC0B // use OC0B
596 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)
597 # else
598 # error wrong value of IRSND_OCx
599 # endif // IRSND_OCx
600 # endif // C18
601 #endif // ANALYZE
602
603 #if IRSND_USE_CALLBACK == 1
604 if (irsnd_callback_ptr)
605 {
606 (*irsnd_callback_ptr) (TRUE);
607 }
608 #endif // IRSND_USE_CALLBACK == 1
609
610 irsnd_is_on = TRUE;
611 }
612 }
613
614 /*---------------------------------------------------------------------------------------------------------------------------------------------------
615 * Switch PWM off
616 * @details Switches PWM off
617 *---------------------------------------------------------------------------------------------------------------------------------------------------
618 */
619 static void
620 irsnd_off (void)
621 {
622 if (irsnd_is_on)
623 {
624 #ifndef ANALYZE
625
626 # if defined(PIC_C18) // PIC C18
627 PWMoff();
628 // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)
629
630 # elif defined (ARM_STM32) // STM32
631 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter
632 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive
633 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
634 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value
635
636 # elif defined (LIBOPENCM3) // STM32
637 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);
638
639 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
640 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
641
642 # elif defined (__xtensa__) // ESP8266
643 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
644
645 # elif defined (__AVR_XMEGA__)
646 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
647 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected
648 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
649 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected
650 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
651 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected
652 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
653 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected
654 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
655 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected
656 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
657 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected
658 # else
659 # error wrong value of IRSND_OCx
660 # endif // IRSND_OCx
661
662 # else //AVR
663
664 # if IRSND_OCx == IRSND_OC2 // use OC2
665 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.
666 # elif IRSND_OCx == IRSND_OC2A // use OC2A
667 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.
668 # elif IRSND_OCx == IRSND_OC2B // use OC2B
669 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.
670 # elif IRSND_OCx == IRSND_OC0 // use OC0
671 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.
672 # elif IRSND_OCx == IRSND_OC0A // use OC0A
673 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.
674 # elif IRSND_OCx == IRSND_OC0B // use OC0B
675 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.
676 # else
677 # error wrong value of IRSND_OCx
678 # endif // IRSND_OCx
679 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
680 # endif //C18
681 #endif // ANALYZE
682
683 #if IRSND_USE_CALLBACK == 1
684 if (irsnd_callback_ptr)
685 {
686 (*irsnd_callback_ptr) (FALSE);
687 }
688 #endif // IRSND_USE_CALLBACK == 1
689
690 irsnd_is_on = FALSE;
691 }
692 }
693
694 /*---------------------------------------------------------------------------------------------------------------------------------------------------
695 * Set PWM frequency
696 * @details sets pwm frequency
697 *---------------------------------------------------------------------------------------------------------------------------------------------------
698 */
699 #if defined(__12F1840)
700 extern void pwm_init(uint16_t freq);
701 #include <stdio.h>
702 #endif
703
704 static void
705 irsnd_set_freq (IRSND_FREQ_TYPE freq)
706 {
707 #ifndef ANALYZE
708 # if defined(PIC_C18) // PIC C18 or XC8
709 # if defined(__12F1840) // XC8
710 TRISA2=0;
711 PR2=freq;
712 CCP1M0=1;
713 CCP1M1=1;
714 CCP1M2=1;
715 CCP1M3=1;
716 DC1B0=1;
717 DC1B1=0;
718 CCPR1L = 0b01101001;
719 TMR2IF = 0;
720 TMR2ON=1;
721 CCP1CON &=(~0b0011); // p 197 "active high"
722 # else // PIC C18
723 OpenPWM(freq);
724 SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%
725 # endif
726 PWMoff();
727 # elif defined (ARM_STM32) // STM32
728 static uint32_t TimeBaseFreq = 0;
729
730 if (TimeBaseFreq == 0)
731 {
732 RCC_ClocksTypeDef RCC_ClocksStructure;
733 /* Get system clocks and store timer clock in variable */
734 RCC_GetClocksFreq(&RCC_ClocksStructure);
735 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
736 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)
737 {
738 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;
739 }
740 else
741 {
742 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;
743 }
744 # else
745 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)
746 {
747 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;
748 }
749 else
750 {
751 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;
752 }
753 # endif
754 }
755
756 freq = TimeBaseFreq/freq;
757
758 /* Set frequency */
759 TIM_SetAutoreload(IRSND_TIMER, freq - 1);
760 /* Set duty cycle */
761 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);
762
763 # elif defined(LIBOPENCM3)
764 static uint32_t TimeBaseFreq = 0;
765
766 if (TimeBaseFreq == 0)
767 {
768 # if defined(STM32F0) || (IRSND_TIMER < PERIPH_BASE_APB2)
769 TimeBaseFreq = rcc_apb1_frequency;
770 # else
771 TimeBaseFreq = rcc_apb2_frequency;
772 # endif
773 /* Timer clock is doubled, if the APB prescaler is greater than 1 */
774 if (TimeBaseFreq != rcc_ahb_frequency)
775 TimeBaseFreq *= 2;
776 }
777 freq = TimeBaseFreq/freq;
778
779 /* Set frequency */
780 timer_set_period(IRSND_TIMER, freq - 1);
781 /* Set duty cycle to 33% */
782 timer_set_oc_value(IRSND_TIMER, IRSND_TIMER_CHANNEL, (freq + 2) / 3);
783 timer_set_counter(IRSND_TIMER, 0);
784 timer_enable_counter(IRSND_TIMER);
785
786 # elif defined (TEENSY_ARM_CORTEX_M4)
787 analogWriteResolution(8); // 8 bit
788 analogWriteFrequency(IRSND_PIN, freq);
789 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
790
791 #elif defined (__xtensa__)
792 // analogWriteRange(255);
793 analogWriteFreq(freq);
794 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
795
796 # elif defined (__AVR_XMEGA__)
797 XMEGA_Timer.CCA = freq;
798
799 # else // AVR
800
801 # if IRSND_OCx == IRSND_OC2
802 OCR2 = freq; // use register OCR2 for OC2
803 # elif IRSND_OCx == IRSND_OC2A // use OC2A
804 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
805 # elif IRSND_OCx == IRSND_OC2B // use OC2B
806 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
807 # elif IRSND_OCx == IRSND_OC0 // use OC0
808 OCR0 = freq; // use register OCR2 for OC2
809 # elif IRSND_OCx == IRSND_OC0A // use OC0A
810 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
811 # elif IRSND_OCx == IRSND_OC0B // use OC0B
812 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
813 # else
814 # error wrong value of IRSND_OCx
815 # endif
816 # endif //PIC_C18
817 #endif // ANALYZE
818 }
819
820 /*---------------------------------------------------------------------------------------------------------------------------------------------------
821 * Initialize the PWM
822 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels
823 *---------------------------------------------------------------------------------------------------------------------------------------------------
824 */
825 void
826 irsnd_init (void)
827 {
828 #ifndef ANALYZE
829 # if defined(PIC_C18) // PIC C18 or XC8 compiler
830 # if ! defined(__12F1840) // only C18:
831 OpenTimer;
832 # endif
833 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
834 IRSND_PIN = 0; // set IO to outout
835 PWMoff();
836 # elif defined (ARM_STM32) // STM32
837 GPIO_InitTypeDef GPIO_InitStructure;
838 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
839 TIM_OCInitTypeDef TIM_OCInitStructure;
840
841 /* GPIOx clock enable */
842 # if defined (ARM_STM32L1XX)
843 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);
844 # elif defined (ARM_STM32F10X)
845 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
846 // RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping
847 # elif defined (ARM_STM32F4XX)
848 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
849 # endif
850
851 /* GPIO Configuration */
852 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;
853 # if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)
854 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
855 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
856 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
857 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
858 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
859 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);
860 # elif defined (ARM_STM32F10X)
861 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
862 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
863 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
864 // GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping
865 # endif
866
867 /* TIMx clock enable */
868 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
869 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
870 # else
871 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
872 # endif
873
874 /* Time base configuration */
875 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later
876 TIM_TimeBaseStructure.TIM_Prescaler = 0;
877 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
878 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
879 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);
880
881 /* PWM1 Mode configuration */
882 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
883 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
884 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later
885 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
886 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);
887
888 /* Preload configuration */
889 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);
890 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);
891
892 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency
893
894 # elif defined (LIBOPENCM3)
895 /* GPIOx clock enable */
896 rcc_periph_clock_enable(IRSND_PORT_RCC);
897 /* TIMx clock enable */
898 rcc_periph_clock_enable(IRSND_TIMER_RCC);
899
900 /* Time base configuration */
901 /* Stop timer and set it to its default mode (edge-aligned upcounting) */
902 timer_reset(IRSND_TIMER);
903
904 /* PWM Mode configuration */
905 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);
906 timer_enable_oc_output(IRSND_TIMER, IRSND_TIMER_CHANNEL);
907 timer_enable_break_main_output(IRSND_TIMER);
908 /* Output polarity and GPIO Configuration */
909 # if 1
910 /* (active) high is the default output polarity */
911 gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,
912 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, IRSND_BIT);
913 # else
914 timer_set_oc_polarity_low(IRSND_TIMER, IRSND_TIMER_CHANNEL);
915 gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,
916 GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, IRSND_BIT);
917 # endif
918
919 # elif defined (TEENSY_ARM_CORTEX_M4)
920 if (!digitalPinHasPWM(IRSND_PIN))
921 {
922 return;
923 }
924
925 # elif defined (__xtensa__)
926 pinMode(IRSND_PIN, OUTPUT);
927 irsnd_set_freq (IRSND_FREQ_36_KHZ);
928
929 # elif defined (__AVR_XMEGA__)
930 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
931 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
932
933 XMEGA_Timer.PER = 0xFFFF; //Topwert
934 XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC
935
936 # if AVR_PRESCALER == 8
937 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8
938 # else
939 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1
940 # endif
941
942 # else // AVR
943 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
944 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
945
946 # if IRSND_OCx == IRSND_OC2 // use OC2
947 TCCR2 = (1<<WGM21); // CTC mode
948 # if AVR_PRESCALER == 8
949 TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8
950 # else
951 TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1
952 # endif
953 # elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B
954 TCCR2A = (1<<WGM21); // CTC mode
955 # if AVR_PRESCALER == 8
956 TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8
957 # else
958 TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1
959 # endif
960 # elif IRSND_OCx == IRSND_OC0 // use OC0
961 TCCR0 = (1<<WGM01); // CTC mode
962 # if AVR_PRESCALER == 8
963 TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8
964 # else
965 TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1
966 # endif
967 # elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B
968 TCCR0A = (1<<WGM01); // CTC mode
969 # if AVR_PRESCALER == 8
970 TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8
971 # else
972 TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1
973 # endif
974 # else
975 # error wrong value of IRSND_OCx
976 # endif
977 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
978 # endif //PIC_C18
979 #endif // ANALYZE
980 }
981
982 #if IRSND_USE_CALLBACK == 1
983 void
984 irsnd_set_callback_ptr (void (*cb)(uint8_t))
985 {
986 irsnd_callback_ptr = cb;
987 }
988 #endif // IRSND_USE_CALLBACK == 1
989
990 uint8_t
991 irsnd_is_busy (void)
992 {
993 return irsnd_busy;
994 }
995
996 static uint16_t
997 bitsrevervse (uint16_t x, uint8_t len)
998 {
999 uint16_t xx = 0;
1000
1001 while(len)
1002 {
1003 xx <<= 1;
1004 if (x & 1)
1005 {
1006 xx |= 1;
1007 }
1008 x >>= 1;
1009 len--;
1010 }
1011 return xx;
1012 }
1013
1014
1015 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1016 static uint8_t sircs_additional_bitlen;
1017 #endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1018
1019 uint8_t
1020 irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)
1021 {
1022 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1023 static uint8_t toggle_bit_recs80;
1024 #endif
1025 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
1026 static uint8_t toggle_bit_recs80ext;
1027 #endif
1028 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
1029 static uint8_t toggle_bit_rc5;
1030 #endif
1031 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
1032 static uint8_t toggle_bit_rc6;
1033 #endif
1034 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
1035 static uint8_t toggle_bit_thomson;
1036 #endif
1037 uint16_t address;
1038 uint16_t command;
1039
1040 if (do_wait)
1041 {
1042 while (irsnd_busy)
1043 {
1044 // do nothing;
1045 }
1046 }
1047 else if (irsnd_busy)
1048 {
1049 return (FALSE);
1050 }
1051
1052 irsnd_protocol = irmp_data_p->protocol;
1053 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;
1054
1055 switch (irsnd_protocol)
1056 {
1057 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1058 case IRMP_SIRCS_PROTOCOL:
1059 {
1060 // uint8_t sircs_additional_command_len;
1061 uint8_t sircs_additional_address_len;
1062
1063 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen
1064
1065 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)
1066 {
1067 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;
1068 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);
1069 }
1070 else
1071 {
1072 // sircs_additional_command_len = sircs_additional_bitlen;
1073 sircs_additional_address_len = 0;
1074 }
1075
1076 command = bitsrevervse (irmp_data_p->command, 15);
1077
1078 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC
1079 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****
1080
1081 if (sircs_additional_address_len > 0)
1082 {
1083 address = bitsrevervse (irmp_data_p->address, 5);
1084 irsnd_buffer[1] |= (address & 0x0010) >> 4;
1085 irsnd_buffer[2] = (address & 0x000F) << 4;
1086 }
1087 irsnd_busy = TRUE;
1088 break;
1089 }
1090 #endif
1091 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
1092 case IRMP_APPLE_PROTOCOL:
1093 {
1094 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command
1095 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)
1096
1097 address = bitsrevervse (address, NEC_ADDRESS_LEN);
1098 command = bitsrevervse (command, NEC_COMMAND_LEN);
1099
1100 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command
1101
1102 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1103 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1104 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1105 irsnd_buffer[3] = 0x8B; // 10001011 (id)
1106 irsnd_busy = TRUE;
1107 break;
1108 }
1109 case IRMP_NEC_PROTOCOL:
1110 {
1111 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);
1112 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);
1113
1114 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1115 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1116 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1117 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
1118 irsnd_busy = TRUE;
1119 break;
1120 }
1121 #endif
1122 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1123 case IRMP_NEC16_PROTOCOL:
1124 {
1125 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);
1126 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);
1127
1128 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA
1129 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1130 irsnd_busy = TRUE;
1131 break;
1132 }
1133 #endif
1134 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1135 case IRMP_NEC42_PROTOCOL:
1136 {
1137 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);
1138 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);
1139
1140 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA
1141 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa
1142 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa
1143 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC
1144 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc
1145 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc
1146 irsnd_busy = TRUE;
1147 break;
1148 }
1149 #endif
1150 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1151 case IRMP_LGAIR_PROTOCOL:
1152 {
1153 address = irmp_data_p->address;
1154 command = irmp_data_p->command;
1155
1156 irsnd_buffer[0] = ( (address & 0x00FF)); // AAAAAAAA
1157 irsnd_buffer[1] = ( (command & 0xFF00) >> 8); // CCCCCCCC
1158 irsnd_buffer[2] = ( (command & 0x00FF)); // CCCCCCCC
1159 irsnd_buffer[3] = (( ((command & 0xF000) >> 12) + // checksum
1160 ((command & 0x0F00) >> 8) +
1161 ((command & 0x00F0) >>4 ) +
1162 ((command & 0x000F))) & 0x000F) << 4;
1163 irsnd_busy = TRUE;
1164 break;
1165 }
1166 #endif
1167 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1168 case IRMP_SAMSUNG_PROTOCOL:
1169 {
1170 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1171 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);
1172
1173 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1174 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1175 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC
1176 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc
1177 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000
1178 irsnd_busy = TRUE;
1179 break;
1180 }
1181 case IRMP_SAMSUNG32_PROTOCOL:
1182 {
1183 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1184 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);
1185
1186 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1187 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1188 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1189 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC
1190 irsnd_busy = TRUE;
1191 break;
1192 }
1193 #endif
1194 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1195 case IRMP_SAMSUNG48_PROTOCOL:
1196 {
1197 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1198 command = bitsrevervse (irmp_data_p->command, 16);
1199
1200 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1201 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1202 irsnd_buffer[2] = ((command & 0xFF00) >> 8); // CCCCCCCC
1203 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
1204 irsnd_buffer[4] = (command & 0x00FF); // CCCCCCCC
1205 irsnd_buffer[5] = ~(command & 0x00FF); // cccccccc
1206 irsnd_busy = TRUE;
1207 break;
1208 }
1209 #endif
1210 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1211 case IRMP_MATSUSHITA_PROTOCOL:
1212 {
1213 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);
1214 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);
1215
1216 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC
1217 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA
1218 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA
1219 irsnd_busy = TRUE;
1220 break;
1221 }
1222 #endif
1223 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1224 case IRMP_TECHNICS_PROTOCOL:
1225 {
1226 command = bitsrevervse (irmp_data_p->command, TECHNICS_COMMAND_LEN);
1227
1228 irsnd_buffer[0] = (command & 0x07FC) >> 3; // CCCCCCCC
1229 irsnd_buffer[1] = ((command & 0x0007) << 5) | ((~command & 0x07C0) >> 6); // CCCccccc
1230 irsnd_buffer[2] = (~command & 0x003F) << 2; // cccccc
1231 irsnd_busy = TRUE;
1232 break;
1233 }
1234 #endif
1235 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1236 case IRMP_KASEIKYO_PROTOCOL:
1237 {
1238 uint8_t xor_value;
1239 uint16_t genre2;
1240
1241 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);
1242 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);
1243 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);
1244
1245 xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;
1246
1247 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1248 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1249 irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC
1250 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC
1251 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC
1252
1253 xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];
1254
1255 irsnd_buffer[5] = xor_value;
1256 irsnd_busy = TRUE;
1257 break;
1258 }
1259 #endif
1260 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
1261 case IRMP_PANASONIC_PROTOCOL:
1262 {
1263 address = bitsrevervse (irmp_data_p->address, PANASONIC_ADDRESS_LEN);
1264 command = bitsrevervse (irmp_data_p->command, PANASONIC_COMMAND_LEN);
1265
1266 irsnd_buffer[0] = 0x40; // 01000000
1267 irsnd_buffer[1] = 0x04; // 00000100
1268 irsnd_buffer[2] = 0x01; // 00000001
1269 irsnd_buffer[3] = (address & 0xFF00) >> 8; // AAAAAAAA
1270 irsnd_buffer[4] = (address & 0x00FF); // AAAAAAAA
1271 irsnd_buffer[5] = (command & 0xFF00) >> 8; // CCCCCCCC
1272 irsnd_buffer[6] = (command & 0x00FF); // CCCCCCCC
1273
1274 irsnd_busy = TRUE;
1275 break;
1276 }
1277 #endif
1278 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
1279 case IRMP_MITSU_HEAVY_PROTOCOL:
1280 {
1281 address = irmp_data_p->address;
1282 command = irmp_data_p->command;
1283
1284 irsnd_buffer[0] = 0x4A;
1285 irsnd_buffer[1] = 0x75;
1286 irsnd_buffer[2] = 0xC3;
1287 irsnd_buffer[3] = 0x64;
1288 irsnd_buffer[4] = 0x9B;
1289 irsnd_buffer[5] = ~(address & 0xFF00) >> 8;
1290 irsnd_buffer[6] = (address & 0xFF00) >> 8;
1291 irsnd_buffer[7] = ~(address & 0x00FF);
1292 irsnd_buffer[8] = (address & 0x00FF);
1293 irsnd_buffer[9] = ~(command & 0x00FF);
1294 irsnd_buffer[10] = (command & 0x00FF);
1295
1296 irsnd_busy = TRUE;
1297 break;
1298 }
1299 #endif
1300 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1301 case IRMP_RECS80_PROTOCOL:
1302 {
1303 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x80;
1304
1305 irsnd_buffer[0] = toggle_bit_recs80 | ((irmp_data_p->address & 0x000F) << 4) |
1306 ((irmp_data_p->command & 0x003C) >> 2); // TAAACCCC
1307 irsnd_buffer[1] = (irmp_data_p->command & 0x03) << 6; // CC000000
1308 irsnd_busy = TRUE;
1309 break;
1310 }
1311 #endif
1312 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
1313 case IRMP_RECS80EXT_PROTOCOL:
1314 {
1315 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;
1316
1317 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |
1318 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC
1319 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000
1320 irsnd_busy = TRUE;
1321 break;
1322 }
1323 #endif
1324 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
1325 case IRMP_RC5_PROTOCOL:
1326 {
1327 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;
1328
1329 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |
1330 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC
1331 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000
1332 irsnd_busy = TRUE;
1333 break;
1334 }
1335 #endif
1336 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
1337 case IRMP_RC6_PROTOCOL:
1338 {
1339 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1340
1341 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000
1342 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC
1343 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC
1344 irsnd_busy = TRUE;
1345 break;
1346 }
1347 #endif
1348 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
1349 case IRMP_RC6A_PROTOCOL:
1350 {
1351 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1352
1353 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110
1354 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA
1355 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC
1356 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1357 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC
1358 irsnd_busy = TRUE;
1359 break;
1360 }
1361 #endif
1362 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1363 case IRMP_DENON_PROTOCOL:
1364 {
1365 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)
1366 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC
1367 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)
1368 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc
1369 irsnd_busy = TRUE;
1370 break;
1371 }
1372 #endif
1373 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
1374 case IRMP_THOMSON_PROTOCOL:
1375 {
1376 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;
1377
1378 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)
1379 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC
1380 irsnd_busy = TRUE;
1381 break;
1382 }
1383 #endif
1384 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
1385 case IRMP_BOSE_PROTOCOL:
1386 {
1387 command = bitsrevervse (irmp_data_p->command, BOSE_COMMAND_LEN);
1388
1389 irsnd_buffer[0] = (command & 0xFF00) >> 8; // CCCCCCCC
1390 irsnd_buffer[1] = ~((command & 0xFF00) >> 8); // cccccccc
1391 irsnd_busy = TRUE;
1392 break;
1393 }
1394 #endif
1395 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
1396 case IRMP_NUBERT_PROTOCOL:
1397 {
1398 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1399 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1400 irsnd_busy = TRUE;
1401 break;
1402 }
1403 #endif
1404 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
1405 case IRMP_FAN_PROTOCOL:
1406 {
1407 irsnd_buffer[0] = irmp_data_p->command >> 3; // CCCCCCCC
1408 irsnd_buffer[1] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1409 irsnd_busy = TRUE;
1410 break;
1411 }
1412 #endif
1413 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
1414 case IRMP_SPEAKER_PROTOCOL:
1415 {
1416 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1417 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1418 irsnd_busy = TRUE;
1419 break;
1420 }
1421 #endif
1422 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1423 case IRMP_BANG_OLUFSEN_PROTOCOL:
1424 {
1425 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC
1426 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC
1427 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1428 irsnd_busy = TRUE;
1429 break;
1430 }
1431 #endif
1432 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1433 case IRMP_GRUNDIG_PROTOCOL:
1434 {
1435 command = bitsrevervse (irmp_data_p->command, TELEFUNKEN_COMMAND_LEN);
1436
1437 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)
1438 irsnd_buffer[1] = 0xC0; // 11
1439 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)
1440 irsnd_buffer[3] = (command << 6) & 0xC0; // CC
1441
1442 irsnd_busy = TRUE;
1443 break;
1444 }
1445 #endif
1446 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
1447 case IRMP_TELEFUNKEN_PROTOCOL:
1448 {
1449 irsnd_buffer[0] = irmp_data_p->command >> 7; // CCCCCCCC
1450 irsnd_buffer[1] = (irmp_data_p->command << 1) & 0xff; // CCCCCCC
1451
1452 irsnd_busy = TRUE;
1453 break;
1454 }
1455 #endif
1456 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1457 case IRMP_IR60_PROTOCOL:
1458 {
1459 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);
1460 #if 0
1461 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)
1462 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)
1463 #else
1464 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)
1465 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)
1466 #endif
1467
1468 irsnd_busy = TRUE;
1469 break;
1470 }
1471 #endif
1472 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1473 case IRMP_NOKIA_PROTOCOL:
1474 {
1475 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);
1476 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);
1477
1478 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)
1479 irsnd_buffer[1] = 0xFF; // 11111111
1480 irsnd_buffer[2] = 0x80; // 1
1481 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)
1482 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA
1483 irsnd_buffer[5] = (address << 7); // A
1484
1485 irsnd_busy = TRUE;
1486 break;
1487 }
1488 #endif
1489 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
1490 case IRMP_SIEMENS_PROTOCOL:
1491 {
1492 irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA
1493 irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC
1494 irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc
1495
1496 irsnd_busy = TRUE;
1497 break;
1498 }
1499 #endif
1500 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
1501 case IRMP_RUWIDO_PROTOCOL:
1502 {
1503 irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA
1504 irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC
1505 irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c
1506 irsnd_busy = TRUE;
1507 break;
1508 }
1509 #endif
1510 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
1511 case IRMP_FDC_PROTOCOL:
1512 {
1513 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);
1514 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);
1515
1516 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA
1517 irsnd_buffer[1] = 0; // 00000000
1518 irsnd_buffer[2] = 0; // 0000RRRR
1519 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC
1520 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc
1521 irsnd_busy = TRUE;
1522 break;
1523 }
1524 #endif
1525 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
1526 case IRMP_RCCAR_PROTOCOL:
1527 {
1528 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1
1529 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V
1530
1531 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3
1532 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0
1533
1534 irsnd_busy = TRUE;
1535 break;
1536 }
1537 #endif
1538 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
1539 case IRMP_JVC_PROTOCOL:
1540 {
1541 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);
1542 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);
1543
1544 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC
1545 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1546
1547 irsnd_busy = TRUE;
1548 break;
1549 }
1550 #endif
1551 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
1552 case IRMP_NIKON_PROTOCOL:
1553 {
1554 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC
1555 irsnd_busy = TRUE;
1556 break;
1557 }
1558 #endif
1559 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
1560 case IRMP_LEGO_PROTOCOL:
1561 {
1562 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);
1563
1564 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1565 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc
1566 irsnd_busy = TRUE;
1567 break;
1568 }
1569 #endif
1570 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
1571 case IRMP_A1TVBOX_PROTOCOL:
1572 {
1573 irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA
1574 irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC
1575 irsnd_buffer[2] = (irmp_data_p->command << 6); // CC
1576
1577 irsnd_busy = TRUE;
1578 break;
1579 }
1580 #endif
1581 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
1582 case IRMP_ROOMBA_PROTOCOL:
1583 {
1584 irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.
1585 irsnd_busy = TRUE;
1586 break;
1587 }
1588 #endif
1589 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
1590 case IRMP_PENTAX_PROTOCOL:
1591 {
1592 irsnd_buffer[0] = (irmp_data_p->command & 0x3F) << 2; // CCCCCC..
1593 irsnd_busy = TRUE;
1594 break;
1595 }
1596 #endif
1597 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
1598 # define ACP_SET_BIT(acp24_bitno, c, irmp_bitno) \
1599 do \
1600 { \
1601 if ((c) & (1<<(irmp_bitno))) \
1602 { \
1603 irsnd_buffer[((acp24_bitno)>>3)] |= 1 << (((7 - (acp24_bitno)) & 0x07)); \
1604 } \
1605 } while (0)
1606
1607 case IRMP_ACP24_PROTOCOL:
1608 {
1609 uint16_t cmd = irmp_data_p->command;
1610 uint8_t i;
1611
1612 address = bitsrevervse (irmp_data_p->address, ACP24_ADDRESS_LEN);
1613
1614 for (i = 0; i < 8; i++)
1615 {
1616 irsnd_buffer[i] = 0x00; // CCCCCCCC
1617 }
1618
1619 // ACP24-Frame:
1620 // 1 2 3 4 5 6
1621 // 0123456789012345678901234567890123456789012345678901234567890123456789
1622 // N VVMMM ? ??? t vmA x y TTTT
1623 //
1624 // irmp_data_p->command:
1625 //
1626 // 5432109876543210
1627 // NAVVvMMMmtxyTTTT
1628
1629 ACP_SET_BIT( 0, cmd, 15);
1630 ACP_SET_BIT(24, cmd, 14);
1631 ACP_SET_BIT( 2, cmd, 13);
1632 ACP_SET_BIT( 3, cmd, 12);
1633 ACP_SET_BIT(22, cmd, 11);
1634 ACP_SET_BIT( 4, cmd, 10);
1635 ACP_SET_BIT( 5, cmd, 9);
1636 ACP_SET_BIT( 6, cmd, 8);
1637 ACP_SET_BIT(23, cmd, 7);
1638 ACP_SET_BIT(20, cmd, 6);
1639 ACP_SET_BIT(26, cmd, 5);
1640 ACP_SET_BIT(44, cmd, 4);
1641 ACP_SET_BIT(66, cmd, 3);
1642 ACP_SET_BIT(67, cmd, 2);
1643 ACP_SET_BIT(68, cmd, 1);
1644 ACP_SET_BIT(69, cmd, 0);
1645
1646 irsnd_busy = TRUE;
1647 break;
1648 }
1649 #endif
1650
1651 default:
1652 {
1653 break;
1654 }
1655 }
1656
1657 return irsnd_busy;
1658 }
1659
1660 void
1661 irsnd_stop (void)
1662 {
1663 irsnd_repeat = 0;
1664 }
1665
1666 /*---------------------------------------------------------------------------------------------------------------------------------------------------
1667 * ISR routine
1668 * @details ISR routine, called 10000 times per second
1669 *---------------------------------------------------------------------------------------------------------------------------------------------------
1670 */
1671 uint8_t
1672 irsnd_ISR (void)
1673 {
1674 static uint8_t send_trailer = FALSE;
1675 static uint8_t current_bit = 0xFF;
1676 static uint8_t pulse_counter = 0;
1677 static IRSND_PAUSE_LEN pause_counter = 0;
1678 static uint8_t startbit_pulse_len = 0;
1679 static IRSND_PAUSE_LEN startbit_pause_len = 0;
1680 static uint8_t pulse_1_len = 0;
1681 static uint8_t pause_1_len = 0;
1682 static uint8_t pulse_0_len = 0;
1683 static uint8_t pause_0_len = 0;
1684 static uint8_t has_stop_bit = 0;
1685 static uint8_t new_frame = TRUE;
1686 static uint8_t complete_data_len = 0;
1687 static uint8_t n_repeat_frames = 0; // number of repetition frames
1688 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions
1689 static uint8_t auto_repetition_counter = 0; // auto_repetition counter
1690 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!
1691 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!
1692 static uint8_t repeat_counter = 0; // repeat counter
1693 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!
1694 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!
1695 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1696 static uint8_t last_bit_value;
1697 #endif
1698 static uint8_t pulse_len = 0xFF;
1699 static IRSND_PAUSE_LEN pause_len = 0xFF;
1700
1701 if (irsnd_busy)
1702 {
1703 if (current_bit == 0xFF && new_frame) // start of transmission...
1704 {
1705 if (auto_repetition_counter > 0)
1706 {
1707 auto_repetition_pause_counter++;
1708
1709 if (auto_repetition_pause_counter >= auto_repetition_pause_len)
1710 {
1711 auto_repetition_pause_counter = 0;
1712
1713 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1714 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame
1715 {
1716 current_bit = 16;
1717 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;
1718 }
1719 else
1720 #endif
1721 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1722 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame
1723 {
1724 current_bit = 15;
1725 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;
1726 }
1727 else
1728 #endif
1729 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1730 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame
1731 {
1732 current_bit = 7;
1733 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;
1734 }
1735 else
1736 #endif
1737 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1738 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame
1739 {
1740 if (auto_repetition_counter + 1 < n_auto_repetitions)
1741 {
1742 current_bit = 23;
1743 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;
1744 }
1745 else // nokia stop frame
1746 {
1747 current_bit = 0xFF;
1748 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
1749 }
1750 }
1751 else
1752 #endif
1753 {
1754 ;
1755 }
1756 }
1757 else
1758 {
1759 #ifdef ANALYZE
1760 if (irsnd_is_on)
1761 {
1762 putchar ('0');
1763 }
1764 else
1765 {
1766 putchar ('1');
1767 }
1768 #endif
1769 return irsnd_busy;
1770 }
1771 }
1772 else if (packet_repeat_pause_counter < repeat_frame_pause_len)
1773 {
1774 packet_repeat_pause_counter++;
1775 #ifdef ANALYZE
1776 if (irsnd_is_on)
1777 {
1778 putchar ('0');
1779 }
1780 else
1781 {
1782 putchar ('1');
1783 }
1784 #endif
1785 return irsnd_busy;
1786 }
1787 else
1788 {
1789 if (send_trailer)
1790 {
1791 irsnd_busy = FALSE;
1792 send_trailer = FALSE;
1793 return irsnd_busy;
1794 }
1795
1796 n_repeat_frames = irsnd_repeat;
1797
1798 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)
1799 {
1800 n_repeat_frames = 255;
1801 }
1802
1803 packet_repeat_pause_counter = 0;
1804 pulse_counter = 0;
1805 pause_counter = 0;
1806
1807 switch (irsnd_protocol)
1808 {
1809 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1810 case IRMP_SIRCS_PROTOCOL:
1811 {
1812 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;
1813 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;
1814 pulse_1_len = SIRCS_1_PULSE_LEN;
1815 pause_1_len = SIRCS_PAUSE_LEN - 1;
1816 pulse_0_len = SIRCS_0_PULSE_LEN;
1817 pause_0_len = SIRCS_PAUSE_LEN - 1;
1818 has_stop_bit = SIRCS_STOP_BIT;
1819 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;
1820 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame
1821 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause
1822 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;
1823 irsnd_set_freq (IRSND_FREQ_40_KHZ);
1824 break;
1825 }
1826 #endif
1827 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
1828 case IRMP_NEC_PROTOCOL:
1829 {
1830 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1831
1832 if (repeat_counter > 0)
1833 {
1834 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;
1835 complete_data_len = 0;
1836 }
1837 else
1838 {
1839 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1840 complete_data_len = NEC_COMPLETE_DATA_LEN;
1841 }
1842
1843 pulse_1_len = NEC_PULSE_LEN;
1844 pause_1_len = NEC_1_PAUSE_LEN - 1;
1845 pulse_0_len = NEC_PULSE_LEN;
1846 pause_0_len = NEC_0_PAUSE_LEN - 1;
1847 has_stop_bit = NEC_STOP_BIT;
1848 n_auto_repetitions = 1; // 1 frame
1849 auto_repetition_pause_len = 0;
1850 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1851 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1852 break;
1853 }
1854 #endif
1855 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1856 case IRMP_NEC16_PROTOCOL:
1857 {
1858 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1859 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1860 pulse_1_len = NEC_PULSE_LEN;
1861 pause_1_len = NEC_1_PAUSE_LEN - 1;
1862 pulse_0_len = NEC_PULSE_LEN;
1863 pause_0_len = NEC_0_PAUSE_LEN - 1;
1864 has_stop_bit = NEC_STOP_BIT;
1865 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit
1866 n_auto_repetitions = 1; // 1 frame
1867 auto_repetition_pause_len = 0;
1868 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1869 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1870 break;
1871 }
1872 #endif
1873 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1874 case IRMP_NEC42_PROTOCOL:
1875 {
1876 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1877 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1878 pulse_1_len = NEC_PULSE_LEN;
1879 pause_1_len = NEC_1_PAUSE_LEN - 1;
1880 pulse_0_len = NEC_PULSE_LEN;
1881 pause_0_len = NEC_0_PAUSE_LEN - 1;
1882 has_stop_bit = NEC_STOP_BIT;
1883 complete_data_len = NEC42_COMPLETE_DATA_LEN;
1884 n_auto_repetitions = 1; // 1 frame
1885 auto_repetition_pause_len = 0;
1886 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1887 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1888 break;
1889 }
1890 #endif
1891 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1892 case IRMP_LGAIR_PROTOCOL:
1893 {
1894 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1895 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1896 pulse_1_len = NEC_PULSE_LEN;
1897 pause_1_len = NEC_1_PAUSE_LEN - 1;
1898 pulse_0_len = NEC_PULSE_LEN;
1899 pause_0_len = NEC_0_PAUSE_LEN - 1;
1900 has_stop_bit = NEC_STOP_BIT;
1901 complete_data_len = LGAIR_COMPLETE_DATA_LEN;
1902 n_auto_repetitions = 1; // 1 frame
1903 auto_repetition_pause_len = 0;
1904 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1905 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1906 break;
1907 }
1908 #endif
1909 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1910 case IRMP_SAMSUNG_PROTOCOL:
1911 {
1912 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1913 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1914 pulse_1_len = SAMSUNG_PULSE_LEN;
1915 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1916 pulse_0_len = SAMSUNG_PULSE_LEN;
1917 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1918 has_stop_bit = SAMSUNG_STOP_BIT;
1919 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;
1920 n_auto_repetitions = 1; // 1 frame
1921 auto_repetition_pause_len = 0;
1922 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;
1923 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1924 break;
1925 }
1926
1927 case IRMP_SAMSUNG32_PROTOCOL:
1928 {
1929 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1930 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1931 pulse_1_len = SAMSUNG_PULSE_LEN;
1932 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1933 pulse_0_len = SAMSUNG_PULSE_LEN;
1934 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1935 has_stop_bit = SAMSUNG_STOP_BIT;
1936 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;
1937 n_auto_repetitions = SAMSUNG32_FRAMES; // 1 frame
1938 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1939 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;
1940 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1941 break;
1942 }
1943 #endif
1944 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1945 case IRMP_SAMSUNG48_PROTOCOL:
1946 {
1947 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1948 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1949 pulse_1_len = SAMSUNG_PULSE_LEN;
1950 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1951 pulse_0_len = SAMSUNG_PULSE_LEN;
1952 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1953 has_stop_bit = SAMSUNG_STOP_BIT;
1954 complete_data_len = SAMSUNG48_COMPLETE_DATA_LEN;
1955 n_auto_repetitions = SAMSUNG48_FRAMES; // 1 frame
1956 auto_repetition_pause_len = SAMSUNG48_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1957 repeat_frame_pause_len = SAMSUNG48_FRAME_REPEAT_PAUSE_LEN;
1958 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1959 break;
1960 }
1961 #endif
1962 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1963 case IRMP_MATSUSHITA_PROTOCOL:
1964 {
1965 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1966 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1967 pulse_1_len = MATSUSHITA_PULSE_LEN;
1968 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1969 pulse_0_len = MATSUSHITA_PULSE_LEN;
1970 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1971 has_stop_bit = MATSUSHITA_STOP_BIT;
1972 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;
1973 n_auto_repetitions = 1; // 1 frame
1974 auto_repetition_pause_len = 0;
1975 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1976 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1977 break;
1978 }
1979 #endif
1980 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1981 case IRMP_TECHNICS_PROTOCOL:
1982 {
1983 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1984 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1985 pulse_1_len = MATSUSHITA_PULSE_LEN;
1986 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1987 pulse_0_len = MATSUSHITA_PULSE_LEN;
1988 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1989 has_stop_bit = MATSUSHITA_STOP_BIT;
1990 complete_data_len = TECHNICS_COMPLETE_DATA_LEN; // here TECHNICS
1991 n_auto_repetitions = 1; // 1 frame
1992 auto_repetition_pause_len = 0;
1993 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1994 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1995 break;
1996 }
1997 #endif
1998 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1999 case IRMP_KASEIKYO_PROTOCOL:
2000 {
2001 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;
2002 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;
2003 pulse_1_len = KASEIKYO_PULSE_LEN;
2004 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;
2005 pulse_0_len = KASEIKYO_PULSE_LEN;
2006 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;
2007 has_stop_bit = KASEIKYO_STOP_BIT;
2008 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;
2009 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame
2010 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause
2011 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;
2012 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2013 break;
2014 }
2015 #endif
2016 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
2017 case IRMP_PANASONIC_PROTOCOL:
2018 {
2019 startbit_pulse_len = PANASONIC_START_BIT_PULSE_LEN;
2020 startbit_pause_len = PANASONIC_START_BIT_PAUSE_LEN - 1;
2021 pulse_1_len = PANASONIC_PULSE_LEN;
2022 pause_1_len = PANASONIC_1_PAUSE_LEN - 1;
2023 pulse_0_len = PANASONIC_PULSE_LEN;
2024 pause_0_len = PANASONIC_0_PAUSE_LEN - 1;
2025 has_stop_bit = PANASONIC_STOP_BIT;
2026 complete_data_len = PANASONIC_COMPLETE_DATA_LEN;
2027 n_auto_repetitions = PANASONIC_FRAMES; // 1 frame
2028 auto_repetition_pause_len = PANASONIC_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
2029 repeat_frame_pause_len = PANASONIC_FRAME_REPEAT_PAUSE_LEN;
2030 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2031 break;
2032 }
2033 #endif
2034 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
2035 case IRMP_MITSU_HEAVY_PROTOCOL:
2036 {
2037 startbit_pulse_len = MITSU_HEAVY_START_BIT_PULSE_LEN;
2038 startbit_pause_len = MITSU_HEAVY_START_BIT_PAUSE_LEN - 1;
2039 pulse_1_len = MITSU_HEAVY_PULSE_LEN;
2040 pause_1_len = MITSU_HEAVY_1_PAUSE_LEN - 1;
2041 pulse_0_len = MITSU_HEAVY_PULSE_LEN;
2042 pause_0_len = MITSU_HEAVY_0_PAUSE_LEN - 1;
2043 has_stop_bit = MITSU_HEAVY_STOP_BIT;
2044 complete_data_len = MITSU_HEAVY_COMPLETE_DATA_LEN;
2045 n_auto_repetitions = MITSU_HEAVY_FRAMES; // 1 frame
2046 auto_repetition_pause_len = 0;;
2047 repeat_frame_pause_len = MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN;
2048 irsnd_set_freq (IRSND_FREQ_40_KHZ);
2049 break;
2050 }
2051 #endif
2052 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
2053 case IRMP_RECS80_PROTOCOL:
2054 {
2055 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;
2056 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;
2057 pulse_1_len = RECS80_PULSE_LEN;
2058 pause_1_len = RECS80_1_PAUSE_LEN - 1;
2059 pulse_0_len = RECS80_PULSE_LEN;
2060 pause_0_len = RECS80_0_PAUSE_LEN - 1;
2061 has_stop_bit = RECS80_STOP_BIT;
2062 complete_data_len = RECS80_COMPLETE_DATA_LEN;
2063 n_auto_repetitions = 1; // 1 frame
2064 auto_repetition_pause_len = 0;
2065 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;
2066 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2067 break;
2068 }
2069 #endif
2070 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
2071 case IRMP_RECS80EXT_PROTOCOL:
2072 {
2073 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;
2074 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;
2075 pulse_1_len = RECS80EXT_PULSE_LEN;
2076 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;
2077 pulse_0_len = RECS80EXT_PULSE_LEN;
2078 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;
2079 has_stop_bit = RECS80EXT_STOP_BIT;
2080 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;
2081 n_auto_repetitions = 1; // 1 frame
2082 auto_repetition_pause_len = 0;
2083 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;
2084 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2085 break;
2086 }
2087 #endif
2088 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
2089 case IRMP_TELEFUNKEN_PROTOCOL:
2090 {
2091 startbit_pulse_len = TELEFUNKEN_START_BIT_PULSE_LEN;
2092 startbit_pause_len = TELEFUNKEN_START_BIT_PAUSE_LEN - 1;
2093 pulse_1_len = TELEFUNKEN_PULSE_LEN;
2094 pause_1_len = TELEFUNKEN_1_PAUSE_LEN - 1;
2095 pulse_0_len = TELEFUNKEN_PULSE_LEN;
2096 pause_0_len = TELEFUNKEN_0_PAUSE_LEN - 1;
2097 has_stop_bit = TELEFUNKEN_STOP_BIT;
2098 complete_data_len = TELEFUNKEN_COMPLETE_DATA_LEN;
2099 n_auto_repetitions = 1; // 1 frames
2100 auto_repetition_pause_len = 0; // TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN; // xx ms pause
2101 repeat_frame_pause_len = TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2102 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2103 break;
2104 }
2105 #endif
2106 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
2107 case IRMP_RC5_PROTOCOL:
2108 {
2109 startbit_pulse_len = RC5_BIT_LEN;
2110 startbit_pause_len = RC5_BIT_LEN;
2111 pulse_len = RC5_BIT_LEN;
2112 pause_len = RC5_BIT_LEN;
2113 has_stop_bit = RC5_STOP_BIT;
2114 complete_data_len = RC5_COMPLETE_DATA_LEN;
2115 n_auto_repetitions = 1; // 1 frame
2116 auto_repetition_pause_len = 0;
2117 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;
2118 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2119 break;
2120 }
2121 #endif
2122 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
2123 case IRMP_RC6_PROTOCOL:
2124 {
2125 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
2126 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
2127 pulse_len = RC6_BIT_LEN;
2128 pause_len = RC6_BIT_LEN;
2129 has_stop_bit = RC6_STOP_BIT;
2130 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;
2131 n_auto_repetitions = 1; // 1 frame
2132 auto_repetition_pause_len = 0;
2133 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
2134 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2135 break;
2136 }
2137 #endif
2138 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
2139 case IRMP_RC6A_PROTOCOL:
2140 {
2141 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
2142 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
2143 pulse_len = RC6_BIT_LEN;
2144 pause_len = RC6_BIT_LEN;
2145 has_stop_bit = RC6_STOP_BIT;
2146 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;
2147 n_auto_repetitions = 1; // 1 frame
2148 auto_repetition_pause_len = 0;
2149 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
2150 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2151 break;
2152 }
2153 #endif
2154 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
2155 case IRMP_DENON_PROTOCOL:
2156 {
2157 startbit_pulse_len = 0x00;
2158 startbit_pause_len = 0x00;
2159 pulse_1_len = DENON_PULSE_LEN;
2160 pause_1_len = DENON_1_PAUSE_LEN - 1;
2161 pulse_0_len = DENON_PULSE_LEN;
2162 pause_0_len = DENON_0_PAUSE_LEN - 1;
2163 has_stop_bit = DENON_STOP_BIT;
2164 complete_data_len = DENON_COMPLETE_DATA_LEN;
2165 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command
2166 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame
2167 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;
2168 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better
2169 break;
2170 }
2171 #endif
2172 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2173 case IRMP_THOMSON_PROTOCOL:
2174 {
2175 startbit_pulse_len = 0x00;
2176 startbit_pause_len = 0x00;
2177 pulse_1_len = THOMSON_PULSE_LEN;
2178 pause_1_len = THOMSON_1_PAUSE_LEN - 1;
2179 pulse_0_len = THOMSON_PULSE_LEN;
2180 pause_0_len = THOMSON_0_PAUSE_LEN - 1;
2181 has_stop_bit = THOMSON_STOP_BIT;
2182 complete_data_len = THOMSON_COMPLETE_DATA_LEN;
2183 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame
2184 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;
2185 repeat_frame_pause_len = THOMSON_FRAME_REPEAT_PAUSE_LEN;
2186 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2187 break;
2188 }
2189 #endif
2190 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2191 case IRMP_BOSE_PROTOCOL:
2192 {
2193 startbit_pulse_len = BOSE_START_BIT_PULSE_LEN;
2194 startbit_pause_len = BOSE_START_BIT_PAUSE_LEN - 1;
2195 pulse_1_len = BOSE_PULSE_LEN;
2196 pause_1_len = BOSE_1_PAUSE_LEN - 1;
2197 pulse_0_len = BOSE_PULSE_LEN;
2198 pause_0_len = BOSE_0_PAUSE_LEN - 1;
2199 has_stop_bit = BOSE_STOP_BIT;
2200 complete_data_len = BOSE_COMPLETE_DATA_LEN;
2201 n_auto_repetitions = BOSE_FRAMES; // 1 frame
2202 auto_repetition_pause_len = BOSE_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
2203 repeat_frame_pause_len = BOSE_FRAME_REPEAT_PAUSE_LEN;
2204 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2205 break;
2206 }
2207 #endif
2208 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2209 case IRMP_NUBERT_PROTOCOL:
2210 {
2211 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;
2212 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;
2213 pulse_1_len = NUBERT_1_PULSE_LEN;
2214 pause_1_len = NUBERT_1_PAUSE_LEN - 1;
2215 pulse_0_len = NUBERT_0_PULSE_LEN;
2216 pause_0_len = NUBERT_0_PAUSE_LEN - 1;
2217 has_stop_bit = NUBERT_STOP_BIT;
2218 complete_data_len = NUBERT_COMPLETE_DATA_LEN;
2219 n_auto_repetitions = NUBERT_FRAMES; // 2 frames
2220 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2221 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;
2222 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2223 break;
2224 }
2225 #endif
2226 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2227 case IRMP_FAN_PROTOCOL:
2228 {
2229 startbit_pulse_len = FAN_START_BIT_PULSE_LEN;
2230 startbit_pause_len = FAN_START_BIT_PAUSE_LEN - 1;
2231 pulse_1_len = FAN_1_PULSE_LEN;
2232 pause_1_len = FAN_1_PAUSE_LEN - 1;
2233 pulse_0_len = FAN_0_PULSE_LEN;
2234 pause_0_len = FAN_0_PAUSE_LEN - 1;
2235 has_stop_bit = FAN_STOP_BIT;
2236 complete_data_len = FAN_COMPLETE_DATA_LEN;
2237 n_auto_repetitions = FAN_FRAMES; // only 1 frame
2238 auto_repetition_pause_len = FAN_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2239 repeat_frame_pause_len = FAN_FRAME_REPEAT_PAUSE_LEN;
2240 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2241 break;
2242 }
2243 #endif
2244 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2245 case IRMP_SPEAKER_PROTOCOL:
2246 {
2247 startbit_pulse_len = SPEAKER_START_BIT_PULSE_LEN;
2248 startbit_pause_len = SPEAKER_START_BIT_PAUSE_LEN - 1;
2249 pulse_1_len = SPEAKER_1_PULSE_LEN;
2250 pause_1_len = SPEAKER_1_PAUSE_LEN - 1;
2251 pulse_0_len = SPEAKER_0_PULSE_LEN;
2252 pause_0_len = SPEAKER_0_PAUSE_LEN - 1;
2253 has_stop_bit = SPEAKER_STOP_BIT;
2254 complete_data_len = SPEAKER_COMPLETE_DATA_LEN;
2255 n_auto_repetitions = SPEAKER_FRAMES; // 2 frames
2256 auto_repetition_pause_len = SPEAKER_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2257 repeat_frame_pause_len = SPEAKER_FRAME_REPEAT_PAUSE_LEN;
2258 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2259 break;
2260 }
2261 #endif
2262 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2263 case IRMP_BANG_OLUFSEN_PROTOCOL:
2264 {
2265 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;
2266 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;
2267 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;
2268 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;
2269 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;
2270 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;
2271 has_stop_bit = BANG_OLUFSEN_STOP_BIT;
2272 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;
2273 n_auto_repetitions = 1; // 1 frame
2274 auto_repetition_pause_len = 0;
2275 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;
2276 last_bit_value = 0;
2277 irsnd_set_freq (IRSND_FREQ_455_KHZ);
2278 break;
2279 }
2280 #endif
2281 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2282 case IRMP_GRUNDIG_PROTOCOL:
2283 {
2284 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2285 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2286 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2287 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2288 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2289 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;
2290 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames
2291 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2292 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2293 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2294 break;
2295 }
2296 #endif
2297 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2298 case IRMP_IR60_PROTOCOL:
2299 {
2300 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2301 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2302 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2303 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2304 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2305 complete_data_len = IR60_COMPLETE_DATA_LEN;
2306 n_auto_repetitions = IR60_FRAMES; // 2 frames
2307 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2308 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2309 irsnd_set_freq (IRSND_FREQ_30_KHZ);
2310 break;
2311 }
2312 #endif
2313 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2314 case IRMP_NOKIA_PROTOCOL:
2315 {
2316 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2317 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2318 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2319 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2320 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2321 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
2322 n_auto_repetitions = NOKIA_FRAMES; // 2 frames
2323 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause
2324 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2325 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2326 break;
2327 }
2328 #endif
2329 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2330 case IRMP_SIEMENS_PROTOCOL:
2331 {
2332 startbit_pulse_len = SIEMENS_BIT_LEN;
2333 startbit_pause_len = SIEMENS_BIT_LEN;
2334 pulse_len = SIEMENS_BIT_LEN;
2335 pause_len = SIEMENS_BIT_LEN;
2336 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2337 complete_data_len = SIEMENS_COMPLETE_DATA_LEN;
2338 n_auto_repetitions = 1; // 1 frame
2339 auto_repetition_pause_len = 0;
2340 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;
2341 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2342 break;
2343 }
2344 #endif
2345 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2346 case IRMP_RUWIDO_PROTOCOL:
2347 {
2348 startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;
2349 startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;
2350 pulse_len = RUWIDO_BIT_PULSE_LEN;
2351 pause_len = RUWIDO_BIT_PAUSE_LEN;
2352 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2353 complete_data_len = RUWIDO_COMPLETE_DATA_LEN;
2354 n_auto_repetitions = 1; // 1 frame
2355 auto_repetition_pause_len = 0;
2356 repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;
2357 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2358 break;
2359 }
2360 #endif
2361 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2362 case IRMP_FDC_PROTOCOL:
2363 {
2364 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;
2365 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;
2366 complete_data_len = FDC_COMPLETE_DATA_LEN;
2367 pulse_1_len = FDC_PULSE_LEN;
2368 pause_1_len = FDC_1_PAUSE_LEN - 1;
2369 pulse_0_len = FDC_PULSE_LEN;
2370 pause_0_len = FDC_0_PAUSE_LEN - 1;
2371 has_stop_bit = FDC_STOP_BIT;
2372 n_auto_repetitions = 1; // 1 frame
2373 auto_repetition_pause_len = 0;
2374 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;
2375 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2376 break;
2377 }
2378 #endif
2379 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2380 case IRMP_RCCAR_PROTOCOL:
2381 {
2382 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;
2383 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;
2384 complete_data_len = RCCAR_COMPLETE_DATA_LEN;
2385 pulse_1_len = RCCAR_PULSE_LEN;
2386 pause_1_len = RCCAR_1_PAUSE_LEN - 1;
2387 pulse_0_len = RCCAR_PULSE_LEN;
2388 pause_0_len = RCCAR_0_PAUSE_LEN - 1;
2389 has_stop_bit = RCCAR_STOP_BIT;
2390 n_auto_repetitions = 1; // 1 frame
2391 auto_repetition_pause_len = 0;
2392 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;
2393 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2394 break;
2395 }
2396 #endif
2397 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2398 case IRMP_JVC_PROTOCOL:
2399 {
2400 if (repeat_counter != 0) // skip start bit if repetition frame
2401 {
2402 current_bit = 0;
2403 }
2404
2405 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;
2406 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;
2407 complete_data_len = JVC_COMPLETE_DATA_LEN;
2408 pulse_1_len = JVC_PULSE_LEN;
2409 pause_1_len = JVC_1_PAUSE_LEN - 1;
2410 pulse_0_len = JVC_PULSE_LEN;
2411 pause_0_len = JVC_0_PAUSE_LEN - 1;
2412 has_stop_bit = JVC_STOP_BIT;
2413 n_auto_repetitions = 1; // 1 frame
2414 auto_repetition_pause_len = 0;
2415 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;
2416 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2417 break;
2418 }
2419 #endif
2420 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2421 case IRMP_NIKON_PROTOCOL:
2422 {
2423 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;
2424 startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;
2425 complete_data_len = NIKON_COMPLETE_DATA_LEN;
2426 pulse_1_len = NIKON_PULSE_LEN;
2427 pause_1_len = NIKON_1_PAUSE_LEN - 1;
2428 pulse_0_len = NIKON_PULSE_LEN;
2429 pause_0_len = NIKON_0_PAUSE_LEN - 1;
2430 has_stop_bit = NIKON_STOP_BIT;
2431 n_auto_repetitions = 1; // 1 frame
2432 auto_repetition_pause_len = 0;
2433 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;
2434 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2435 break;
2436 }
2437 #endif
2438 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2439 case IRMP_LEGO_PROTOCOL:
2440 {
2441 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;
2442 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;
2443 complete_data_len = LEGO_COMPLETE_DATA_LEN;
2444 pulse_1_len = LEGO_PULSE_LEN;
2445 pause_1_len = LEGO_1_PAUSE_LEN - 1;
2446 pulse_0_len = LEGO_PULSE_LEN;
2447 pause_0_len = LEGO_0_PAUSE_LEN - 1;
2448 has_stop_bit = LEGO_STOP_BIT;
2449 n_auto_repetitions = 1; // 1 frame
2450 auto_repetition_pause_len = 0;
2451 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;
2452 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2453 break;
2454 }
2455 #endif
2456 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2457 case IRMP_A1TVBOX_PROTOCOL:
2458 {
2459 startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN
2460 startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN
2461 pulse_len = A1TVBOX_BIT_PULSE_LEN;
2462 pause_len = A1TVBOX_BIT_PAUSE_LEN;
2463 has_stop_bit = A1TVBOX_STOP_BIT;
2464 complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data
2465 n_auto_repetitions = 1; // 1 frame
2466 auto_repetition_pause_len = 0;
2467 repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;
2468 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2469 break;
2470 }
2471 #endif
2472 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2473 case IRMP_ROOMBA_PROTOCOL:
2474 {
2475 startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;
2476 startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;
2477 pulse_1_len = ROOMBA_1_PULSE_LEN;
2478 pause_1_len = ROOMBA_1_PAUSE_LEN - 1;
2479 pulse_0_len = ROOMBA_0_PULSE_LEN;
2480 pause_0_len = ROOMBA_0_PAUSE_LEN - 1;
2481 has_stop_bit = ROOMBA_STOP_BIT;
2482 complete_data_len = ROOMBA_COMPLETE_DATA_LEN;
2483 n_auto_repetitions = ROOMBA_FRAMES; // 8 frames
2484 auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2485 repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2486 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2487 break;
2488 }
2489 #endif
2490 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2491 case IRMP_PENTAX_PROTOCOL:
2492 {
2493 startbit_pulse_len = PENTAX_START_BIT_PULSE_LEN;
2494 startbit_pause_len = PENTAX_START_BIT_PAUSE_LEN;
2495 complete_data_len = PENTAX_COMPLETE_DATA_LEN;
2496 pulse_1_len = PENTAX_PULSE_LEN;
2497 pause_1_len = PENTAX_1_PAUSE_LEN - 1;
2498 pulse_0_len = PENTAX_PULSE_LEN;
2499 pause_0_len = PENTAX_0_PAUSE_LEN - 1;
2500 has_stop_bit = PENTAX_STOP_BIT;
2501 n_auto_repetitions = 1; // 1 frame
2502 auto_repetition_pause_len = 0;
2503 repeat_frame_pause_len = PENTAX_FRAME_REPEAT_PAUSE_LEN;
2504 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2505 break;
2506 }
2507 #endif
2508 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2509 case IRMP_ACP24_PROTOCOL:
2510 {
2511 startbit_pulse_len = ACP24_START_BIT_PULSE_LEN;
2512 startbit_pause_len = ACP24_START_BIT_PAUSE_LEN - 1;
2513 complete_data_len = ACP24_COMPLETE_DATA_LEN;
2514 pulse_1_len = ACP24_PULSE_LEN;
2515 pause_1_len = ACP24_1_PAUSE_LEN - 1;
2516 pulse_0_len = ACP24_PULSE_LEN;
2517 pause_0_len = ACP24_0_PAUSE_LEN - 1;
2518 has_stop_bit = ACP24_STOP_BIT;
2519 n_auto_repetitions = 1; // 1 frame
2520 auto_repetition_pause_len = 0;
2521 repeat_frame_pause_len = ACP24_FRAME_REPEAT_PAUSE_LEN;
2522 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2523 break;
2524 }
2525 #endif
2526 default:
2527 {
2528 irsnd_busy = FALSE;
2529 break;
2530 }
2531 }
2532 }
2533 }
2534
2535 if (irsnd_busy)
2536 {
2537 new_frame = FALSE;
2538
2539 switch (irsnd_protocol)
2540 {
2541 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
2542 case IRMP_SIRCS_PROTOCOL:
2543 #endif
2544 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
2545 case IRMP_NEC_PROTOCOL:
2546 #endif
2547 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2548 case IRMP_NEC16_PROTOCOL:
2549 #endif
2550 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
2551 case IRMP_NEC42_PROTOCOL:
2552 #endif
2553 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
2554 case IRMP_LGAIR_PROTOCOL:
2555 #endif
2556 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2557 case IRMP_SAMSUNG_PROTOCOL:
2558 case IRMP_SAMSUNG32_PROTOCOL:
2559 #endif
2560 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
2561 case IRMP_SAMSUNG48_PROTOCOL:
2562 #endif
2563 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2564 case IRMP_MATSUSHITA_PROTOCOL:
2565 #endif
2566 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2567 case IRMP_TECHNICS_PROTOCOL:
2568 #endif
2569 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
2570 case IRMP_KASEIKYO_PROTOCOL:
2571 #endif
2572 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
2573 case IRMP_PANASONIC_PROTOCOL:
2574 #endif
2575 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
2576 case IRMP_MITSU_HEAVY_PROTOCOL:
2577 #endif
2578 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
2579 case IRMP_RECS80_PROTOCOL:
2580 #endif
2581 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
2582 case IRMP_RECS80EXT_PROTOCOL:
2583 #endif
2584 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
2585 case IRMP_TELEFUNKEN_PROTOCOL:
2586 #endif
2587 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
2588 case IRMP_DENON_PROTOCOL:
2589 #endif
2590 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2591 case IRMP_BOSE_PROTOCOL:
2592 #endif
2593 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2594 case IRMP_NUBERT_PROTOCOL:
2595 #endif
2596 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2597 case IRMP_FAN_PROTOCOL:
2598 #endif
2599 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2600 case IRMP_SPEAKER_PROTOCOL:
2601 #endif
2602 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2603 case IRMP_BANG_OLUFSEN_PROTOCOL:
2604 #endif
2605 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2606 case IRMP_FDC_PROTOCOL:
2607 #endif
2608 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2609 case IRMP_RCCAR_PROTOCOL:
2610 #endif
2611 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2612 case IRMP_JVC_PROTOCOL:
2613 #endif
2614 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2615 case IRMP_NIKON_PROTOCOL:
2616 #endif
2617 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2618 case IRMP_LEGO_PROTOCOL:
2619 #endif
2620 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2621 case IRMP_THOMSON_PROTOCOL:
2622 #endif
2623 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2624 case IRMP_ROOMBA_PROTOCOL:
2625 #endif
2626 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2627 case IRMP_PENTAX_PROTOCOL:
2628 #endif
2629 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2630 case IRMP_ACP24_PROTOCOL:
2631 #endif
2632
2633 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \
2634 IRSND_SUPPORT_LGAIR_PROTOCOL == 1 || IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || IRSND_SUPPORT_TECHNICS_PROTOCOL == 1 || \
2635 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \
2636 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_FAN_PROTOCOL == 1 || IRSND_SUPPORT_SPEAKER_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \
2637 IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || \
2638 IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || IRSND_SUPPORT_ROOMBA_PROTOCOL == 1 || IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1 || \
2639 IRSND_SUPPORT_PENTAX_PROTOCOL == 1 || IRSND_SUPPORT_ACP24_PROTOCOL == 1 || IRSND_SUPPORT_PANASONIC_PROTOCOL == 1 || IRSND_SUPPORT_BOSE_PROTOCOL == 1 || \
2640 IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
2641 {
2642 if (pulse_counter == 0)
2643 {
2644 if (current_bit == 0xFF) // send start bit
2645 {
2646 pulse_len = startbit_pulse_len;
2647 pause_len = startbit_pause_len;
2648 }
2649 else if (current_bit < complete_data_len) // send n'th bit
2650 {
2651 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2652 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)
2653 {
2654 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits
2655 {
2656 pulse_len = SAMSUNG_PULSE_LEN;
2657 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2658 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2659 }
2660 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)
2661 {
2662 pulse_len = SAMSUNG_PULSE_LEN;
2663 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
2664 }
2665 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit
2666 {
2667 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2668
2669 pulse_len = SAMSUNG_PULSE_LEN;
2670 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2671 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2672 }
2673 }
2674 else
2675 #endif
2676
2677 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2678 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)
2679 {
2680 if (current_bit < NEC16_ADDRESS_LEN) // send address bits
2681 {
2682 pulse_len = NEC_PULSE_LEN;
2683 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2684 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2685 }
2686 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)
2687 {
2688 pulse_len = NEC_PULSE_LEN;
2689 pause_len = NEC_START_BIT_PAUSE_LEN - 1;
2690 }
2691 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit
2692 {
2693 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2694
2695 pulse_len = NEC_PULSE_LEN;
2696 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2697 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2698 }
2699 }
2700 else
2701 #endif
2702
2703 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2704 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)
2705 {
2706 if (current_bit == 0) // send 2nd start bit
2707 {
2708 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2709 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2710 }
2711 else if (current_bit == 1) // send 3rd start bit
2712 {
2713 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;
2714 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;
2715 }
2716 else if (current_bit == 2) // send 4th start bit
2717 {
2718 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2719 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2720 }
2721 else if (current_bit == 19) // send trailer bit
2722 {
2723 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2724 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;
2725 }
2726 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit
2727 {
2728 uint8_t cur_bit_value = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? 1 : 0;
2729 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2730
2731 if (cur_bit_value == last_bit_value)
2732 {
2733 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;
2734 }
2735 else
2736 {
2737 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);
2738 last_bit_value = cur_bit_value;
2739 }
2740 }
2741 }
2742 else
2743 #endif
2744 if (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7))))
2745 {
2746 pulse_len = pulse_1_len;
2747 pause_len = pause_1_len;
2748 }
2749 else
2750 {
2751 pulse_len = pulse_0_len;
2752 pause_len = pause_0_len;
2753 }
2754 }
2755 else if (has_stop_bit) // send stop bit
2756 {
2757 pulse_len = pulse_0_len;
2758
2759 if (auto_repetition_counter < n_auto_repetitions)
2760 {
2761 pause_len = pause_0_len;
2762 }
2763 else
2764 {
2765 pause_len = 255; // last frame: pause of 255
2766 }
2767 }
2768 }
2769
2770 if (pulse_counter < pulse_len)
2771 {
2772 if (pulse_counter == 0)
2773 {
2774 irsnd_on ();
2775 }
2776 pulse_counter++;
2777 }
2778 else if (pause_counter < pause_len)
2779 {
2780 if (pause_counter == 0)
2781 {
2782 irsnd_off ();
2783 }
2784 pause_counter++;
2785 }
2786 else
2787 {
2788 current_bit++;
2789
2790 if (current_bit >= complete_data_len + has_stop_bit)
2791 {
2792 current_bit = 0xFF;
2793 auto_repetition_counter++;
2794
2795 if (auto_repetition_counter == n_auto_repetitions)
2796 {
2797 irsnd_busy = FALSE;
2798 auto_repetition_counter = 0;
2799 }
2800 new_frame = TRUE;
2801 }
2802
2803 pulse_counter = 0;
2804 pause_counter = 0;
2805 }
2806 break;
2807 }
2808 #endif
2809
2810 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
2811 case IRMP_RC5_PROTOCOL:
2812 #endif
2813 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
2814 case IRMP_RC6_PROTOCOL:
2815 #endif
2816 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
2817 case IRMP_RC6A_PROTOCOL:
2818 #endif
2819 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2820 case IRMP_SIEMENS_PROTOCOL:
2821 #endif
2822 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2823 case IRMP_RUWIDO_PROTOCOL:
2824 #endif
2825 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2826 case IRMP_GRUNDIG_PROTOCOL:
2827 #endif
2828 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2829 case IRMP_IR60_PROTOCOL:
2830 #endif
2831 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2832 case IRMP_NOKIA_PROTOCOL:
2833 #endif
2834 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2835 case IRMP_A1TVBOX_PROTOCOL:
2836 #endif
2837
2838 #if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \
2839 IRSND_SUPPORT_RC6_PROTOCOL == 1 || \
2840 IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \
2841 IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \
2842 IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \
2843 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \
2844 IRSND_SUPPORT_IR60_PROTOCOL == 1 || \
2845 IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \
2846 IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2847 {
2848 if (pulse_counter == pulse_len && pause_counter == pause_len)
2849 {
2850 current_bit++;
2851
2852 if (current_bit >= complete_data_len)
2853 {
2854 current_bit = 0xFF;
2855
2856 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2857 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2858 {
2859 auto_repetition_counter++;
2860
2861 if (repeat_counter > 0)
2862 { // set 117 msec pause time
2863 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;
2864 }
2865
2866 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame
2867 {
2868 n_auto_repetitions++; // increment number of auto repetitions
2869 repeat_counter++;
2870 }
2871 else if (auto_repetition_counter == n_auto_repetitions)
2872 {
2873 irsnd_busy = FALSE;
2874 auto_repetition_counter = 0;
2875 }
2876 }
2877 else
2878 #endif
2879 {
2880 irsnd_busy = FALSE;
2881 }
2882
2883 new_frame = TRUE;
2884 irsnd_off ();
2885 }
2886
2887 pulse_counter = 0;
2888 pause_counter = 0;
2889 }
2890
2891 if (! new_frame)
2892 {
2893 uint8_t first_pulse;
2894
2895 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2896 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2897 {
2898 if (current_bit == 0xFF || // start bit of start-frame
2899 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)
2900 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)
2901 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)
2902 {
2903 pulse_len = startbit_pulse_len;
2904 pause_len = startbit_pause_len;
2905 first_pulse = TRUE;
2906 }
2907 else // send n'th bit
2908 {
2909 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2910 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2911 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2912 }
2913 }
2914 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||
2915 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)
2916 #endif
2917 {
2918 if (current_bit == 0xFF) // 1 start bit
2919 {
2920 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2921 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2922 {
2923 pulse_len = startbit_pulse_len;
2924 pause_len = startbit_pause_len;
2925 }
2926 else
2927 #endif
2928 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2929 if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)
2930 {
2931 current_bit = 0;
2932 }
2933 else
2934 #endif
2935 {
2936 ;
2937 }
2938
2939 first_pulse = TRUE;
2940 }
2941 else // send n'th bit
2942 {
2943 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2944 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2945 {
2946 pulse_len = RC6_BIT_LEN;
2947 pause_len = RC6_BIT_LEN;
2948
2949 if (irsnd_protocol == IRMP_RC6_PROTOCOL)
2950 {
2951 if (current_bit == 4) // toggle bit (double len)
2952 {
2953 pulse_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2954 pause_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2955 }
2956 }
2957 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)
2958 {
2959 if (current_bit == 4) // toggle bit (double len)
2960 {
2961 pulse_len = RC6_BIT_3_LEN; // = 3 * RC6_BIT_LEN
2962 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2963 }
2964 else if (current_bit == 5) // toggle bit (double len)
2965 {
2966 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2967 }
2968 }
2969 }
2970 #endif
2971 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2972 }
2973
2974 if (irsnd_protocol == IRMP_RC5_PROTOCOL)
2975 {
2976 first_pulse = first_pulse ? FALSE : TRUE;
2977 }
2978 }
2979
2980 if (first_pulse)
2981 {
2982 // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
2983
2984 if (pulse_counter < pulse_len)
2985 {
2986 if (pulse_counter == 0)
2987 {
2988 irsnd_on ();
2989 }
2990 pulse_counter++;
2991 }
2992 else // if (pause_counter < pause_len)
2993 {
2994 if (pause_counter == 0)
2995 {
2996 irsnd_off ();
2997 }
2998 pause_counter++;
2999 }
3000 }
3001 else
3002 {
3003 // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
3004
3005 if (pause_counter < pause_len)
3006 {
3007 if (pause_counter == 0)
3008 {
3009 irsnd_off ();
3010 }
3011 pause_counter++;
3012 }
3013 else // if (pulse_counter < pulse_len)
3014 {
3015 if (pulse_counter == 0)
3016 {
3017 irsnd_on ();
3018 }
3019 pulse_counter++;
3020 }
3021 }
3022 }
3023 break;
3024 }
3025 #endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||
3026 // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
3027
3028 default:
3029 {
3030 irsnd_busy = FALSE;
3031 break;
3032 }
3033 }
3034 }
3035
3036 if (! irsnd_busy)
3037 {
3038 if (repeat_counter < n_repeat_frames)
3039 {
3040 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
3041 if (irsnd_protocol == IRMP_FDC_PROTOCOL)
3042 {
3043 irsnd_buffer[2] |= 0x0F;
3044 }
3045 #endif
3046 repeat_counter++;
3047 irsnd_busy = TRUE;
3048 }
3049 else
3050 {
3051 irsnd_busy = TRUE; //Rainer
3052 send_trailer = TRUE;
3053 n_repeat_frames = 0;
3054 repeat_counter = 0;
3055 }
3056 }
3057 }
3058
3059 #ifdef ANALYZE
3060 if (irsnd_is_on)
3061 {
3062 putchar ('0');
3063 }
3064 else
3065 {
3066 putchar ('1');
3067 }
3068 #endif
3069
3070 return irsnd_busy;
3071 }
3072
3073 #ifdef ANALYZE
3074
3075 // main function - for unix/linux + windows only!
3076 // AVR: see main.c!
3077 // Compile it under linux with:
3078 // cc irsnd.c -o irsnd
3079 //
3080 // usage: ./irsnd protocol hex-address hex-command >filename
3081
3082 int
3083 main (int argc, char ** argv)
3084 {
3085 int protocol;
3086 int address;
3087 int command;
3088 IRMP_DATA irmp_data;
3089
3090 if (argc != 4 && argc != 5)
3091 {
3092 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);
3093 return 1;
3094 }
3095
3096 if (sscanf (argv[1], "%d", &protocol) == 1 &&
3097 sscanf (argv[2], "%x", &address) == 1 &&
3098 sscanf (argv[3], "%x", &command) == 1)
3099 {
3100 irmp_data.protocol = protocol;
3101 irmp_data.address = address;
3102 irmp_data.command = command;
3103
3104 if (argc == 5)
3105 {
3106 irmp_data.flags = atoi (argv[4]);
3107 }
3108 else
3109 {
3110 irmp_data.flags = 0;
3111 }
3112
3113 irsnd_init ();
3114
3115 (void) irsnd_send_data (&irmp_data, TRUE);
3116
3117 while (irsnd_busy)
3118 {
3119 irsnd_ISR ();
3120 }
3121
3122 putchar ('\n');
3123
3124 #if 1 // enable here to send twice
3125 (void) irsnd_send_data (&irmp_data, TRUE);
3126
3127 while (irsnd_busy)
3128 {
3129 irsnd_ISR ();
3130 }
3131
3132 putchar ('\n');
3133 #endif
3134 }
3135 else
3136 {
3137 fprintf (stderr, "%s: wrong arguments\n", argv[0]);
3138 return 1;
3139 }
3140 return 0;
3141 }
3142
3143 #endif // ANALYZE
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)