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libopencm3: Add IRMP_LOGGING
[irmp.git] / irsnd.c
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4225a882 1/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
2 * @file irsnd.c\r
3 *\r
7365350c 4 * Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de\r
4225a882 5 *\r
622f5f59 6 * Supported AVR mikrocontrollers:\r
7644ac04 7 *\r
21a4e0ee 8 * ATtiny87, ATtiny167\r
476267f4 9 * ATtiny45, ATtiny85\r
2ac088b2 10 * ATtiny44 ATtiny84\r
173b00a6 11 * ATtiny2313 ATtiny4313\r
7644ac04 12 * ATmega8, ATmega16, ATmega32\r
13 * ATmega162\r
e664a9f3 14 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P\r
7644ac04 15 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r
16 *\r
30d1689d 17 * $Id: irsnd.c,v 1.103 2017/02/17 09:13:06 fm Exp $\r
5481e9cd 18 *\r
4225a882 19 * This program is free software; you can redistribute it and/or modify\r
20 * it under the terms of the GNU General Public License as published by\r
21 * the Free Software Foundation; either version 2 of the License, or\r
22 * (at your option) any later version.\r
23 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
24 */\r
25\r
4225a882 26#include "irsnd.h"\r
27\r
a03ad359 28#ifndef F_CPU\r
29# error F_CPU unkown\r
30#endif\r
31\r
1f54e86c 32/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
33 * ATtiny pin definition of OC0A / OC0B\r
34 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B\r
35 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
36 */\r
2ac088b2 37#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7\r
08f2dd9d 38# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 39# define IRSND_PORT_LETTER B\r
40# define IRSND_BIT_NUMBER 2\r
08f2dd9d 41# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 42# define IRSND_PORT_LETTER A\r
43# define IRSND_BIT_NUMBER 7\r
08f2dd9d 44# else\r
45# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
46# endif // IRSND_OCx\r
ad4d3d41 47\r
08f2dd9d 48#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1\r
49# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 50# define IRSND_PORT_LETTER B\r
51# define IRSND_BIT_NUMBER 0\r
08f2dd9d 52# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 53# define IRSND_PORT_LETTER B\r
54# define IRSND_BIT_NUMBER 1\r
08f2dd9d 55# else\r
56# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
57# endif // IRSND_OCx\r
ad4d3d41 58\r
173b00a6 59#elif defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny4313__) // ATtiny2313/4313 uses OC0A = PB2 or OC0B = PD5\r
60# if IRSND_OCx == IRSND_OC0A // OC0A\r
61# define IRSND_PORT_LETTER B\r
62# define IRSND_BIT_NUMBER 2\r
63# elif IRSND_OCx == IRSND_OC0B // OC0B\r
64# define IRSND_PORT_LETTER D\r
65# define IRSND_BIT_NUMBER 5\r
66# else\r
67# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
68# endif // IRSND_OCx\r
69\r
21a4e0ee 70#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2\r
90387f65 71# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 72# define IRSND_PORT_LETTER A\r
73# define IRSND_BIT_NUMBER 2\r
90387f65 74# else\r
75# error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h\r
76# endif // IRSND_OCx\r
ad4d3d41 77\r
08f2dd9d 78#elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3\r
173b00a6 79# if IRSND_OCx == IRSND_OC2 // OC2\r
f874da09 80# define IRSND_PORT_LETTER B\r
81# define IRSND_BIT_NUMBER 3\r
08f2dd9d 82# else\r
83# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
84# endif // IRSND_OCx\r
173b00a6 85#elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC0 = PB3 or OC2 = PD7\r
08f2dd9d 86# if IRSND_OCx == IRSND_OC2 // OC2\r
f874da09 87# define IRSND_PORT_LETTER D\r
88# define IRSND_BIT_NUMBER 7\r
173b00a6 89# elif IRSND_OCx == IRSND_OC0 // OC0\r
90# define IRSND_PORT_LETTER B\r
91# define IRSND_BIT_NUMBER 3\r
08f2dd9d 92# else\r
173b00a6 93# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r
08f2dd9d 94# endif // IRSND_OCx\r
ad4d3d41 95\r
08f2dd9d 96#elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0\r
97# if IRSND_OCx == IRSND_OC2 // OC2\r
f874da09 98# define IRSND_PORT_LETTER B\r
99# define IRSND_BIT_NUMBER 1\r
08f2dd9d 100# elif IRSND_OCx == IRSND_OC0 // OC0\r
f874da09 101# define IRSND_PORT_LETTER B\r
102# define IRSND_BIT_NUMBER 0\r
08f2dd9d 103# else\r
104# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r
105# endif // IRSND_OCx\r
ad4d3d41 106\r
f50e01e7 107#elif defined (__AVR_ATmega164__) \\r
108 || defined (__AVR_ATmega324__) \\r
109 || defined (__AVR_ATmega644__) \\r
110 || defined (__AVR_ATmega644P__) \\r
0f700c8e 111 || defined (__AVR_ATmega1284__) \\r
08f2dd9d 112 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4\r
113# if IRSND_OCx == IRSND_OC2A // OC2A\r
f874da09 114# define IRSND_PORT_LETTER D\r
115# define IRSND_BIT_NUMBER 7\r
08f2dd9d 116# elif IRSND_OCx == IRSND_OC2B // OC2B\r
f874da09 117# define IRSND_PORT_LETTER D\r
118# define IRSND_BIT_NUMBER 6\r
08f2dd9d 119# elif IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 120# define IRSND_PORT_LETTER B\r
121# define IRSND_BIT_NUMBER 3\r
08f2dd9d 122# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 123# define IRSND_PORT_LETTER B\r
124# define IRSND_BIT_NUMBER 4\r
08f2dd9d 125# else\r
126# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
127# endif // IRSND_OCx\r
ad4d3d41 128\r
f50e01e7 129#elif defined (__AVR_ATmega48__) \\r
130 || defined (__AVR_ATmega88__) \\r
7644ac04 131 || defined (__AVR_ATmega88P__) \\r
f50e01e7 132 || defined (__AVR_ATmega168__) \\r
1f54e86c 133 || defined (__AVR_ATmega168P__) \\r
08f2dd9d 134 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5\r
135# if IRSND_OCx == IRSND_OC2A // OC2A\r
f874da09 136# define IRSND_PORT_LETTER B\r
137# define IRSND_BIT_NUMBER 3\r
08f2dd9d 138# elif IRSND_OCx == IRSND_OC2B // OC2B\r
f874da09 139# define IRSND_PORT_LETTER D\r
140# define IRSND_BIT_NUMBER 3\r
08f2dd9d 141# elif IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 142# define IRSND_PORT_LETTER D\r
143# define IRSND_BIT_NUMBER 6\r
08f2dd9d 144# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 145# define IRSND_PORT_LETTER D\r
146# define IRSND_BIT_NUMBER 5\r
08f2dd9d 147# else\r
148# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
149# endif // IRSND_OCx\r
ad4d3d41 150\r
f874da09 151#elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2\r
30d1689d 152# if IRSND_OCx == IRSND_OC0\r
f874da09 153# define IRSND_PORT_LETTER B\r
154# define IRSND_BIT_NUMBER 0\r
30d1689d 155# elif IRSND_OCx == IRSND_OC1A\r
f874da09 156# define IRSND_PORT_LETTER D\r
157# define IRSND_BIT_NUMBER 5\r
30d1689d 158# elif IRSND_OCx == IRSND_OC1B\r
f874da09 159# define IRSND_PORT_LETTER E\r
160# define IRSND_BIT_NUMBER 2\r
ad4d3d41 161# endif // IRSND_OCx\r
162\r
c2b70f0b 163#elif defined (__AVR_XMEGA__) // ATxmega\r
30d1689d 164# if IRSND_OCx == IRSND_XMEGA_OC0A\r
ad4d3d41 165# define IRSND_BIT_NUMBER 0\r
166# elif IRSND_OCx == IRSND_XMEGA_OC0B\r
167# define IRSND_BIT_NUMBER 1\r
168# elif IRSND_OCx == IRSND_XMEGA_OC0C\r
169# define IRSND_BIT_NUMBER 2\r
170# elif IRSND_OCx == IRSND_XMEGA_OC0D\r
171# define IRSND_BIT_NUMBER 3\r
172# elif IRSND_OCx == IRSND_XMEGA_OC1A\r
173# define IRSND_BIT_NUMBER 4\r
174# elif IRSND_OCx == IRSND_XMEGA_OC1B\r
175# define IRSND_BIT_NUMBER 5\r
08f2dd9d 176# else\r
c2b70f0b 177# error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h\r
08f2dd9d 178# endif // IRSND_OCx\r
ad4d3d41 179\r
30d1689d 180#elif defined (PIC_C18) // Microchip C18 compiler\r
9c86ff1a 181 //Nothing here to do here -> See irsndconfig.h\r
30d1689d 182#elif defined (ARM_STM32) // STM32\r
08f2dd9d 183 //Nothing here to do here -> See irsndconfig.h\r
54cbcce6
L		 184#elif defined(LIBOPENCM3)\r
185 //Nothing here to do here -> See irsndconfig.h\r
30d1689d 186#elif defined (__xtensa__) // ESP8266\r
187 //Nothing here to do here -> See irsndconfig.h\r
188\r
7365350c 189/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
190 * Macro digitalPinHasPWM bothers PIC_C18 compiler, but why?\r
191 *\r
192 * #elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3\r
193 * # if !digitalPinHasPWM(IRSND_PIN)\r
194 * # error need pin with PWM output.\r
195 * # endif\r
196 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
197 */\r
f50e01e7 198#else\r
08f2dd9d 199# if !defined (unix) && !defined (WIN32)\r
200# error mikrocontroller not defined, please fill in definitions here.\r
201# endif // unix, WIN32\r
f50e01e7 202#endif // __AVR...\r
203\r
ad4d3d41 204#if defined(__AVR_XMEGA__)\r
205# define _CONCAT(a,b) a##b\r
206# define CONCAT(a,b) _CONCAT(a,b)\r
207# define IRSND_PORT IRSND_PORT_PRE.OUT\r
22a5040e 208# define IRSND_DDR IRSND_PORT_PRE.DIR\r
209# define IRSND_PIN IRSND_PORT_PRE.IN\r
ad4d3d41 210# define IRSND_BIT IRSND_BIT_NUMBER\r
ad4d3d41 211#elif defined(ATMEL_AVR)\r
f874da09 212# define _CONCAT(a,b) a##b\r
213# define CONCAT(a,b) _CONCAT(a,b)\r
214# define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)\r
215# define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)\r
216# define IRSND_BIT IRSND_BIT_NUMBER\r
217#endif\r
218\r
9405f84a 219#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
9c86ff1a 220 typedef uint16_t IRSND_PAUSE_LEN;\r
9405f84a 221#else\r
9c86ff1a 222 typedef uint8_t IRSND_PAUSE_LEN;\r
9405f84a 223#endif\r
224\r
f50e01e7 225/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
226 * IR timings\r
227 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
228 */\r
4225a882 229#define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)\r
230#define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)\r
231#define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)\r
232#define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)\r
233#define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)\r
9c07687e 234#define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
235#define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 236\r
237#define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)\r
238#define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)\r
a7054daf 239#define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
4225a882 240#define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)\r
241#define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)\r
242#define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)\r
9c07687e 243#define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 244\r
245#define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)\r
246#define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)\r
247#define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)\r
248#define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)\r
249#define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)\r
9c07687e 250#define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 251\r
9c07687e 252#define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
253#define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 254\r
ac8504f8 255#define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
256#define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
257\r
4225a882 258#define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)\r
259#define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)\r
260#define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)\r
261#define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)\r
262#define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)\r
9c07687e 263#define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 264\r
770a1a9d 265#define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)\r
266#define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)\r
267#define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)\r
268#define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)\r
269#define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)\r
9c07687e 270#define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
271#define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
770a1a9d 272\r
7365350c 273#define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)\r
274#define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)\r
275#define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)\r
276#define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)\r
277#define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)\r
278#define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
279#define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
280\r
281#define MITSU_HEAVY_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PULSE_TIME + 0.5)\r
282#define MITSU_HEAVY_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PAUSE_TIME + 0.5)\r
283#define MITSU_HEAVY_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_PULSE_TIME + 0.5)\r
284#define MITSU_HEAVY_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_1_PAUSE_TIME + 0.5)\r
285#define MITSU_HEAVY_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_0_PAUSE_TIME + 0.5)\r
286#define MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MITSU_HEAVY_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
95b27043 287\r
4225a882 288#define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)\r
289#define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)\r
290#define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)\r
291#define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)\r
292#define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)\r
9c07687e 293#define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 294\r
295#define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
296#define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
9c07687e 297#define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 298\r
299#define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)\r
300#define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)\r
4225a882 301#define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)\r
95b27043 302#define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)\r
303#define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)\r
9c07687e 304#define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 305\r
306#define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)\r
307#define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)\r
308#define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)\r
9c07687e 309#define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
310#define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 311\r
beda975f 312#define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)\r
313#define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)\r
314#define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)\r
9c07687e 315#define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
316#define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
beda975f 317\r
4225a882 318#define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)\r
319#define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)\r
320#define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)\r
321#define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)\r
322#define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)\r
9c07687e 323#define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
324\r
325#define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)\r
326#define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)\r
327#define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)\r
328#define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)\r
329#define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)\r
330#define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
331#define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 332\r
95b27043 333#define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)\r
334#define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)\r
335#define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)\r
336#define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)\r
337#define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)\r
338#define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
339#define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
340\r
4225a882 341#define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)\r
342#define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)\r
343#define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)\r
344#define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)\r
345#define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)\r
346#define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)\r
9c07687e 347#define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
348#define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 349\r
0715cf5e 350#define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)\r
351#define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)\r
352#define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)\r
353#define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)\r
354#define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)\r
355#define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)\r
356#define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
357#define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
358\r
15dd9c32 359#define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)\r
360#define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)\r
361#define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)\r
362#define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)\r
363#define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)\r
364#define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)\r
9c07687e 365#define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
366#define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
15dd9c32 367\r
5481e9cd 368#define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)\r
369#define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)\r
370#define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)\r
371#define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)\r
372#define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)\r
373#define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)\r
374#define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)\r
375#define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)\r
376#define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)\r
377#define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)\r
378#define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)\r
9c07687e 379#define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5481e9cd 380\r
9c86ff1a 381#define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)\r
382#define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)\r
9c07687e 383#define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
384#define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
89e8cafb 385#define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
a7054daf 386\r
9c07687e 387#define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
a48187fa 388\r
02ccdb69 389#define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
390#define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
9c07687e 391#define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 392\r
cb93f9e9 393#define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
394#define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)\r
395#define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
396#define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)\r
9c07687e 397#define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
cb93f9e9 398\r
08f2dd9d 399#ifdef PIC_C18 // PIC C18\r
400# define IRSND_FREQ_TYPE uint8_t\r
401# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
402# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
403# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
404# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
405# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
406# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
407# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
408#elif defined (ARM_STM32) // STM32\r
409# define IRSND_FREQ_TYPE uint32_t\r
410# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
411# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
412# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
413# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
414# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
415# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
416# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
54cbcce6
L		 417#elif defined(LIBOPENCM3)\r
418# define IRSND_FREQ_TYPE uint32_t\r
419# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
420# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
421# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
422# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
423# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
424# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
425# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
df24bb50 426#elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
95b27043 427# define IRSND_FREQ_TYPE float\r
428# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
429# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
430# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
431# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
432# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
433# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
434# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
30d1689d 435#elif defined (__xtensa__) // ESP8266\r
436# define IRSND_FREQ_TYPE float\r
437# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
438# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
439# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
440# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
441# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
442# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
443# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
08f2dd9d 444#else // AVR\r
a03ad359 445# if F_CPU >= 16000000L\r
446# define AVR_PRESCALER 8\r
447# else\r
448# define AVR_PRESCALER 1\r
449# endif\r
08f2dd9d 450# define IRSND_FREQ_TYPE uint8_t\r
a03ad359 451# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)\r
452# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)\r
453# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)\r
454# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)\r
455# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)\r
456# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)\r
457# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)\r
9c86ff1a 458#endif\r
4225a882 459\r
48664931 460#define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)\r
461#define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)\r
462#define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)\r
463#define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)\r
464#define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)\r
465#define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
b5ea7869 466\r
c7c9a4a1 467#define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)\r
468#define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)\r
469#define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)\r
470#define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)\r
471#define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)\r
472#define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
473\r
c7a47e89 474#define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)\r
475#define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)\r
476#define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
477#define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)\r
478#define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)\r
479#define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)\r
480#define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
481\r
9405f84a 482#define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)\r
483#define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)\r
484#define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
485#define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)\r
486#define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)\r
487#define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)\r
f50e01e7 488#define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
489\r
490#define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)\r
491#define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)\r
492#define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
493#define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)\r
494#define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)\r
495#define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)\r
496#define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
9405f84a 497\r
fa09ce10 498#define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)\r
499#define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)\r
500#define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)\r
501#define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)\r
502#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
503#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
504\r
c9b6916a 505#define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)\r
506#define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)\r
507#define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)\r
508#define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)\r
509#define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)\r
510#define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)\r
511#define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
512\r
003c1008 513#define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)\r
514#define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)\r
515#define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
516#define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)\r
517#define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)\r
518#define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)\r
519#define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
520\r
43c535be 521#define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)\r
522#define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)\r
523#define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
524#define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)\r
525#define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)\r
526#define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)\r
527#define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
528\r
9c86ff1a 529static volatile uint8_t irsnd_busy = 0;\r
530static volatile uint8_t irsnd_protocol = 0;\r
7365350c 531static volatile uint8_t irsnd_buffer[11] = {0};\r
9c86ff1a 532static volatile uint8_t irsnd_repeat = 0;\r
4225a882 533static volatile uint8_t irsnd_is_on = FALSE;\r
534\r
f50e01e7 535#if IRSND_USE_CALLBACK == 1\r
536static void (*irsnd_callback_ptr) (uint8_t);\r
537#endif // IRSND_USE_CALLBACK == 1\r
538\r
4225a882 539/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
540 * Switch PWM on\r
4225a882 541 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
542 */\r
543static void\r
544irsnd_on (void)\r
545{\r
546 if (! irsnd_is_on)\r
547 {\r
cb93f9e9 548#ifndef ANALYZE\r
08f2dd9d 549# if defined(PIC_C18) // PIC C18\r
df24bb50 550 PWMon();\r
551 // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
ad4d3d41 552\r
08f2dd9d 553# elif defined (ARM_STM32) // STM32\r
df24bb50 554 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
555 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
556 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r
95b27043 557\r
54cbcce6
L		 558# elif defined (LIBOPENCM3) // STM32 whit libopencm3\r
559 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_PWM1);\r
54cbcce6 560\r
df24bb50 561# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
562 analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%\r
ad4d3d41 563\r
30d1689d 564# elif defined (__xtensa__) // ESP8266 (Arduino)\r
565 analogWrite(IRSND_PIN, 33 * 1023 / 100); // pwm 33%\r
566\r
567# elif defined (__AVR_XMEGA__)\r
ea585783 568# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A\r
30d1689d 569 XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A\r
ea585783 570# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B\r
30d1689d 571 XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B\r
ea585783 572# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C\r
df24bb50 573 XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C\r
ea585783 574# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D\r
df24bb50 575 XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D\r
ea585783 576# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A\r
df24bb50 577 XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A\r
ea585783 578# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B\r
df24bb50 579 XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B\r
ad4d3d41 580# else\r
581# error wrong value of IRSND_OCx\r
582# endif // IRSND_OCx\r
583\r
08f2dd9d 584# else // AVR\r
585# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 586 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r
08f2dd9d 587# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 588 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r
08f2dd9d 589# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 590 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)\r
08f2dd9d 591# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 592 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0\r
08f2dd9d 593# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 594 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A\r
08f2dd9d 595# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 596 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)\r
08f2dd9d 597# else\r
598# error wrong value of IRSND_OCx\r
599# endif // IRSND_OCx\r
600# endif // C18\r
cb93f9e9 601#endif // ANALYZE\r
f50e01e7 602\r
603#if IRSND_USE_CALLBACK == 1\r
df24bb50 604 if (irsnd_callback_ptr)\r
605 {\r
606 (*irsnd_callback_ptr) (TRUE);\r
607 }\r
f50e01e7 608#endif // IRSND_USE_CALLBACK == 1\r
609\r
df24bb50 610 irsnd_is_on = TRUE;\r
4225a882 611 }\r
612}\r
613\r
614/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
615 * Switch PWM off\r
616 * @details Switches PWM off\r
617 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
618 */\r
619static void\r
620irsnd_off (void)\r
621{\r
622 if (irsnd_is_on)\r
623 {\r
cb93f9e9 624#ifndef ANALYZE\r
30d1689d 625\r
626# if defined(PIC_C18) // PIC C18\r
df24bb50 627 PWMoff();\r
628 // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
ad4d3d41 629\r
30d1689d 630# elif defined (ARM_STM32) // STM32\r
631 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r
632 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r
633 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
634 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r
95b27043 635\r
54cbcce6 636# elif defined (LIBOPENCM3) // STM32\r
e97defc0 637 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);\r
54cbcce6 638\r
30d1689d 639# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
640 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
641\r
642# elif defined (__xtensa__) // ESP8266\r
643 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
ad4d3d41 644\r
645# elif defined (__AVR_XMEGA__)\r
30d1689d 646# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A\r
df24bb50 647 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected\r
30d1689d 648# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B\r
df24bb50 649 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected\r
ad4d3d41 650# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C\r
df24bb50 651 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected\r
ad4d3d41 652# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D\r
df24bb50 653 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected\r
22a5040e 654# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A\r
30d1689d 655 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected\r
22a5040e 656# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B\r
30d1689d 657 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected\r
ad4d3d41 658# else\r
659# error wrong value of IRSND_OCx\r
660# endif // IRSND_OCx\r
661\r
08f2dd9d 662# else //AVR\r
9c86ff1a 663\r
08f2dd9d 664# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 665 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.\r
08f2dd9d 666# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 667 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.\r
08f2dd9d 668# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 669 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.\r
08f2dd9d 670# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 671 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.\r
08f2dd9d 672# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 673 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.\r
08f2dd9d 674# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 675 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.\r
08f2dd9d 676# else\r
677# error wrong value of IRSND_OCx\r
678# endif // IRSND_OCx\r
df24bb50 679 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
08f2dd9d 680# endif //C18\r
cb93f9e9 681#endif // ANALYZE\r
f50e01e7 682\r
683#if IRSND_USE_CALLBACK == 1\r
df24bb50 684 if (irsnd_callback_ptr)\r
685 {\r
686 (*irsnd_callback_ptr) (FALSE);\r
687 }\r
f50e01e7 688#endif // IRSND_USE_CALLBACK == 1\r
689\r
df24bb50 690 irsnd_is_on = FALSE;\r
4225a882 691 }\r
692}\r
693\r
694/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
695 * Set PWM frequency\r
696 * @details sets pwm frequency\r
697 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
698 */\r
7fe8188d 699#if defined(__12F1840)\r
700extern void pwm_init(uint16_t freq);\r
701#include <stdio.h>\r
702#endif\r
703\r
4225a882 704static void\r
08f2dd9d 705irsnd_set_freq (IRSND_FREQ_TYPE freq)\r
4225a882 706{\r
cb93f9e9 707#ifndef ANALYZE\r
7fe8188d 708# if defined(PIC_C18) // PIC C18 or XC8\r
709# if defined(__12F1840) // XC8\r
30d1689d 710 TRISA2=0;\r
df24bb50 711 PR2=freq;\r
712 CCP1M0=1;\r
713 CCP1M1=1;\r
714 CCP1M2=1;\r
715 CCP1M3=1;\r
716 DC1B0=1;\r
717 DC1B1=0;\r
718 CCPR1L = 0b01101001;\r
719 TMR2IF = 0;\r
720 TMR2ON=1;\r
721 CCP1CON &=(~0b0011); // p 197 "active high"\r
7fe8188d 722# else // PIC C18\r
30d1689d 723 OpenPWM(freq);\r
df24bb50 724 SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%\r
7fe8188d 725# endif\r
df24bb50 726 PWMoff();\r
08f2dd9d 727# elif defined (ARM_STM32) // STM32\r
df24bb50 728 static uint32_t TimeBaseFreq = 0;\r
08f2dd9d 729\r
df24bb50 730 if (TimeBaseFreq == 0)\r
731 {\r
732 RCC_ClocksTypeDef RCC_ClocksStructure;\r
733 /* Get system clocks and store timer clock in variable */\r
734 RCC_GetClocksFreq(&RCC_ClocksStructure);\r
08f2dd9d 735# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
df24bb50 736 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
737 {\r
738 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r
739 }\r
740 else\r
741 {\r
742 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;\r
743 }\r
08f2dd9d 744# else\r
df24bb50 745 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
746 {\r
747 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r
748 }\r
749 else\r
750 {\r
751 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;\r
752 }\r
08f2dd9d 753# endif\r
df24bb50 754 }\r
95b27043 755\r
df24bb50 756 freq = TimeBaseFreq/freq;\r
08f2dd9d 757\r
df24bb50 758 /* Set frequency */\r
759 TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
760 /* Set duty cycle */\r
761 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
08f2dd9d 762\r
54cbcce6
L		 763# elif defined(LIBOPENCM3)\r
764 static uint32_t TimeBaseFreq = 0;\r
765\r
766 if (TimeBaseFreq == 0)\r
767 {\r
768# if defined(STM32F0) || (IRSND_TIMER < PERIPH_BASE_APB2)\r
769 TimeBaseFreq = rcc_apb1_frequency;\r
770# else\r
771 TimeBaseFreq = rcc_apb2_frequency;\r
772# endif\r
773 /* Timer clock is doubled, if the APB prescaler is greater than 1 */\r
774 if (TimeBaseFreq != rcc_ahb_frequency)\r
775 TimeBaseFreq *= 2;\r
776 }\r
777 freq = TimeBaseFreq/freq;\r
778\r
779 /* Set frequency */\r
780 timer_set_period(IRSND_TIMER, freq - 1);\r
e97defc0
L		 781 /* Set duty cycle to 33% */\r
782 timer_set_oc_value(IRSND_TIMER, IRSND_TIMER_CHANNEL, (freq + 2) / 3);\r
783 timer_set_counter(IRSND_TIMER, 0);\r
784 timer_enable_counter(IRSND_TIMER);\r
54cbcce6 785\r
95b27043 786# elif defined (TEENSY_ARM_CORTEX_M4)\r
30d1689d 787 analogWriteResolution(8); // 8 bit\r
95b27043 788 analogWriteFrequency(IRSND_PIN, freq);\r
30d1689d 789 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
790\r
791#elif defined (__xtensa__)\r
792 // analogWriteRange(255);\r
793 analogWriteFreq(freq);\r
794 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
ad4d3d41 795\r
796# elif defined (__AVR_XMEGA__)\r
df24bb50 797 XMEGA_Timer.CCA = freq;\r
ad4d3d41 798\r
08f2dd9d 799# else // AVR\r
800\r
801# if IRSND_OCx == IRSND_OC2\r
df24bb50 802 OCR2 = freq; // use register OCR2 for OC2\r
08f2dd9d 803# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 804 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
08f2dd9d 805# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 806 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
08f2dd9d 807# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 808 OCR0 = freq; // use register OCR2 for OC2\r
08f2dd9d 809# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 810 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
08f2dd9d 811# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 812 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
08f2dd9d 813# else\r
814# error wrong value of IRSND_OCx\r
815# endif\r
816# endif //PIC_C18\r
cb93f9e9 817#endif // ANALYZE\r
4225a882 818}\r
819\r
820/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
821 * Initialize the PWM\r
822 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels\r
823 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
824 */\r
825void\r
826irsnd_init (void)\r
827{\r
cb93f9e9 828#ifndef ANALYZE\r
7fe8188d 829# if defined(PIC_C18) // PIC C18 or XC8 compiler\r
830# if ! defined(__12F1840) // only C18:\r
df24bb50 831 OpenTimer;\r
7fe8188d 832# endif\r
df24bb50 833 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
834 IRSND_PIN = 0; // set IO to outout\r
835 PWMoff();\r
08f2dd9d 836# elif defined (ARM_STM32) // STM32\r
df24bb50 837 GPIO_InitTypeDef GPIO_InitStructure;\r
838 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
839 TIM_OCInitTypeDef TIM_OCInitStructure;\r
08f2dd9d 840\r
841 /* GPIOx clock enable */\r
842# if defined (ARM_STM32L1XX)\r
df24bb50 843 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
08f2dd9d 844# elif defined (ARM_STM32F10X)\r
df24bb50 845 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
846 // RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping\r
08f2dd9d 847# elif defined (ARM_STM32F4XX)\r
df24bb50 848 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
08f2dd9d 849# endif\r
850\r
df24bb50 851 /* GPIO Configuration */\r
852 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;\r
08f2dd9d 853# if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)\r
df24bb50 854 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
855 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
856 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
857 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
858 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
859 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);\r
08f2dd9d 860# elif defined (ARM_STM32F10X)\r
df24bb50 861 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
862 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
863 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
864 // GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping\r
08f2dd9d 865# endif\r
866\r
df24bb50 867 /* TIMx clock enable */\r
08f2dd9d 868# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
df24bb50 869 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
08f2dd9d 870# else\r
df24bb50 871 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
08f2dd9d 872# endif\r
08f2dd9d 873\r
df24bb50 874 /* Time base configuration */\r
875 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r
876 TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
877 TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
878 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
879 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r
95b27043 880\r
df24bb50 881 /* PWM1 Mode configuration */\r
882 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
883 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
884 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
885 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
886 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
95b27043 887\r
df24bb50 888 /* Preload configuration */\r
889 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
890 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
95b27043 891\r
df24bb50 892 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r
95b27043 893\r
54cbcce6
L		 894# elif defined (LIBOPENCM3)\r
895 /* GPIOx clock enable */\r
896 rcc_periph_clock_enable(IRSND_PORT_RCC);\r
54cbcce6
L		 897 /* TIMx clock enable */\r
898 rcc_periph_clock_enable(IRSND_TIMER_RCC);\r
899\r
900 /* Time base configuration */\r
e97defc0 901 /* Stop timer and set it to its default mode (edge-aligned upcounting) */\r
54cbcce6 902 timer_reset(IRSND_TIMER);\r
54cbcce6 903\r
e97defc0
L		 904 /* PWM Mode configuration */\r
905 timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);\r
54cbcce6 906 timer_enable_oc_output(IRSND_TIMER, IRSND_TIMER_CHANNEL);\r
54cbcce6 907 timer_enable_break_main_output(IRSND_TIMER);\r
e97defc0
L		 908 /* Output polarity and GPIO Configuration */\r
909# if 1\r
910 /* (active) high is the default output polarity */\r
911 gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,\r
912 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, IRSND_BIT);\r
54cbcce6
L		 913# else\r
914 timer_set_oc_polarity_low(IRSND_TIMER, IRSND_TIMER_CHANNEL);\r
e97defc0
L		 915 gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,\r
916 GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, IRSND_BIT);\r
54cbcce6
L		 917# endif\r
918\r
95b27043 919# elif defined (TEENSY_ARM_CORTEX_M4)\r
920 if (!digitalPinHasPWM(IRSND_PIN))\r
df24bb50 921 {\r
922 return;\r
95b27043 923 }\r
22a5040e 924\r
30d1689d 925# elif defined (__xtensa__)\r
926 pinMode(IRSND_PIN, OUTPUT);\r
927 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
928\r
95b27043 929# elif defined (__AVR_XMEGA__)\r
df24bb50 930 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
931 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
22a5040e 932\r
df24bb50 933 XMEGA_Timer.PER = 0xFFFF; //Topwert\r
934 XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC\r
22a5040e 935\r
936# if AVR_PRESCALER == 8\r
df24bb50 937 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8\r
22a5040e 938# else\r
df24bb50 939 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1\r
22a5040e 940# endif\r
30d1689d 941\r
22a5040e 942# else // AVR\r
df24bb50 943 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
944 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
08f2dd9d 945\r
946# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 947 TCCR2 = (1<<WGM21); // CTC mode\r
a03ad359 948# if AVR_PRESCALER == 8\r
df24bb50 949 TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8\r
a03ad359 950# else\r
df24bb50 951 TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1\r
a03ad359 952# endif\r
08f2dd9d 953# elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B\r
df24bb50 954 TCCR2A = (1<<WGM21); // CTC mode\r
a03ad359 955# if AVR_PRESCALER == 8\r
df24bb50 956 TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8\r
a03ad359 957# else\r
df24bb50 958 TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1\r
a03ad359 959# endif\r
08f2dd9d 960# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 961 TCCR0 = (1<<WGM01); // CTC mode\r
a03ad359 962# if AVR_PRESCALER == 8\r
df24bb50 963 TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8\r
a03ad359 964# else\r
df24bb50 965 TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1\r
a03ad359 966# endif\r
08f2dd9d 967# elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B\r
df24bb50 968 TCCR0A = (1<<WGM01); // CTC mode\r
a03ad359 969# if AVR_PRESCALER == 8\r
df24bb50 970 TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8\r
a03ad359 971# else\r
df24bb50 972 TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1\r
a03ad359 973# endif\r
08f2dd9d 974# else\r
975# error wrong value of IRSND_OCx\r
976# endif\r
df24bb50 977 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
08f2dd9d 978# endif //PIC_C18\r
cb93f9e9 979#endif // ANALYZE\r
4225a882 980}\r
981\r
f50e01e7 982#if IRSND_USE_CALLBACK == 1\r
983void\r
984irsnd_set_callback_ptr (void (*cb)(uint8_t))\r
985{\r
986 irsnd_callback_ptr = cb;\r
987}\r
988#endif // IRSND_USE_CALLBACK == 1\r
989\r
4225a882 990uint8_t\r
991irsnd_is_busy (void)\r
992{\r
993 return irsnd_busy;\r
994}\r
995\r
996static uint16_t\r
997bitsrevervse (uint16_t x, uint8_t len)\r
998{\r
999 uint16_t xx = 0;\r
1000\r
1001 while(len)\r
1002 {\r
df24bb50 1003 xx <<= 1;\r
1004 if (x & 1)\r
1005 {\r
1006 xx |= 1;\r
1007 }\r
1008 x >>= 1;\r
1009 len--;\r
4225a882 1010 }\r
1011 return xx;\r
1012}\r
1013\r
1014\r
9547ee89 1015#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
1016static uint8_t sircs_additional_bitlen;\r
1017#endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
1018\r
4225a882 1019uint8_t\r
879b06c2 1020irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)\r
4225a882 1021{\r
1022#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
1023 static uint8_t toggle_bit_recs80;\r
1024#endif\r
1025#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
1026 static uint8_t toggle_bit_recs80ext;\r
1027#endif\r
1028#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
1029 static uint8_t toggle_bit_rc5;\r
9547ee89 1030#endif\r
779fbc81 1031#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
9547ee89 1032 static uint8_t toggle_bit_rc6;\r
beda975f 1033#endif\r
1034#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
1035 static uint8_t toggle_bit_thomson;\r
4225a882 1036#endif\r
1037 uint16_t address;\r
1038 uint16_t command;\r
1039\r
879b06c2 1040 if (do_wait)\r
4225a882 1041 {\r
df24bb50 1042 while (irsnd_busy)\r
1043 {\r
1044 // do nothing;\r
1045 }\r
879b06c2 1046 }\r
1047 else if (irsnd_busy)\r
1048 {\r
df24bb50 1049 return (FALSE);\r
4225a882 1050 }\r
1051\r
1052 irsnd_protocol = irmp_data_p->protocol;\r
beda975f 1053 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;\r
4225a882 1054\r
1055 switch (irsnd_protocol)\r
1056 {\r
1057#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 1058 case IRMP_SIRCS_PROTOCOL:\r
1059 {\r
1060 // uint8_t sircs_additional_command_len;\r
1061 uint8_t sircs_additional_address_len;\r
1062\r
1063 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen\r
1064\r
1065 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)\r
1066 {\r
1067 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;\r
1068 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);\r
1069 }\r
1070 else\r
1071 {\r
1072 // sircs_additional_command_len = sircs_additional_bitlen;\r
1073 sircs_additional_address_len = 0;\r
1074 }\r
1075\r
1076 command = bitsrevervse (irmp_data_p->command, 15);\r
1077\r
1078 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC\r
1079 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****\r
1080\r
1081 if (sircs_additional_address_len > 0)\r
1082 {\r
1083 address = bitsrevervse (irmp_data_p->address, 5);\r
1084 irsnd_buffer[1] |= (address & 0x0010) >> 4;\r
1085 irsnd_buffer[2] = (address & 0x000F) << 4;\r
1086 }\r
1087 irsnd_busy = TRUE;\r
1088 break;\r
1089 }\r
4225a882 1090#endif\r
1091#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 1092 case IRMP_APPLE_PROTOCOL:\r
1093 {\r
1094 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command\r
1095 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)\r
1096\r
1097 address = bitsrevervse (address, NEC_ADDRESS_LEN);\r
1098 command = bitsrevervse (command, NEC_COMMAND_LEN);\r
1099\r
1100 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command\r
1101\r
1102 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1103 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1104 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1105 irsnd_buffer[3] = 0x8B; // 10001011 (id)\r
1106 irsnd_busy = TRUE;\r
1107 break;\r
1108 }\r
1109 case IRMP_NEC_PROTOCOL:\r
1110 {\r
1111 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);\r
1112 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);\r
1113\r
1114 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1115 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1116 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1117 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
1118 irsnd_busy = TRUE;\r
1119 break;\r
1120 }\r
7644ac04 1121#endif\r
1122#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 1123 case IRMP_NEC16_PROTOCOL:\r
1124 {\r
1125 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);\r
1126 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);\r
1127\r
1128 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA\r
1129 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
1130 irsnd_busy = TRUE;\r
1131 break;\r
1132 }\r
7644ac04 1133#endif\r
1134#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 1135 case IRMP_NEC42_PROTOCOL:\r
1136 {\r
1137 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);\r
1138 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);\r
1139\r
1140 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA\r
1141 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa\r
1142 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa\r
1143 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC\r
1144 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc\r
1145 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc\r
1146 irsnd_busy = TRUE;\r
1147 break;\r
1148 }\r
4225a882 1149#endif\r
c1dfa01f 1150#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 1151 case IRMP_LGAIR_PROTOCOL:\r
1152 {\r
1153 address = irmp_data_p->address;\r
1154 command = irmp_data_p->command;\r
1155\r
1156 irsnd_buffer[0] = ( (address & 0x00FF)); // AAAAAAAA\r
1157 irsnd_buffer[1] = ( (command & 0xFF00) >> 8); // CCCCCCCC\r
1158 irsnd_buffer[2] = ( (command & 0x00FF)); // CCCCCCCC\r
1159 irsnd_buffer[3] = (( ((command & 0xF000) >> 12) + // checksum\r
1160 ((command & 0x0F00) >> 8) +\r
1161 ((command & 0x00F0) >>4 ) +\r
1162 ((command & 0x000F))) & 0x000F) << 4;\r
1163 irsnd_busy = TRUE;\r
1164 break;\r
1165 }\r
c1dfa01f 1166#endif\r
4225a882 1167#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 1168 case IRMP_SAMSUNG_PROTOCOL:\r
1169 {\r
1170 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1171 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);\r
1172\r
1173 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1174 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1175 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC\r
1176 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc\r
1177 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000\r
1178 irsnd_busy = TRUE;\r
1179 break;\r
1180 }\r
1181 case IRMP_SAMSUNG32_PROTOCOL:\r
1182 {\r
1183 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1184 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);\r
1185\r
1186 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1187 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1188 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1189 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC\r
1190 irsnd_busy = TRUE;\r
1191 break;\r
1192 }\r
4225a882 1193#endif\r
ac8504f8 1194#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 1195 case IRMP_SAMSUNG48_PROTOCOL:\r
1196 {\r
1197 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1198 command = bitsrevervse (irmp_data_p->command, 16);\r
1199\r
1200 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1201 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1202 irsnd_buffer[2] = ((command & 0xFF00) >> 8); // CCCCCCCC\r
1203 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
1204 irsnd_buffer[4] = (command & 0x00FF); // CCCCCCCC\r
1205 irsnd_buffer[5] = ~(command & 0x00FF); // cccccccc\r
1206 irsnd_busy = TRUE;\r
1207 break;\r
1208 }\r
ac8504f8 1209#endif\r
4225a882 1210#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 1211 case IRMP_MATSUSHITA_PROTOCOL:\r
1212 {\r
1213 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);\r
1214 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);\r
1215\r
1216 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
1217 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA\r
1218 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA\r
1219 irsnd_busy = TRUE;\r
1220 break;\r
1221 }\r
4225a882 1222#endif\r
3d2da98a 1223#if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1\r
df24bb50 1224 case IRMP_TECHNICS_PROTOCOL:\r
1225 {\r
1226 command = bitsrevervse (irmp_data_p->command, TECHNICS_COMMAND_LEN);\r
1227\r
1228 irsnd_buffer[0] = (command & 0x07FC) >> 3; // CCCCCCCC\r
1229 irsnd_buffer[1] = ((command & 0x0007) << 5) | ((~command & 0x07C0) >> 6); // CCCccccc\r
1230 irsnd_buffer[2] = (~command & 0x003F) << 2; // cccccc\r
1231 irsnd_busy = TRUE;\r
1232 break;\r
1233 }\r
3d2da98a 1234#endif\r
770a1a9d 1235#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 1236 case IRMP_KASEIKYO_PROTOCOL:\r
1237 {\r
1238 uint8_t xor_value;\r
1239 uint16_t genre2;\r
95b27043 1240\r
df24bb50 1241 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);\r
1242 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);\r
1243 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);\r
95b27043 1244\r
df24bb50 1245 xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r
95b27043 1246\r
df24bb50 1247 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1248 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1249 irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC\r
1250 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC\r
1251 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
95b27043 1252\r
df24bb50 1253 xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r
95b27043 1254\r
df24bb50 1255 irsnd_buffer[5] = xor_value;\r
1256 irsnd_busy = TRUE;\r
1257 break;\r
1258 }\r
95b27043 1259#endif\r
1260#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 1261 case IRMP_PANASONIC_PROTOCOL:\r
1262 {\r
1263 address = bitsrevervse (irmp_data_p->address, PANASONIC_ADDRESS_LEN);\r
1264 command = bitsrevervse (irmp_data_p->command, PANASONIC_COMMAND_LEN);\r
1265\r
1266 irsnd_buffer[0] = 0x40; // 01000000\r
1267 irsnd_buffer[1] = 0x04; // 00000100\r
1268 irsnd_buffer[2] = 0x01; // 00000001\r
1269 irsnd_buffer[3] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1270 irsnd_buffer[4] = (address & 0x00FF); // AAAAAAAA\r
1271 irsnd_buffer[5] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1272 irsnd_buffer[6] = (command & 0x00FF); // CCCCCCCC\r
1273\r
1274 irsnd_busy = TRUE;\r
1275 break;\r
1276 }\r
770a1a9d 1277#endif\r
7365350c 1278#if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1\r
1279 case IRMP_MITSU_HEAVY_PROTOCOL:\r
1280 {\r
1281 address = irmp_data_p->address;\r
1282 command = irmp_data_p->command;\r
1283\r
1284 irsnd_buffer[0] = 0x4A;\r
1285 irsnd_buffer[1] = 0x75;\r
1286 irsnd_buffer[2] = 0xC3;\r
1287 irsnd_buffer[3] = 0x64;\r
1288 irsnd_buffer[4] = 0x9B;\r
1289 irsnd_buffer[5] = ~(address & 0xFF00) >> 8;\r
1290 irsnd_buffer[6] = (address & 0xFF00) >> 8;\r
1291 irsnd_buffer[7] = ~(address & 0x00FF);\r
1292 irsnd_buffer[8] = (address & 0x00FF);\r
1293 irsnd_buffer[9] = ~(command & 0x00FF);\r
1294 irsnd_buffer[10] = (command & 0x00FF);\r
1295\r
1296 irsnd_busy = TRUE;\r
1297 break;\r
1298 }\r
1299#endif\r
4225a882 1300#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 1301 case IRMP_RECS80_PROTOCOL:\r
1302 {\r
30d1689d 1303 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x80;\r
df24bb50 1304\r
30d1689d 1305 irsnd_buffer[0] = toggle_bit_recs80 | ((irmp_data_p->address & 0x000F) << 4) |\r
1306 ((irmp_data_p->command & 0x003C) >> 2); // TAAACCCC\r
1307 irsnd_buffer[1] = (irmp_data_p->command & 0x03) << 6; // CC000000\r
df24bb50 1308 irsnd_busy = TRUE;\r
1309 break;\r
1310 }\r
4225a882 1311#endif\r
1312#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 1313 case IRMP_RECS80EXT_PROTOCOL:\r
1314 {\r
1315 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;\r
1316\r
1317 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |\r
1318 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC\r
1319 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000\r
1320 irsnd_busy = TRUE;\r
1321 break;\r
1322 }\r
4225a882 1323#endif\r
1324#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 1325 case IRMP_RC5_PROTOCOL:\r
1326 {\r
1327 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;\r
1328\r
1329 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |\r
1330 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC\r
1331 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000\r
1332 irsnd_busy = TRUE;\r
1333 break;\r
1334 }\r
4225a882 1335#endif\r
9547ee89 1336#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 1337 case IRMP_RC6_PROTOCOL:\r
1338 {\r
1339 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
1340\r
1341 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000\r
1342 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC\r
1343 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC\r
1344 irsnd_busy = TRUE;\r
1345 break;\r
1346 }\r
9547ee89 1347#endif\r
1348#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 1349 case IRMP_RC6A_PROTOCOL:\r
1350 {\r
1351 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
1352\r
1353 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110\r
1354 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA\r
1355 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC\r
1356 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
1357 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC\r
1358 irsnd_busy = TRUE;\r
1359 break;\r
1360 }\r
9547ee89 1361#endif\r
4225a882 1362#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 1363 case IRMP_DENON_PROTOCOL:\r
1364 {\r
1365 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)\r
1366 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC\r
1367 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)\r
1368 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc\r
1369 irsnd_busy = TRUE;\r
1370 break;\r
1371 }\r
4225a882 1372#endif\r
beda975f 1373#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 1374 case IRMP_THOMSON_PROTOCOL:\r
1375 {\r
1376 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;\r
1377\r
1378 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)\r
1379 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC\r
1380 irsnd_busy = TRUE;\r
1381 break;\r
1382 }\r
95b27043 1383#endif\r
1384#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 1385 case IRMP_BOSE_PROTOCOL:\r
1386 {\r
1387 command = bitsrevervse (irmp_data_p->command, BOSE_COMMAND_LEN);\r
1388\r
1389 irsnd_buffer[0] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1390 irsnd_buffer[1] = ~((command & 0xFF00) >> 8); // cccccccc\r
1391 irsnd_busy = TRUE;\r
1392 break;\r
1393 }\r
beda975f 1394#endif\r
4225a882 1395#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 1396 case IRMP_NUBERT_PROTOCOL:\r
1397 {\r
1398 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
1399 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
1400 irsnd_busy = TRUE;\r
1401 break;\r
1402 }\r
5481e9cd 1403#endif\r
0715cf5e 1404#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 1405 case IRMP_FAN_PROTOCOL:\r
1406 {\r
1407 irsnd_buffer[0] = irmp_data_p->command >> 3; // CCCCCCCC\r
1408 irsnd_buffer[1] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
1409 irsnd_busy = TRUE;\r
1410 break;\r
1411 }\r
0715cf5e 1412#endif\r
15dd9c32 1413#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 1414 case IRMP_SPEAKER_PROTOCOL:\r
1415 {\r
1416 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
1417 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
1418 irsnd_busy = TRUE;\r
1419 break;\r
1420 }\r
15dd9c32 1421#endif\r
5481e9cd 1422#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 1423 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
1424 {\r
1425 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC\r
1426 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC\r
1427 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
1428 irsnd_busy = TRUE;\r
1429 break;\r
1430 }\r
4225a882 1431#endif\r
5b437ff6 1432#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 1433 case IRMP_GRUNDIG_PROTOCOL:\r
1434 {\r
1435 command = bitsrevervse (irmp_data_p->command, TELEFUNKEN_COMMAND_LEN);\r
5b437ff6 1436\r
df24bb50 1437 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)\r
1438 irsnd_buffer[1] = 0xC0; // 11\r
1439 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)\r
1440 irsnd_buffer[3] = (command << 6) & 0xC0; // CC\r
d155e9ab 1441\r
df24bb50 1442 irsnd_busy = TRUE;\r
1443 break;\r
1444 }\r
d155e9ab 1445#endif\r
9c07687e 1446#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 1447 case IRMP_TELEFUNKEN_PROTOCOL:\r
1448 {\r
1449 irsnd_buffer[0] = irmp_data_p->command >> 7; // CCCCCCCC\r
1450 irsnd_buffer[1] = (irmp_data_p->command << 1) & 0xff; // CCCCCCC\r
9c07687e 1451\r
df24bb50 1452 irsnd_busy = TRUE;\r
1453 break;\r
1454 }\r
9c07687e 1455#endif\r
a48187fa 1456#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 1457 case IRMP_IR60_PROTOCOL:\r
1458 {\r
1459 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);\r
08f2dd9d 1460#if 0\r
df24bb50 1461 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)\r
1462 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)\r
08f2dd9d 1463#else\r
df24bb50 1464 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)\r
1465 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)\r
08f2dd9d 1466#endif\r
a48187fa 1467\r
df24bb50 1468 irsnd_busy = TRUE;\r
1469 break;\r
1470 }\r
a48187fa 1471#endif\r
d155e9ab 1472#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 1473 case IRMP_NOKIA_PROTOCOL:\r
1474 {\r
1475 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);\r
1476 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);\r
1477\r
1478 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)\r
1479 irsnd_buffer[1] = 0xFF; // 11111111\r
1480 irsnd_buffer[2] = 0x80; // 1\r
1481 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)\r
1482 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA\r
1483 irsnd_buffer[5] = (address << 7); // A\r
1484\r
1485 irsnd_busy = TRUE;\r
1486 break;\r
1487 }\r
5b437ff6 1488#endif\r
a7054daf 1489#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 1490 case IRMP_SIEMENS_PROTOCOL:\r
1491 {\r
1492 irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA\r
1493 irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC\r
1494 irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r
1495\r
1496 irsnd_busy = TRUE;\r
1497 break;\r
1498 }\r
b5ea7869 1499#endif\r
cb93f9e9 1500#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 1501 case IRMP_RUWIDO_PROTOCOL:\r
1502 {\r
1503 irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA\r
1504 irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC\r
1505 irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c\r
1506 irsnd_busy = TRUE;\r
1507 break;\r
1508 }\r
cb93f9e9 1509#endif\r
48664931 1510#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 1511 case IRMP_FDC_PROTOCOL:\r
1512 {\r
1513 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);\r
1514 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);\r
1515\r
1516 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA\r
1517 irsnd_buffer[1] = 0; // 00000000\r
1518 irsnd_buffer[2] = 0; // 0000RRRR\r
1519 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC\r
1520 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc\r
1521 irsnd_busy = TRUE;\r
1522 break;\r
1523 }\r
c7c9a4a1 1524#endif\r
1525#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 1526 case IRMP_RCCAR_PROTOCOL:\r
1527 {\r
1528 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1\r
1529 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V\r
1530\r
1531 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3\r
1532 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0\r
30d1689d 1533\r
df24bb50 1534 irsnd_busy = TRUE;\r
1535 break;\r
1536 }\r
a7054daf 1537#endif\r
c7a47e89 1538#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 1539 case IRMP_JVC_PROTOCOL:\r
1540 {\r
1541 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);\r
1542 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);\r
c7a47e89 1543\r
df24bb50 1544 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC\r
1545 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
c7a47e89 1546\r
df24bb50 1547 irsnd_busy = TRUE;\r
1548 break;\r
1549 }\r
c7a47e89 1550#endif\r
9405f84a 1551#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 1552 case IRMP_NIKON_PROTOCOL:\r
1553 {\r
1554 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC\r
1555 irsnd_busy = TRUE;\r
1556 break;\r
1557 }\r
f50e01e7 1558#endif\r
1559#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 1560 case IRMP_LEGO_PROTOCOL:\r
1561 {\r
1562 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);\r
1563\r
1564 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
1565 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc\r
1566 irsnd_busy = TRUE;\r
1567 break;\r
1568 }\r
fa09ce10 1569#endif\r
1570#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 1571 case IRMP_A1TVBOX_PROTOCOL:\r
1572 {\r
1573 irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA\r
1574 irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC\r
1575 irsnd_buffer[2] = (irmp_data_p->command << 6); // CC\r
1576\r
1577 irsnd_busy = TRUE;\r
1578 break;\r
1579 }\r
e664a9f3 1580#endif\r
c9b6916a 1581#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 1582 case IRMP_ROOMBA_PROTOCOL:\r
1583 {\r
1584 irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.\r
1585 irsnd_busy = TRUE;\r
1586 break;\r
1587 }\r
c9b6916a 1588#endif\r
003c1008 1589#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 1590 case IRMP_PENTAX_PROTOCOL:\r
1591 {\r
1592 irsnd_buffer[0] = (irmp_data_p->command & 0x3F) << 2; // CCCCCC..\r
1593 irsnd_busy = TRUE;\r
1594 break;\r
1595 }\r
003c1008 1596#endif\r
43c535be 1597#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
1598# define ACP_SET_BIT(acp24_bitno, c, irmp_bitno) \\r
df24bb50 1599 do \\r
1600 { \\r
1601 if ((c) & (1<<(irmp_bitno))) \\r
1602 { \\r
1603 irsnd_buffer[((acp24_bitno)>>3)] |= 1 << (((7 - (acp24_bitno)) & 0x07)); \\r
1604 } \\r
1605 } while (0)\r
1606\r
1607 case IRMP_ACP24_PROTOCOL:\r
1608 {\r
1609 uint16_t cmd = irmp_data_p->command;\r
1610 uint8_t i;\r
1611\r
1612 address = bitsrevervse (irmp_data_p->address, ACP24_ADDRESS_LEN);\r
1613\r
1614 for (i = 0; i < 8; i++)\r
1615 {\r
1616 irsnd_buffer[i] = 0x00; // CCCCCCCC\r
1617 }\r
1618\r
1619 // ACP24-Frame:\r
1620 // 1 2 3 4 5 6\r
1621 // 0123456789012345678901234567890123456789012345678901234567890123456789\r
1622 // N VVMMM ? ??? t vmA x y TTTT\r
30d1689d 1623 //\r
df24bb50 1624 // irmp_data_p->command:\r
30d1689d 1625 //\r
df24bb50 1626 // 5432109876543210\r
1627 // NAVVvMMMmtxyTTTT\r
1628\r
1629 ACP_SET_BIT( 0, cmd, 15);\r
1630 ACP_SET_BIT(24, cmd, 14);\r
1631 ACP_SET_BIT( 2, cmd, 13);\r
1632 ACP_SET_BIT( 3, cmd, 12);\r
1633 ACP_SET_BIT(22, cmd, 11);\r
1634 ACP_SET_BIT( 4, cmd, 10);\r
1635 ACP_SET_BIT( 5, cmd, 9);\r
1636 ACP_SET_BIT( 6, cmd, 8);\r
1637 ACP_SET_BIT(23, cmd, 7);\r
1638 ACP_SET_BIT(20, cmd, 6);\r
1639 ACP_SET_BIT(26, cmd, 5);\r
1640 ACP_SET_BIT(44, cmd, 4);\r
1641 ACP_SET_BIT(66, cmd, 3);\r
1642 ACP_SET_BIT(67, cmd, 2);\r
1643 ACP_SET_BIT(68, cmd, 1);\r
1644 ACP_SET_BIT(69, cmd, 0);\r
1645\r
1646 irsnd_busy = TRUE;\r
1647 break;\r
1648 }\r
1649#endif\r
1650\r
1651 default:\r
1652 {\r
1653 break;\r
1654 }\r
4225a882 1655 }\r
1656\r
1657 return irsnd_busy;\r
1658}\r
1659\r
beda975f 1660void\r
1661irsnd_stop (void)\r
1662{\r
acf7fb44 1663 irsnd_repeat = 0;\r
beda975f 1664}\r
1665\r
4225a882 1666/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
1667 * ISR routine\r
1668 * @details ISR routine, called 10000 times per second\r
1669 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
1670 */\r
1671uint8_t\r
1672irsnd_ISR (void)\r
1673{\r
a48187fa 1674 static uint8_t send_trailer = FALSE;\r
1675 static uint8_t current_bit = 0xFF;\r
1676 static uint8_t pulse_counter = 0;\r
1677 static IRSND_PAUSE_LEN pause_counter = 0;\r
1678 static uint8_t startbit_pulse_len = 0;\r
1679 static IRSND_PAUSE_LEN startbit_pause_len = 0;\r
1680 static uint8_t pulse_1_len = 0;\r
1681 static uint8_t pause_1_len = 0;\r
1682 static uint8_t pulse_0_len = 0;\r
1683 static uint8_t pause_0_len = 0;\r
1684 static uint8_t has_stop_bit = 0;\r
1685 static uint8_t new_frame = TRUE;\r
1686 static uint8_t complete_data_len = 0;\r
1687 static uint8_t n_repeat_frames = 0; // number of repetition frames\r
1688 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions\r
1689 static uint8_t auto_repetition_counter = 0; // auto_repetition counter\r
1690 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!\r
1691 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!\r
1692 static uint8_t repeat_counter = 0; // repeat counter\r
1693 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!\r
1694 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!\r
5481e9cd 1695#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
a48187fa 1696 static uint8_t last_bit_value;\r
5481e9cd 1697#endif\r
a48187fa 1698 static uint8_t pulse_len = 0xFF;\r
08f2dd9d 1699 static IRSND_PAUSE_LEN pause_len = 0xFF;\r
4225a882 1700\r
1701 if (irsnd_busy)\r
1702 {\r
df24bb50 1703 if (current_bit == 0xFF && new_frame) // start of transmission...\r
1704 {\r
1705 if (auto_repetition_counter > 0)\r
1706 {\r
1707 auto_repetition_pause_counter++;\r
08f2dd9d 1708\r
df24bb50 1709 if (auto_repetition_pause_counter >= auto_repetition_pause_len)\r
1710 {\r
1711 auto_repetition_pause_counter = 0;\r
4225a882 1712\r
08f2dd9d 1713#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 1714 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame\r
1715 {\r
1716 current_bit = 16;\r
1717 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;\r
1718 }\r
1719 else\r
08f2dd9d 1720#endif\r
1721#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 1722 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame\r
1723 {\r
1724 current_bit = 15;\r
1725 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;\r
1726 }\r
1727 else\r
08f2dd9d 1728#endif\r
1729#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 1730 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame\r
1731 {\r
1732 current_bit = 7;\r
1733 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;\r
1734 }\r
1735 else\r
08f2dd9d 1736#endif\r
1737#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 1738 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame\r
1739 {\r
1740 if (auto_repetition_counter + 1 < n_auto_repetitions)\r
1741 {\r
1742 current_bit = 23;\r
1743 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;\r
1744 }\r
1745 else // nokia stop frame\r
1746 {\r
1747 current_bit = 0xFF;\r
1748 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
1749 }\r
1750 }\r
1751 else\r
1752#endif\r
1753 {\r
1754 ;\r
1755 }\r
1756 }\r
1757 else\r
1758 {\r
cb93f9e9 1759#ifdef ANALYZE\r
df24bb50 1760 if (irsnd_is_on)\r
1761 {\r
1762 putchar ('0');\r
1763 }\r
1764 else\r
1765 {\r
1766 putchar ('1');\r
1767 }\r
1768#endif\r
1769 return irsnd_busy;\r
1770 }\r
1771 }\r
1772 else if (packet_repeat_pause_counter < repeat_frame_pause_len)\r
1773 {\r
1774 packet_repeat_pause_counter++;\r
cb93f9e9 1775#ifdef ANALYZE\r
df24bb50 1776 if (irsnd_is_on)\r
1777 {\r
1778 putchar ('0');\r
1779 }\r
1780 else\r
1781 {\r
1782 putchar ('1');\r
1783 }\r
1784#endif\r
1785 return irsnd_busy;\r
1786 }\r
1787 else\r
1788 {\r
1789 if (send_trailer)\r
1790 {\r
1791 irsnd_busy = FALSE;\r
1792 send_trailer = FALSE;\r
1793 return irsnd_busy;\r
1794 }\r
30d1689d 1795\r
df24bb50 1796 n_repeat_frames = irsnd_repeat;\r
1797\r
1798 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)\r
1799 {\r
1800 n_repeat_frames = 255;\r
1801 }\r
1802\r
1803 packet_repeat_pause_counter = 0;\r
1804 pulse_counter = 0;\r
1805 pause_counter = 0;\r
1806\r
1807 switch (irsnd_protocol)\r
1808 {\r
4225a882 1809#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 1810 case IRMP_SIRCS_PROTOCOL:\r
1811 {\r
1812 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;\r
1813 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;\r
1814 pulse_1_len = SIRCS_1_PULSE_LEN;\r
1815 pause_1_len = SIRCS_PAUSE_LEN - 1;\r
1816 pulse_0_len = SIRCS_0_PULSE_LEN;\r
1817 pause_0_len = SIRCS_PAUSE_LEN - 1;\r
1818 has_stop_bit = SIRCS_STOP_BIT;\r
1819 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;\r
1820 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame\r
1821 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause\r
1822 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;\r
1823 irsnd_set_freq (IRSND_FREQ_40_KHZ);\r
1824 break;\r
1825 }\r
4225a882 1826#endif\r
1827#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 1828 case IRMP_NEC_PROTOCOL:\r
1829 {\r
1830 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1831\r
1832 if (repeat_counter > 0)\r
1833 {\r
1834 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;\r
1835 complete_data_len = 0;\r
1836 }\r
1837 else\r
1838 {\r
1839 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1840 complete_data_len = NEC_COMPLETE_DATA_LEN;\r
1841 }\r
1842\r
1843 pulse_1_len = NEC_PULSE_LEN;\r
1844 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1845 pulse_0_len = NEC_PULSE_LEN;\r
1846 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1847 has_stop_bit = NEC_STOP_BIT;\r
1848 n_auto_repetitions = 1; // 1 frame\r
1849 auto_repetition_pause_len = 0;\r
1850 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1851 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1852 break;\r
1853 }\r
4225a882 1854#endif\r
7644ac04 1855#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 1856 case IRMP_NEC16_PROTOCOL:\r
1857 {\r
1858 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1859 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1860 pulse_1_len = NEC_PULSE_LEN;\r
1861 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1862 pulse_0_len = NEC_PULSE_LEN;\r
1863 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1864 has_stop_bit = NEC_STOP_BIT;\r
1865 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit\r
1866 n_auto_repetitions = 1; // 1 frame\r
1867 auto_repetition_pause_len = 0;\r
1868 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1869 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1870 break;\r
1871 }\r
7644ac04 1872#endif\r
1873#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 1874 case IRMP_NEC42_PROTOCOL:\r
1875 {\r
1876 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1877 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1878 pulse_1_len = NEC_PULSE_LEN;\r
1879 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1880 pulse_0_len = NEC_PULSE_LEN;\r
1881 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1882 has_stop_bit = NEC_STOP_BIT;\r
1883 complete_data_len = NEC42_COMPLETE_DATA_LEN;\r
1884 n_auto_repetitions = 1; // 1 frame\r
1885 auto_repetition_pause_len = 0;\r
1886 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1887 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1888 break;\r
1889 }\r
7644ac04 1890#endif\r
c1dfa01f 1891#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 1892 case IRMP_LGAIR_PROTOCOL:\r
1893 {\r
1894 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1895 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1896 pulse_1_len = NEC_PULSE_LEN;\r
1897 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1898 pulse_0_len = NEC_PULSE_LEN;\r
1899 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1900 has_stop_bit = NEC_STOP_BIT;\r
1901 complete_data_len = LGAIR_COMPLETE_DATA_LEN;\r
1902 n_auto_repetitions = 1; // 1 frame\r
1903 auto_repetition_pause_len = 0;\r
1904 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1905 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1906 break;\r
1907 }\r
c1dfa01f 1908#endif\r
4225a882 1909#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 1910 case IRMP_SAMSUNG_PROTOCOL:\r
1911 {\r
1912 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1913 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1914 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1915 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1916 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1917 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1918 has_stop_bit = SAMSUNG_STOP_BIT;\r
1919 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;\r
1920 n_auto_repetitions = 1; // 1 frame\r
1921 auto_repetition_pause_len = 0;\r
1922 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;\r
1923 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1924 break;\r
1925 }\r
1926\r
1927 case IRMP_SAMSUNG32_PROTOCOL:\r
1928 {\r
1929 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1930 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1931 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1932 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1933 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1934 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1935 has_stop_bit = SAMSUNG_STOP_BIT;\r
1936 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;\r
1937 n_auto_repetitions = SAMSUNG32_FRAMES; // 1 frame\r
1938 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r
1939 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;\r
1940 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1941 break;\r
1942 }\r
4225a882 1943#endif\r
ac8504f8 1944#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 1945 case IRMP_SAMSUNG48_PROTOCOL:\r
1946 {\r
1947 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1948 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1949 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1950 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1951 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1952 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1953 has_stop_bit = SAMSUNG_STOP_BIT;\r
1954 complete_data_len = SAMSUNG48_COMPLETE_DATA_LEN;\r
1955 n_auto_repetitions = SAMSUNG48_FRAMES; // 1 frame\r
1956 auto_repetition_pause_len = SAMSUNG48_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r
1957 repeat_frame_pause_len = SAMSUNG48_FRAME_REPEAT_PAUSE_LEN;\r
1958 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1959 break;\r
1960 }\r
ac8504f8 1961#endif\r
4225a882 1962#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 1963 case IRMP_MATSUSHITA_PROTOCOL:\r
1964 {\r
1965 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
1966 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r
1967 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
1968 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r
1969 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
1970 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r
1971 has_stop_bit = MATSUSHITA_STOP_BIT;\r
1972 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;\r
1973 n_auto_repetitions = 1; // 1 frame\r
1974 auto_repetition_pause_len = 0;\r
1975 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r
1976 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1977 break;\r
1978 }\r
4225a882 1979#endif\r
3d2da98a 1980#if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1\r
df24bb50 1981 case IRMP_TECHNICS_PROTOCOL:\r
1982 {\r
1983 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
1984 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r
1985 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
1986 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r
1987 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
1988 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r
1989 has_stop_bit = MATSUSHITA_STOP_BIT;\r
1990 complete_data_len = TECHNICS_COMPLETE_DATA_LEN; // here TECHNICS\r
1991 n_auto_repetitions = 1; // 1 frame\r
1992 auto_repetition_pause_len = 0;\r
1993 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r
1994 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1995 break;\r
1996 }\r
3d2da98a 1997#endif\r
770a1a9d 1998#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 1999 case IRMP_KASEIKYO_PROTOCOL:\r
2000 {\r
2001 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;\r
2002 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;\r
2003 pulse_1_len = KASEIKYO_PULSE_LEN;\r
2004 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;\r
2005 pulse_0_len = KASEIKYO_PULSE_LEN;\r
2006 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;\r
2007 has_stop_bit = KASEIKYO_STOP_BIT;\r
2008 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;\r
2009 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame\r
2010 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause\r
2011 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;\r
2012 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2013 break;\r
2014 }\r
95b27043 2015#endif\r
2016#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 2017 case IRMP_PANASONIC_PROTOCOL:\r
2018 {\r
2019 startbit_pulse_len = PANASONIC_START_BIT_PULSE_LEN;\r
2020 startbit_pause_len = PANASONIC_START_BIT_PAUSE_LEN - 1;\r
2021 pulse_1_len = PANASONIC_PULSE_LEN;\r
2022 pause_1_len = PANASONIC_1_PAUSE_LEN - 1;\r
2023 pulse_0_len = PANASONIC_PULSE_LEN;\r
2024 pause_0_len = PANASONIC_0_PAUSE_LEN - 1;\r
2025 has_stop_bit = PANASONIC_STOP_BIT;\r
2026 complete_data_len = PANASONIC_COMPLETE_DATA_LEN;\r
2027 n_auto_repetitions = PANASONIC_FRAMES; // 1 frame\r
2028 auto_repetition_pause_len = PANASONIC_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause\r
2029 repeat_frame_pause_len = PANASONIC_FRAME_REPEAT_PAUSE_LEN;\r
2030 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2031 break;\r
2032 }\r
770a1a9d 2033#endif\r
7365350c 2034#if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1\r
2035 case IRMP_MITSU_HEAVY_PROTOCOL:\r
2036 {\r
2037 startbit_pulse_len = MITSU_HEAVY_START_BIT_PULSE_LEN;\r
2038 startbit_pause_len = MITSU_HEAVY_START_BIT_PAUSE_LEN - 1;\r
2039 pulse_1_len = MITSU_HEAVY_PULSE_LEN;\r
2040 pause_1_len = MITSU_HEAVY_1_PAUSE_LEN - 1;\r
2041 pulse_0_len = MITSU_HEAVY_PULSE_LEN;\r
2042 pause_0_len = MITSU_HEAVY_0_PAUSE_LEN - 1;\r
2043 has_stop_bit = MITSU_HEAVY_STOP_BIT;\r
2044 complete_data_len = MITSU_HEAVY_COMPLETE_DATA_LEN;\r
2045 n_auto_repetitions = MITSU_HEAVY_FRAMES; // 1 frame\r
2046 auto_repetition_pause_len = 0;;\r
2047 repeat_frame_pause_len = MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN;\r
2048 irsnd_set_freq (IRSND_FREQ_40_KHZ);\r
2049 break;\r
2050 }\r
2051#endif\r
4225a882 2052#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 2053 case IRMP_RECS80_PROTOCOL:\r
2054 {\r
2055 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;\r
2056 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;\r
2057 pulse_1_len = RECS80_PULSE_LEN;\r
2058 pause_1_len = RECS80_1_PAUSE_LEN - 1;\r
2059 pulse_0_len = RECS80_PULSE_LEN;\r
2060 pause_0_len = RECS80_0_PAUSE_LEN - 1;\r
2061 has_stop_bit = RECS80_STOP_BIT;\r
2062 complete_data_len = RECS80_COMPLETE_DATA_LEN;\r
2063 n_auto_repetitions = 1; // 1 frame\r
2064 auto_repetition_pause_len = 0;\r
2065 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;\r
2066 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2067 break;\r
2068 }\r
4225a882 2069#endif\r
2070#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 2071 case IRMP_RECS80EXT_PROTOCOL:\r
2072 {\r
2073 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;\r
2074 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;\r
2075 pulse_1_len = RECS80EXT_PULSE_LEN;\r
2076 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;\r
2077 pulse_0_len = RECS80EXT_PULSE_LEN;\r
2078 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;\r
2079 has_stop_bit = RECS80EXT_STOP_BIT;\r
2080 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;\r
2081 n_auto_repetitions = 1; // 1 frame\r
2082 auto_repetition_pause_len = 0;\r
2083 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;\r
2084 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2085 break;\r
2086 }\r
4225a882 2087#endif\r
9c07687e 2088#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 2089 case IRMP_TELEFUNKEN_PROTOCOL:\r
2090 {\r
2091 startbit_pulse_len = TELEFUNKEN_START_BIT_PULSE_LEN;\r
2092 startbit_pause_len = TELEFUNKEN_START_BIT_PAUSE_LEN - 1;\r
2093 pulse_1_len = TELEFUNKEN_PULSE_LEN;\r
2094 pause_1_len = TELEFUNKEN_1_PAUSE_LEN - 1;\r
2095 pulse_0_len = TELEFUNKEN_PULSE_LEN;\r
2096 pause_0_len = TELEFUNKEN_0_PAUSE_LEN - 1;\r
2097 has_stop_bit = TELEFUNKEN_STOP_BIT;\r
2098 complete_data_len = TELEFUNKEN_COMPLETE_DATA_LEN;\r
2099 n_auto_repetitions = 1; // 1 frames\r
2100 auto_repetition_pause_len = 0; // TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN; // xx ms pause\r
2101 repeat_frame_pause_len = TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2102 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2103 break;\r
2104 }\r
9c07687e 2105#endif\r
4225a882 2106#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 2107 case IRMP_RC5_PROTOCOL:\r
2108 {\r
2109 startbit_pulse_len = RC5_BIT_LEN;\r
2110 startbit_pause_len = RC5_BIT_LEN;\r
2111 pulse_len = RC5_BIT_LEN;\r
2112 pause_len = RC5_BIT_LEN;\r
2113 has_stop_bit = RC5_STOP_BIT;\r
2114 complete_data_len = RC5_COMPLETE_DATA_LEN;\r
2115 n_auto_repetitions = 1; // 1 frame\r
2116 auto_repetition_pause_len = 0;\r
2117 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;\r
2118 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2119 break;\r
2120 }\r
4225a882 2121#endif\r
9547ee89 2122#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 2123 case IRMP_RC6_PROTOCOL:\r
2124 {\r
2125 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
2126 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
2127 pulse_len = RC6_BIT_LEN;\r
2128 pause_len = RC6_BIT_LEN;\r
2129 has_stop_bit = RC6_STOP_BIT;\r
2130 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;\r
2131 n_auto_repetitions = 1; // 1 frame\r
2132 auto_repetition_pause_len = 0;\r
2133 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
2134 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2135 break;\r
2136 }\r
9547ee89 2137#endif\r
2138#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2139 case IRMP_RC6A_PROTOCOL:\r
2140 {\r
2141 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
2142 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
2143 pulse_len = RC6_BIT_LEN;\r
2144 pause_len = RC6_BIT_LEN;\r
2145 has_stop_bit = RC6_STOP_BIT;\r
2146 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;\r
2147 n_auto_repetitions = 1; // 1 frame\r
2148 auto_repetition_pause_len = 0;\r
2149 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
2150 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2151 break;\r
2152 }\r
9547ee89 2153#endif\r
4225a882 2154#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 2155 case IRMP_DENON_PROTOCOL:\r
2156 {\r
2157 startbit_pulse_len = 0x00;\r
2158 startbit_pause_len = 0x00;\r
2159 pulse_1_len = DENON_PULSE_LEN;\r
2160 pause_1_len = DENON_1_PAUSE_LEN - 1;\r
2161 pulse_0_len = DENON_PULSE_LEN;\r
2162 pause_0_len = DENON_0_PAUSE_LEN - 1;\r
2163 has_stop_bit = DENON_STOP_BIT;\r
2164 complete_data_len = DENON_COMPLETE_DATA_LEN;\r
2165 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command\r
2166 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame\r
2167 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r
2168 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better\r
2169 break;\r
2170 }\r
4225a882 2171#endif\r
beda975f 2172#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 2173 case IRMP_THOMSON_PROTOCOL:\r
2174 {\r
2175 startbit_pulse_len = 0x00;\r
2176 startbit_pause_len = 0x00;\r
2177 pulse_1_len = THOMSON_PULSE_LEN;\r
2178 pause_1_len = THOMSON_1_PAUSE_LEN - 1;\r
2179 pulse_0_len = THOMSON_PULSE_LEN;\r
2180 pause_0_len = THOMSON_0_PAUSE_LEN - 1;\r
2181 has_stop_bit = THOMSON_STOP_BIT;\r
2182 complete_data_len = THOMSON_COMPLETE_DATA_LEN;\r
2183 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame\r
2184 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;\r
2185 repeat_frame_pause_len = THOMSON_FRAME_REPEAT_PAUSE_LEN;\r
2186 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2187 break;\r
2188 }\r
95b27043 2189#endif\r
2190#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 2191 case IRMP_BOSE_PROTOCOL:\r
2192 {\r
2193 startbit_pulse_len = BOSE_START_BIT_PULSE_LEN;\r
2194 startbit_pause_len = BOSE_START_BIT_PAUSE_LEN - 1;\r
2195 pulse_1_len = BOSE_PULSE_LEN;\r
2196 pause_1_len = BOSE_1_PAUSE_LEN - 1;\r
2197 pulse_0_len = BOSE_PULSE_LEN;\r
2198 pause_0_len = BOSE_0_PAUSE_LEN - 1;\r
2199 has_stop_bit = BOSE_STOP_BIT;\r
2200 complete_data_len = BOSE_COMPLETE_DATA_LEN;\r
2201 n_auto_repetitions = BOSE_FRAMES; // 1 frame\r
2202 auto_repetition_pause_len = BOSE_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause\r
2203 repeat_frame_pause_len = BOSE_FRAME_REPEAT_PAUSE_LEN;\r
2204 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2205 break;\r
2206 }\r
beda975f 2207#endif\r
4225a882 2208#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 2209 case IRMP_NUBERT_PROTOCOL:\r
2210 {\r
2211 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;\r
2212 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;\r
2213 pulse_1_len = NUBERT_1_PULSE_LEN;\r
2214 pause_1_len = NUBERT_1_PAUSE_LEN - 1;\r
2215 pulse_0_len = NUBERT_0_PULSE_LEN;\r
2216 pause_0_len = NUBERT_0_PAUSE_LEN - 1;\r
2217 has_stop_bit = NUBERT_STOP_BIT;\r
2218 complete_data_len = NUBERT_COMPLETE_DATA_LEN;\r
2219 n_auto_repetitions = NUBERT_FRAMES; // 2 frames\r
2220 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2221 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;\r
2222 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2223 break;\r
2224 }\r
5481e9cd 2225#endif\r
0715cf5e 2226#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 2227 case IRMP_FAN_PROTOCOL:\r
2228 {\r
2229 startbit_pulse_len = FAN_START_BIT_PULSE_LEN;\r
2230 startbit_pause_len = FAN_START_BIT_PAUSE_LEN - 1;\r
2231 pulse_1_len = FAN_1_PULSE_LEN;\r
2232 pause_1_len = FAN_1_PAUSE_LEN - 1;\r
2233 pulse_0_len = FAN_0_PULSE_LEN;\r
2234 pause_0_len = FAN_0_PAUSE_LEN - 1;\r
2235 has_stop_bit = FAN_STOP_BIT;\r
2236 complete_data_len = FAN_COMPLETE_DATA_LEN;\r
2237 n_auto_repetitions = FAN_FRAMES; // only 1 frame\r
2238 auto_repetition_pause_len = FAN_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2239 repeat_frame_pause_len = FAN_FRAME_REPEAT_PAUSE_LEN;\r
2240 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2241 break;\r
2242 }\r
0715cf5e 2243#endif\r
15dd9c32 2244#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 2245 case IRMP_SPEAKER_PROTOCOL:\r
2246 {\r
2247 startbit_pulse_len = SPEAKER_START_BIT_PULSE_LEN;\r
2248 startbit_pause_len = SPEAKER_START_BIT_PAUSE_LEN - 1;\r
2249 pulse_1_len = SPEAKER_1_PULSE_LEN;\r
2250 pause_1_len = SPEAKER_1_PAUSE_LEN - 1;\r
2251 pulse_0_len = SPEAKER_0_PULSE_LEN;\r
2252 pause_0_len = SPEAKER_0_PAUSE_LEN - 1;\r
2253 has_stop_bit = SPEAKER_STOP_BIT;\r
2254 complete_data_len = SPEAKER_COMPLETE_DATA_LEN;\r
2255 n_auto_repetitions = SPEAKER_FRAMES; // 2 frames\r
2256 auto_repetition_pause_len = SPEAKER_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2257 repeat_frame_pause_len = SPEAKER_FRAME_REPEAT_PAUSE_LEN;\r
2258 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2259 break;\r
2260 }\r
15dd9c32 2261#endif\r
5481e9cd 2262#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2263 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
2264 {\r
2265 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;\r
2266 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;\r
2267 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;\r
2268 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;\r
2269 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;\r
2270 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;\r
2271 has_stop_bit = BANG_OLUFSEN_STOP_BIT;\r
2272 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;\r
2273 n_auto_repetitions = 1; // 1 frame\r
2274 auto_repetition_pause_len = 0;\r
2275 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;\r
2276 last_bit_value = 0;\r
2277 irsnd_set_freq (IRSND_FREQ_455_KHZ);\r
2278 break;\r
2279 }\r
5b437ff6 2280#endif\r
2281#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 2282 case IRMP_GRUNDIG_PROTOCOL:\r
2283 {\r
2284 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2285 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2286 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2287 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2288 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2289 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;\r
2290 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames\r
2291 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
2292 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2293 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2294 break;\r
2295 }\r
a48187fa 2296#endif\r
2297#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 2298 case IRMP_IR60_PROTOCOL:\r
2299 {\r
2300 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2301 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2302 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2303 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2304 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2305 complete_data_len = IR60_COMPLETE_DATA_LEN;\r
2306 n_auto_repetitions = IR60_FRAMES; // 2 frames\r
2307 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
2308 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2309 irsnd_set_freq (IRSND_FREQ_30_KHZ);\r
2310 break;\r
2311 }\r
d155e9ab 2312#endif\r
2313#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2314 case IRMP_NOKIA_PROTOCOL:\r
2315 {\r
2316 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2317 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2318 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2319 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2320 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2321 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
2322 n_auto_repetitions = NOKIA_FRAMES; // 2 frames\r
2323 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause\r
2324 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2325 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2326 break;\r
2327 }\r
a7054daf 2328#endif\r
2329#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 2330 case IRMP_SIEMENS_PROTOCOL:\r
2331 {\r
2332 startbit_pulse_len = SIEMENS_BIT_LEN;\r
2333 startbit_pause_len = SIEMENS_BIT_LEN;\r
2334 pulse_len = SIEMENS_BIT_LEN;\r
2335 pause_len = SIEMENS_BIT_LEN;\r
2336 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
2337 complete_data_len = SIEMENS_COMPLETE_DATA_LEN;\r
2338 n_auto_repetitions = 1; // 1 frame\r
2339 auto_repetition_pause_len = 0;\r
2340 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;\r
2341 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2342 break;\r
2343 }\r
b5ea7869 2344#endif\r
cb93f9e9 2345#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 2346 case IRMP_RUWIDO_PROTOCOL:\r
2347 {\r
2348 startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;\r
2349 startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;\r
2350 pulse_len = RUWIDO_BIT_PULSE_LEN;\r
2351 pause_len = RUWIDO_BIT_PAUSE_LEN;\r
2352 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
2353 complete_data_len = RUWIDO_COMPLETE_DATA_LEN;\r
2354 n_auto_repetitions = 1; // 1 frame\r
2355 auto_repetition_pause_len = 0;\r
2356 repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;\r
2357 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2358 break;\r
2359 }\r
cb93f9e9 2360#endif\r
48664931 2361#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 2362 case IRMP_FDC_PROTOCOL:\r
2363 {\r
2364 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;\r
2365 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;\r
2366 complete_data_len = FDC_COMPLETE_DATA_LEN;\r
2367 pulse_1_len = FDC_PULSE_LEN;\r
2368 pause_1_len = FDC_1_PAUSE_LEN - 1;\r
2369 pulse_0_len = FDC_PULSE_LEN;\r
2370 pause_0_len = FDC_0_PAUSE_LEN - 1;\r
2371 has_stop_bit = FDC_STOP_BIT;\r
2372 n_auto_repetitions = 1; // 1 frame\r
2373 auto_repetition_pause_len = 0;\r
2374 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;\r
2375 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2376 break;\r
2377 }\r
c7c9a4a1 2378#endif\r
2379#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 2380 case IRMP_RCCAR_PROTOCOL:\r
2381 {\r
2382 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;\r
2383 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;\r
2384 complete_data_len = RCCAR_COMPLETE_DATA_LEN;\r
2385 pulse_1_len = RCCAR_PULSE_LEN;\r
2386 pause_1_len = RCCAR_1_PAUSE_LEN - 1;\r
2387 pulse_0_len = RCCAR_PULSE_LEN;\r
2388 pause_0_len = RCCAR_0_PAUSE_LEN - 1;\r
2389 has_stop_bit = RCCAR_STOP_BIT;\r
2390 n_auto_repetitions = 1; // 1 frame\r
2391 auto_repetition_pause_len = 0;\r
2392 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;\r
2393 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2394 break;\r
2395 }\r
4225a882 2396#endif\r
c7a47e89 2397#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 2398 case IRMP_JVC_PROTOCOL:\r
2399 {\r
2400 if (repeat_counter != 0) // skip start bit if repetition frame\r
2401 {\r
2402 current_bit = 0;\r
2403 }\r
2404\r
2405 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;\r
2406 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;\r
2407 complete_data_len = JVC_COMPLETE_DATA_LEN;\r
2408 pulse_1_len = JVC_PULSE_LEN;\r
2409 pause_1_len = JVC_1_PAUSE_LEN - 1;\r
2410 pulse_0_len = JVC_PULSE_LEN;\r
2411 pause_0_len = JVC_0_PAUSE_LEN - 1;\r
2412 has_stop_bit = JVC_STOP_BIT;\r
2413 n_auto_repetitions = 1; // 1 frame\r
2414 auto_repetition_pause_len = 0;\r
2415 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;\r
2416 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2417 break;\r
2418 }\r
c7a47e89 2419#endif\r
9405f84a 2420#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 2421 case IRMP_NIKON_PROTOCOL:\r
2422 {\r
2423 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;\r
2424 startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;\r
2425 complete_data_len = NIKON_COMPLETE_DATA_LEN;\r
2426 pulse_1_len = NIKON_PULSE_LEN;\r
2427 pause_1_len = NIKON_1_PAUSE_LEN - 1;\r
2428 pulse_0_len = NIKON_PULSE_LEN;\r
2429 pause_0_len = NIKON_0_PAUSE_LEN - 1;\r
2430 has_stop_bit = NIKON_STOP_BIT;\r
2431 n_auto_repetitions = 1; // 1 frame\r
2432 auto_repetition_pause_len = 0;\r
2433 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;\r
2434 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2435 break;\r
2436 }\r
9405f84a 2437#endif\r
f50e01e7 2438#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 2439 case IRMP_LEGO_PROTOCOL:\r
2440 {\r
2441 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;\r
2442 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;\r
2443 complete_data_len = LEGO_COMPLETE_DATA_LEN;\r
2444 pulse_1_len = LEGO_PULSE_LEN;\r
2445 pause_1_len = LEGO_1_PAUSE_LEN - 1;\r
2446 pulse_0_len = LEGO_PULSE_LEN;\r
2447 pause_0_len = LEGO_0_PAUSE_LEN - 1;\r
2448 has_stop_bit = LEGO_STOP_BIT;\r
2449 n_auto_repetitions = 1; // 1 frame\r
2450 auto_repetition_pause_len = 0;\r
2451 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;\r
2452 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2453 break;\r
2454 }\r
fa09ce10 2455#endif\r
2456#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2457 case IRMP_A1TVBOX_PROTOCOL:\r
2458 {\r
2459 startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN\r
2460 startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN\r
2461 pulse_len = A1TVBOX_BIT_PULSE_LEN;\r
2462 pause_len = A1TVBOX_BIT_PAUSE_LEN;\r
2463 has_stop_bit = A1TVBOX_STOP_BIT;\r
2464 complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data\r
2465 n_auto_repetitions = 1; // 1 frame\r
2466 auto_repetition_pause_len = 0;\r
2467 repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;\r
2468 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2469 break;\r
2470 }\r
c9b6916a 2471#endif\r
2472#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 2473 case IRMP_ROOMBA_PROTOCOL:\r
2474 {\r
2475 startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;\r
2476 startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;\r
2477 pulse_1_len = ROOMBA_1_PULSE_LEN;\r
2478 pause_1_len = ROOMBA_1_PAUSE_LEN - 1;\r
2479 pulse_0_len = ROOMBA_0_PULSE_LEN;\r
2480 pause_0_len = ROOMBA_0_PAUSE_LEN - 1;\r
2481 has_stop_bit = ROOMBA_STOP_BIT;\r
2482 complete_data_len = ROOMBA_COMPLETE_DATA_LEN;\r
2483 n_auto_repetitions = ROOMBA_FRAMES; // 8 frames\r
2484 auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
2485 repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
2486 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2487 break;\r
2488 }\r
003c1008 2489#endif\r
2490#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 2491 case IRMP_PENTAX_PROTOCOL:\r
2492 {\r
2493 startbit_pulse_len = PENTAX_START_BIT_PULSE_LEN;\r
2494 startbit_pause_len = PENTAX_START_BIT_PAUSE_LEN;\r
2495 complete_data_len = PENTAX_COMPLETE_DATA_LEN;\r
2496 pulse_1_len = PENTAX_PULSE_LEN;\r
2497 pause_1_len = PENTAX_1_PAUSE_LEN - 1;\r
2498 pulse_0_len = PENTAX_PULSE_LEN;\r
2499 pause_0_len = PENTAX_0_PAUSE_LEN - 1;\r
2500 has_stop_bit = PENTAX_STOP_BIT;\r
2501 n_auto_repetitions = 1; // 1 frame\r
2502 auto_repetition_pause_len = 0;\r
2503 repeat_frame_pause_len = PENTAX_FRAME_REPEAT_PAUSE_LEN;\r
2504 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2505 break;\r
2506 }\r
43c535be 2507#endif\r
2508#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
df24bb50 2509 case IRMP_ACP24_PROTOCOL:\r
2510 {\r
2511 startbit_pulse_len = ACP24_START_BIT_PULSE_LEN;\r
2512 startbit_pause_len = ACP24_START_BIT_PAUSE_LEN - 1;\r
2513 complete_data_len = ACP24_COMPLETE_DATA_LEN;\r
2514 pulse_1_len = ACP24_PULSE_LEN;\r
2515 pause_1_len = ACP24_1_PAUSE_LEN - 1;\r
2516 pulse_0_len = ACP24_PULSE_LEN;\r
2517 pause_0_len = ACP24_0_PAUSE_LEN - 1;\r
2518 has_stop_bit = ACP24_STOP_BIT;\r
2519 n_auto_repetitions = 1; // 1 frame\r
2520 auto_repetition_pause_len = 0;\r
2521 repeat_frame_pause_len = ACP24_FRAME_REPEAT_PAUSE_LEN;\r
2522 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2523 break;\r
2524 }\r
2525#endif\r
2526 default:\r
2527 {\r
2528 irsnd_busy = FALSE;\r
2529 break;\r
2530 }\r
2531 }\r
2532 }\r
2533 }\r
2534\r
2535 if (irsnd_busy)\r
2536 {\r
2537 new_frame = FALSE;\r
2538\r
2539 switch (irsnd_protocol)\r
2540 {\r
4225a882 2541#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 2542 case IRMP_SIRCS_PROTOCOL:\r
4225a882 2543#endif\r
2544#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 2545 case IRMP_NEC_PROTOCOL:\r
4225a882 2546#endif\r
7644ac04 2547#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 2548 case IRMP_NEC16_PROTOCOL:\r
7644ac04 2549#endif\r
2550#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 2551 case IRMP_NEC42_PROTOCOL:\r
7644ac04 2552#endif\r
c1dfa01f 2553#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 2554 case IRMP_LGAIR_PROTOCOL:\r
c1dfa01f 2555#endif\r
4225a882 2556#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 2557 case IRMP_SAMSUNG_PROTOCOL:\r
2558 case IRMP_SAMSUNG32_PROTOCOL:\r
4225a882 2559#endif\r
ac8504f8 2560#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 2561 case IRMP_SAMSUNG48_PROTOCOL:\r
ac8504f8 2562#endif\r
4225a882 2563#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 2564 case IRMP_MATSUSHITA_PROTOCOL:\r
4225a882 2565#endif\r
3d2da98a 2566#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 2567 case IRMP_TECHNICS_PROTOCOL:\r
3d2da98a 2568#endif\r
770a1a9d 2569#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 2570 case IRMP_KASEIKYO_PROTOCOL:\r
95b27043 2571#endif\r
2572#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 2573 case IRMP_PANASONIC_PROTOCOL:\r
770a1a9d 2574#endif\r
7365350c 2575#if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1\r
2576 case IRMP_MITSU_HEAVY_PROTOCOL:\r
2577#endif\r
4225a882 2578#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 2579 case IRMP_RECS80_PROTOCOL:\r
4225a882 2580#endif\r
2581#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 2582 case IRMP_RECS80EXT_PROTOCOL:\r
4225a882 2583#endif\r
9c07687e 2584#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 2585 case IRMP_TELEFUNKEN_PROTOCOL:\r
9c07687e 2586#endif\r
4225a882 2587#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 2588 case IRMP_DENON_PROTOCOL:\r
95b27043 2589#endif\r
2590#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 2591 case IRMP_BOSE_PROTOCOL:\r
4225a882 2592#endif\r
2593#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 2594 case IRMP_NUBERT_PROTOCOL:\r
5481e9cd 2595#endif\r
0715cf5e 2596#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 2597 case IRMP_FAN_PROTOCOL:\r
0715cf5e 2598#endif\r
15dd9c32 2599#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 2600 case IRMP_SPEAKER_PROTOCOL:\r
15dd9c32 2601#endif\r
5481e9cd 2602#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2603 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
4225a882 2604#endif\r
c7c9a4a1 2605#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 2606 case IRMP_FDC_PROTOCOL:\r
b5ea7869 2607#endif\r
c7c9a4a1 2608#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 2609 case IRMP_RCCAR_PROTOCOL:\r
c7c9a4a1 2610#endif\r
c7a47e89 2611#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 2612 case IRMP_JVC_PROTOCOL:\r
c7a47e89 2613#endif\r
9405f84a 2614#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 2615 case IRMP_NIKON_PROTOCOL:\r
9405f84a 2616#endif\r
f50e01e7 2617#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 2618 case IRMP_LEGO_PROTOCOL:\r
f50e01e7 2619#endif\r
cb93f9e9 2620#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 2621 case IRMP_THOMSON_PROTOCOL:\r
cb93f9e9 2622#endif\r
c9b6916a 2623#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 2624 case IRMP_ROOMBA_PROTOCOL:\r
c9b6916a 2625#endif\r
003c1008 2626#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 2627 case IRMP_PENTAX_PROTOCOL:\r
003c1008 2628#endif\r
43c535be 2629#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
df24bb50 2630 case IRMP_ACP24_PROTOCOL:\r
43c535be 2631#endif\r
a7054daf 2632\r
7644ac04 2633#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \\r
3d2da98a 2634 IRSND_SUPPORT_LGAIR_PROTOCOL == 1 || IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || IRSND_SUPPORT_TECHNICS_PROTOCOL == 1 || \\r
770a1a9d 2635 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \\r
0715cf5e 2636 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_FAN_PROTOCOL == 1 || IRSND_SUPPORT_SPEAKER_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \\r
2637 IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || \\r
2638 IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || IRSND_SUPPORT_ROOMBA_PROTOCOL == 1 || IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1 || \\r
7365350c 2639 IRSND_SUPPORT_PENTAX_PROTOCOL == 1 || IRSND_SUPPORT_ACP24_PROTOCOL == 1 || IRSND_SUPPORT_PANASONIC_PROTOCOL == 1 || IRSND_SUPPORT_BOSE_PROTOCOL == 1 || \\r
2640 IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1\r
df24bb50 2641 {\r
2642 if (pulse_counter == 0)\r
2643 {\r
2644 if (current_bit == 0xFF) // send start bit\r
2645 {\r
2646 pulse_len = startbit_pulse_len;\r
2647 pause_len = startbit_pause_len;\r
2648 }\r
2649 else if (current_bit < complete_data_len) // send n'th bit\r
2650 {\r
5481e9cd 2651#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 2652 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)\r
2653 {\r
2654 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits\r
2655 {\r
2656 pulse_len = SAMSUNG_PULSE_LEN;\r
2657 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?\r
2658 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
2659 }\r
2660 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)\r
2661 {\r
2662 pulse_len = SAMSUNG_PULSE_LEN;\r
2663 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
2664 }\r
2665 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit\r
2666 {\r
2667 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
2668\r
2669 pulse_len = SAMSUNG_PULSE_LEN;\r
2670 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?\r
2671 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
2672 }\r
2673 }\r
2674 else\r
5481e9cd 2675#endif\r
2676\r
7644ac04 2677#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 2678 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)\r
2679 {\r
2680 if (current_bit < NEC16_ADDRESS_LEN) // send address bits\r
2681 {\r
2682 pulse_len = NEC_PULSE_LEN;\r
2683 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?\r
2684 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
2685 }\r
2686 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)\r
2687 {\r
2688 pulse_len = NEC_PULSE_LEN;\r
2689 pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
2690 }\r
2691 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit\r
2692 {\r
2693 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
2694\r
2695 pulse_len = NEC_PULSE_LEN;\r
2696 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?\r
2697 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
2698 }\r
2699 }\r
2700 else\r
7644ac04 2701#endif\r
2702\r
5481e9cd 2703#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2704 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)\r
2705 {\r
2706 if (current_bit == 0) // send 2nd start bit\r
2707 {\r
2708 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
2709 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
2710 }\r
2711 else if (current_bit == 1) // send 3rd start bit\r
2712 {\r
2713 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;\r
2714 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;\r
2715 }\r
2716 else if (current_bit == 2) // send 4th start bit\r
2717 {\r
2718 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
2719 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
2720 }\r
2721 else if (current_bit == 19) // send trailer bit\r
2722 {\r
2723 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
2724 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;\r
2725 }\r
2726 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit\r
2727 {\r
2728 uint8_t cur_bit_value = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? 1 : 0;\r
2729 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
2730\r
2731 if (cur_bit_value == last_bit_value)\r
2732 {\r
2733 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;\r
2734 }\r
2735 else\r
2736 {\r
2737 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);\r
2738 last_bit_value = cur_bit_value;\r
2739 }\r
2740 }\r
2741 }\r
2742 else\r
2743#endif\r
2744 if (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7))))\r
2745 {\r
2746 pulse_len = pulse_1_len;\r
2747 pause_len = pause_1_len;\r
2748 }\r
2749 else\r
2750 {\r
2751 pulse_len = pulse_0_len;\r
2752 pause_len = pause_0_len;\r
2753 }\r
2754 }\r
2755 else if (has_stop_bit) // send stop bit\r
2756 {\r
2757 pulse_len = pulse_0_len;\r
2758\r
2759 if (auto_repetition_counter < n_auto_repetitions)\r
2760 {\r
2761 pause_len = pause_0_len;\r
2762 }\r
2763 else\r
2764 {\r
2765 pause_len = 255; // last frame: pause of 255\r
2766 }\r
2767 }\r
2768 }\r
2769\r
2770 if (pulse_counter < pulse_len)\r
2771 {\r
2772 if (pulse_counter == 0)\r
2773 {\r
2774 irsnd_on ();\r
2775 }\r
2776 pulse_counter++;\r
2777 }\r
2778 else if (pause_counter < pause_len)\r
2779 {\r
2780 if (pause_counter == 0)\r
2781 {\r
2782 irsnd_off ();\r
2783 }\r
2784 pause_counter++;\r
2785 }\r
2786 else\r
2787 {\r
2788 current_bit++;\r
2789\r
2790 if (current_bit >= complete_data_len + has_stop_bit)\r
2791 {\r
2792 current_bit = 0xFF;\r
2793 auto_repetition_counter++;\r
2794\r
2795 if (auto_repetition_counter == n_auto_repetitions)\r
2796 {\r
2797 irsnd_busy = FALSE;\r
2798 auto_repetition_counter = 0;\r
2799 }\r
2800 new_frame = TRUE;\r
2801 }\r
2802\r
2803 pulse_counter = 0;\r
2804 pause_counter = 0;\r
2805 }\r
2806 break;\r
2807 }\r
a7054daf 2808#endif\r
2809\r
4225a882 2810#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 2811 case IRMP_RC5_PROTOCOL:\r
a7054daf 2812#endif\r
9547ee89 2813#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 2814 case IRMP_RC6_PROTOCOL:\r
9547ee89 2815#endif\r
2816#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2817 case IRMP_RC6A_PROTOCOL:\r
9547ee89 2818#endif\r
a7054daf 2819#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 2820 case IRMP_SIEMENS_PROTOCOL:\r
a7054daf 2821#endif\r
cb93f9e9 2822#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 2823 case IRMP_RUWIDO_PROTOCOL:\r
cb93f9e9 2824#endif\r
a7054daf 2825#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 2826 case IRMP_GRUNDIG_PROTOCOL:\r
a7054daf 2827#endif\r
a48187fa 2828#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 2829 case IRMP_IR60_PROTOCOL:\r
a48187fa 2830#endif\r
a7054daf 2831#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2832 case IRMP_NOKIA_PROTOCOL:\r
fa09ce10 2833#endif\r
2834#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2835 case IRMP_A1TVBOX_PROTOCOL:\r
a7054daf 2836#endif\r
4225a882 2837\r
cb93f9e9 2838#if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \\r
2839 IRSND_SUPPORT_RC6_PROTOCOL == 1 || \\r
2840 IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \\r
2841 IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \\r
2842 IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r
2843 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \\r
2844 IRSND_SUPPORT_IR60_PROTOCOL == 1 || \\r
2845 IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \\r
2846 IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2847 {\r
2848 if (pulse_counter == pulse_len && pause_counter == pause_len)\r
2849 {\r
2850 current_bit++;\r
4225a882 2851\r
df24bb50 2852 if (current_bit >= complete_data_len)\r
2853 {\r
2854 current_bit = 0xFF;\r
a7054daf 2855\r
a48187fa 2856#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2857 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
2858 {\r
2859 auto_repetition_counter++;\r
2860\r
2861 if (repeat_counter > 0)\r
2862 { // set 117 msec pause time\r
2863 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;\r
2864 }\r
2865\r
2866 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame\r
2867 {\r
2868 n_auto_repetitions++; // increment number of auto repetitions\r
2869 repeat_counter++;\r
2870 }\r
2871 else if (auto_repetition_counter == n_auto_repetitions)\r
2872 {\r
2873 irsnd_busy = FALSE;\r
2874 auto_repetition_counter = 0;\r
2875 }\r
2876 }\r
2877 else\r
2878#endif\r
2879 {\r
2880 irsnd_busy = FALSE;\r
2881 }\r
2882\r
2883 new_frame = TRUE;\r
2884 irsnd_off ();\r
2885 }\r
2886\r
2887 pulse_counter = 0;\r
2888 pause_counter = 0;\r
2889 }\r
2890\r
2891 if (! new_frame)\r
2892 {\r
2893 uint8_t first_pulse;\r
5b437ff6 2894\r
a48187fa 2895#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2896 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
2897 {\r
2898 if (current_bit == 0xFF || // start bit of start-frame\r
2899 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)\r
2900 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)\r
2901 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)\r
2902 {\r
2903 pulse_len = startbit_pulse_len;\r
2904 pause_len = startbit_pause_len;\r
2905 first_pulse = TRUE;\r
2906 }\r
2907 else // send n'th bit\r
2908 {\r
2909 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2910 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2911 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;\r
2912 }\r
2913 }\r
2914 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||\r
2915 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)\r
2916#endif\r
2917 {\r
2918 if (current_bit == 0xFF) // 1 start bit\r
2919 {\r
9547ee89 2920#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2921 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2922 {\r
2923 pulse_len = startbit_pulse_len;\r
2924 pause_len = startbit_pause_len;\r
2925 }\r
2926 else\r
fa09ce10 2927#endif\r
2928#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2929 if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)\r
2930 {\r
2931 current_bit = 0;\r
2932 }\r
2933 else\r
2934#endif\r
2935 {\r
2936 ;\r
2937 }\r
2938\r
2939 first_pulse = TRUE;\r
2940 }\r
2941 else // send n'th bit\r
2942 {\r
9547ee89 2943#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2944 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2945 {\r
2946 pulse_len = RC6_BIT_LEN;\r
2947 pause_len = RC6_BIT_LEN;\r
2948\r
2949 if (irsnd_protocol == IRMP_RC6_PROTOCOL)\r
2950 {\r
2951 if (current_bit == 4) // toggle bit (double len)\r
2952 {\r
2953 pulse_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN\r
2954 pause_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN\r
2955 }\r
2956 }\r
2957 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2958 {\r
2959 if (current_bit == 4) // toggle bit (double len)\r
2960 {\r
2961 pulse_len = RC6_BIT_3_LEN; // = 3 * RC6_BIT_LEN\r
2962 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN\r
2963 }\r
2964 else if (current_bit == 5) // toggle bit (double len)\r
2965 {\r
2966 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN\r
2967 }\r
2968 }\r
2969 }\r
2970#endif\r
2971 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;\r
2972 }\r
2973\r
2974 if (irsnd_protocol == IRMP_RC5_PROTOCOL)\r
2975 {\r
2976 first_pulse = first_pulse ? FALSE : TRUE;\r
2977 }\r
2978 }\r
2979\r
2980 if (first_pulse)\r
2981 {\r
2982 // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
2983\r
2984 if (pulse_counter < pulse_len)\r
2985 {\r
2986 if (pulse_counter == 0)\r
2987 {\r
2988 irsnd_on ();\r
2989 }\r
2990 pulse_counter++;\r
2991 }\r
2992 else // if (pause_counter < pause_len)\r
2993 {\r
2994 if (pause_counter == 0)\r
2995 {\r
2996 irsnd_off ();\r
2997 }\r
2998 pause_counter++;\r
2999 }\r
3000 }\r
3001 else\r
3002 {\r
3003 // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
3004\r
3005 if (pause_counter < pause_len)\r
3006 {\r
3007 if (pause_counter == 0)\r
3008 {\r
3009 irsnd_off ();\r
3010 }\r
3011 pause_counter++;\r
3012 }\r
3013 else // if (pulse_counter < pulse_len)\r
3014 {\r
3015 if (pulse_counter == 0)\r
3016 {\r
3017 irsnd_on ();\r
3018 }\r
3019 pulse_counter++;\r
3020 }\r
3021 }\r
3022 }\r
3023 break;\r
3024 }\r
9547ee89 3025#endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||\r
cb93f9e9 3026 // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
5b437ff6 3027\r
df24bb50 3028 default:\r
3029 {\r
3030 irsnd_busy = FALSE;\r
3031 break;\r
3032 }\r
3033 }\r
3034 }\r
3035\r
3036 if (! irsnd_busy)\r
3037 {\r
3038 if (repeat_counter < n_repeat_frames)\r
3039 {\r
c7c9a4a1 3040#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 3041 if (irsnd_protocol == IRMP_FDC_PROTOCOL)\r
3042 {\r
3043 irsnd_buffer[2] |= 0x0F;\r
3044 }\r
3045#endif\r
3046 repeat_counter++;\r
3047 irsnd_busy = TRUE;\r
3048 }\r
3049 else\r
3050 {\r
3051 irsnd_busy = TRUE; //Rainer\r
3052 send_trailer = TRUE;\r
3053 n_repeat_frames = 0;\r
3054 repeat_counter = 0;\r
3055 }\r
3056 }\r
4225a882 3057 }\r
3058\r
cb93f9e9 3059#ifdef ANALYZE\r
4225a882 3060 if (irsnd_is_on)\r
3061 {\r
df24bb50 3062 putchar ('0');\r
4225a882 3063 }\r
3064 else\r
3065 {\r
df24bb50 3066 putchar ('1');\r
4225a882 3067 }\r
3068#endif\r
3069\r
3070 return irsnd_busy;\r
3071}\r
3072\r
cb93f9e9 3073#ifdef ANALYZE\r
4225a882 3074\r
3075// main function - for unix/linux + windows only!\r
3076// AVR: see main.c!\r
3077// Compile it under linux with:\r
3078// cc irsnd.c -o irsnd\r
3079//\r
3080// usage: ./irsnd protocol hex-address hex-command >filename\r
3081\r
3082int\r
3083main (int argc, char ** argv)\r
3084{\r
4225a882 3085 int protocol;\r
3086 int address;\r
3087 int command;\r
4225a882 3088 IRMP_DATA irmp_data;\r
3089\r
a7054daf 3090 if (argc != 4 && argc != 5)\r
4225a882 3091 {\r
df24bb50 3092 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);\r
3093 return 1;\r
4225a882 3094 }\r
3095\r
3096 if (sscanf (argv[1], "%d", &protocol) == 1 &&\r
df24bb50 3097 sscanf (argv[2], "%x", &address) == 1 &&\r
3098 sscanf (argv[3], "%x", &command) == 1)\r
4225a882 3099 {\r
df24bb50 3100 irmp_data.protocol = protocol;\r
3101 irmp_data.address = address;\r
3102 irmp_data.command = command;\r
4225a882 3103\r
df24bb50 3104 if (argc == 5)\r
3105 {\r
3106 irmp_data.flags = atoi (argv[4]);\r
3107 }\r
3108 else\r
3109 {\r
3110 irmp_data.flags = 0;\r
3111 }\r
a7054daf 3112\r
df24bb50 3113 irsnd_init ();\r
4225a882 3114\r
df24bb50 3115 (void) irsnd_send_data (&irmp_data, TRUE);\r
4225a882 3116\r
df24bb50 3117 while (irsnd_busy)\r
3118 {\r
3119 irsnd_ISR ();\r
3120 }\r
beda975f 3121\r
df24bb50 3122 putchar ('\n');\r
a03ad359 3123\r
f874da09 3124#if 1 // enable here to send twice\r
df24bb50 3125 (void) irsnd_send_data (&irmp_data, TRUE);\r
a03ad359 3126\r
df24bb50 3127 while (irsnd_busy)\r
3128 {\r
3129 irsnd_ISR ();\r
3130 }\r
a03ad359 3131\r
df24bb50 3132 putchar ('\n');\r
f874da09 3133#endif\r
4225a882 3134 }\r
3135 else\r
3136 {\r
df24bb50 3137 fprintf (stderr, "%s: wrong arguments\n", argv[0]);\r
3138 return 1;\r
4225a882 3139 }\r
3140 return 0;\r
3141}\r
3142\r
cb93f9e9 3143#endif // ANALYZE\r
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)