]> cloudbase.mooo.com Git - irmp.git/commitdiff
Version 1.6.2: added FDC2 protocol
authorukw <ukw@aeb2e35e-bfc4-4214-b83c-9e8de998ed28>
Thu, 10 Jun 2010 23:20:36 +0000 (23:20 +0000)
committerukw <ukw@aeb2e35e-bfc4-4214-b83c-9e8de998ed28>
Thu, 10 Jun 2010 23:20:36 +0000 (23:20 +0000)
git-svn-id: svn://mikrocontroller.net/irmp@25 aeb2e35e-bfc4-4214-b83c-9e8de998ed28

irmp.c
irmpconfig.h

diff --git a/irmp.c b/irmp.c
index 90bc280d747cf098abfda171c834341077475b67..1dc8fd79a915102b38ab43be7deea7aa43a91c86 100644 (file)
--- a/irmp.c
+++ b/irmp.c
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2010 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmp.c,v 1.41 2010/06/10 21:24:50 fm Exp $\r
+ * $Id: irmp.c,v 1.42 2010/06/10 23:16:03 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -329,6 +329,15 @@ typedef unsigned int16  uint16_t;
 #define MIN_TOLERANCE_00                        1.0                           // -0%\r
 #define MAX_TOLERANCE_00                        1.0                           // +0%\r
 \r
+#define MIN_TOLERANCE_02                        0.98                          // -2%\r
+#define MAX_TOLERANCE_02                        1.02                          // +2%\r
+\r
+#define MIN_TOLERANCE_03                        0.97                          // -3%\r
+#define MAX_TOLERANCE_03                        1.03                          // +3%\r
+\r
+#define MIN_TOLERANCE_04                        0.96                          // -4%\r
+#define MAX_TOLERANCE_04                        1.04                          // +4%\r
+\r
 #define MIN_TOLERANCE_05                        0.95                          // -5%\r
 #define MAX_TOLERANCE_05                        1.05                          // +5%\r
 \r
@@ -421,10 +430,10 @@ typedef unsigned int16  uint16_t;
 #define RECS80_0_PAUSE_LEN_MIN                  ((uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
 #define RECS80_0_PAUSE_LEN_MAX                  ((uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
 \r
-#define RC5_START_BIT_LEN_MIN                   ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_00 + 0.5) - 1)\r
-#define RC5_START_BIT_LEN_MAX                   ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_00 + 0.5) + 1)\r
-#define RC5_BIT_LEN_MIN                         ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_00 + 0.5) - 1)\r
-#define RC5_BIT_LEN_MAX                         ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_00 + 0.5) + 1)\r
+#define RC5_START_BIT_LEN_MIN                   ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define RC5_START_BIT_LEN_MAX                   ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+#define RC5_BIT_LEN_MIN                         ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define RC5_BIT_LEN_MAX                         ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
 \r
 #define DENON_PULSE_LEN_MIN                     ((uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
 #define DENON_PULSE_LEN_MAX                     ((uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
@@ -1304,7 +1313,7 @@ irmp_ISR (void)
 #if IRMP_SUPPORT_RC5_PROTOCOL == 1\r
     static uint8_t    rc5_cmd_bit6;                                             // bit 6 of RC5 command is the inverted 2nd start bit\r
 #endif\r
-#if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_SIEMENS_PROTOCOL == 1\r
+#if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_GRUNDIG_OR_NOKIA_PROTOCOL == 1 || IRMP_SUPPORT_SIEMENS_PROTOCOL == 1\r
     static uint8_t    last_pause;                                               // last pause value\r
 #endif\r
 #if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \\r
index 7fadb9059fd07f3532450276407effa7961c1a6f..1e503adbd5a6270ff8521ad12026d347204edd14 100644 (file)
 #define IRMP_SUPPORT_FDC2_PROTOCOL              0       // DO NOT CHANGE! F_INTERRUPTS too low!\r
 #endif\r
 \r
+\r
+#if IRMP_SUPPORT_FDC2_PROTOCOL == 1 && IRMP_SUPPORT_RC5_PROTOCOL == 1\r
+#error Protocols RC5 and FDC2 may not be enabled both at the same time. Please disable one of them in irmpconfig.h.\r
+#endif\r
+\r
 /*---------------------------------------------------------------------------------------------------------------------------------------------------\r
  * Change hardware pin here:\r
  *---------------------------------------------------------------------------------------------------------------------------------------------------\r