*\r
* Copyright (c) 2009-2010 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmp.c,v 1.41 2010/06/10 21:24:50 fm Exp $\r
+ * $Id: irmp.c,v 1.42 2010/06/10 23:16:03 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
#define MIN_TOLERANCE_00 1.0 // -0%\r
#define MAX_TOLERANCE_00 1.0 // +0%\r
\r
+#define MIN_TOLERANCE_02 0.98 // -2%\r
+#define MAX_TOLERANCE_02 1.02 // +2%\r
+\r
+#define MIN_TOLERANCE_03 0.97 // -3%\r
+#define MAX_TOLERANCE_03 1.03 // +3%\r
+\r
+#define MIN_TOLERANCE_04 0.96 // -4%\r
+#define MAX_TOLERANCE_04 1.04 // +4%\r
+\r
#define MIN_TOLERANCE_05 0.95 // -5%\r
#define MAX_TOLERANCE_05 1.05 // +5%\r
\r
#define RECS80_0_PAUSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
#define RECS80_0_PAUSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
\r
-#define RC5_START_BIT_LEN_MIN ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_00 + 0.5) - 1)\r
-#define RC5_START_BIT_LEN_MAX ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_00 + 0.5) + 1)\r
-#define RC5_BIT_LEN_MIN ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_00 + 0.5) - 1)\r
-#define RC5_BIT_LEN_MAX ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_00 + 0.5) + 1)\r
+#define RC5_START_BIT_LEN_MIN ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define RC5_START_BIT_LEN_MAX ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+#define RC5_BIT_LEN_MIN ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define RC5_BIT_LEN_MAX ((uint8_t)(F_INTERRUPTS * RC5_BIT_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
\r
#define DENON_PULSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
#define DENON_PULSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
#if IRMP_SUPPORT_RC5_PROTOCOL == 1\r
static uint8_t rc5_cmd_bit6; // bit 6 of RC5 command is the inverted 2nd start bit\r
#endif\r
-#if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_SIEMENS_PROTOCOL == 1\r
+#if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_GRUNDIG_OR_NOKIA_PROTOCOL == 1 || IRMP_SUPPORT_SIEMENS_PROTOCOL == 1\r
static uint8_t last_pause; // last pause value\r
#endif\r
#if IRMP_SUPPORT_RC5_PROTOCOL == 1 || IRMP_SUPPORT_RC6_PROTOCOL == 1 || IRMP_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \\r
#define IRMP_SUPPORT_FDC2_PROTOCOL 0 // DO NOT CHANGE! F_INTERRUPTS too low!\r
#endif\r
\r
+\r
+#if IRMP_SUPPORT_FDC2_PROTOCOL == 1 && IRMP_SUPPORT_RC5_PROTOCOL == 1\r
+#error Protocols RC5 and FDC2 may not be enabled both at the same time. Please disable one of them in irmpconfig.h.\r
+#endif\r
+\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* Change hardware pin here:\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r