* ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284\r
* ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r
*\r
- * $Id: irsnd.c,v 1.55 2012/05/24 06:55:11 fm Exp $\r
+ * $Id: irsnd.c,v 1.56 2012/06/05 12:00:46 fm Exp $\r
*\r
* This program is free software; you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
# if defined(PIC_C18) // PIC C18\r
IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
# elif defined (ARM_STM32) // STM32\r
- IRSND_TIMER->CCER |= (uint16_t)TIM_CCER_CC1E;\r
- TIM_Cmd(IRSND_TIMER, ENABLE); // TIMx enable counter\r
+ TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
+ TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+ TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r
# else // AVR\r
# if IRSND_OCx == IRSND_OC2 // use OC2\r
TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r
# if defined(PIC_C18) // PIC C18\r
IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
# elif defined (ARM_STM32) // STM32\r
- IRSND_TIMER->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
- TIM_Cmd(IRSND_TIMER, DISABLE); // TIMx enable counter\r
+ TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r
+ TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r
+ TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+ TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r
# else //AVR\r
\r
# if IRSND_OCx == IRSND_OC2 // use OC2\r
freq = TimeBaseFreq/freq;\r
\r
/* Set frequency */\r
- TIM_SetAutoreload(IRSND_TIMER, freq);\r
+ TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
/* Set duty cycle */\r
TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
# else // AVR\r
# endif\r
\r
/* Time base configuration */\r
- TIM_TimeBaseStructure.TIM_Period = 0; // will be initialized later\r
+ TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r
TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
/* PWM1 Mode configuration */\r
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
- TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
+ TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
\r
/* Preload configuration */\r
- TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
+ TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
\r
- irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
+ irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r
# else // AVR\r
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
*\r
* Copyright (c) 2010-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irsnd.h,v 1.12 2012/05/23 12:26:26 fm Exp $\r
+ * $Id: irsnd.h,v 1.13 2012/06/05 12:00:46 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
# endif\r
# define IRSND_BIT CONCAT(GPIO_Pin_, IRSND_BIT_NUMBER)\r
# define IRSND_TIMER CONCAT(TIM, IRSND_TIMER_NUMBER)\r
+# define IRSND_TIMER_CHANNEL CONCAT(TIM_Channel_, IRSND_TIMER_CHANNEL_NUMBER)\r
# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
# define IRSND_TIMER_RCC CONCAT(RCC_APB1Periph_TIM, IRSND_TIMER_NUMBER)\r
# elif (IRSND_TIMER_NUMBER == 1) || ((IRSND_TIMER_NUMBER >= 8) && (IRSND_TIMER_NUMBER <= 11))\r