IRMP - Infrared Multi Protocol Decoder\r
--------------------------------------\r
\r
-Version IRMP: 2.3.2 06.11.2012\r
+Version IRMP: 2.3.3 19.11.2012\r
Version IRSND: 2.3.2 29.10.2012\r
\r
Dokumentation:\r
*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmp.c,v 1.130 2012/11/06 10:19:41 fm Exp $\r
+ * $Id: irmp.c,v 1.131 2012/11/18 17:51:26 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
#endif\r
GPIO_Init(IRMP_PORT, &GPIO_InitStructure);\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+ // Enable the GPIO port\r
+ ROM_SysCtlPeripheralEnable(IRMP_PORT_PERIPH);\r
+\r
+ // Set as an input\r
+ ROM_GPIODirModeSet(IRMP_PORT_BASE, IRMP_PORT_PIN, GPIO_DIR_MODE_IN);\r
+ ROM_GPIOPadConfigSet(IRMP_PORT_BASE, IRMP_PORT_PIN,\r
+ GPIO_STRENGTH_2MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
#else // AVR\r
IRMP_PORT &= ~(1<<IRMP_BIT); // deactivate pullup\r
IRMP_DDR &= ~(1<<IRMP_BIT); // set pin to input\r
}\r
}\r
}\r
+\r
+#if defined(STELLARIS_ARM_CORTEX_M4)\r
+ // Clear the timer interrupt\r
+ TimerIntClear(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+#endif\r
+\r
return (irmp_ir_detected);\r
}\r
\r
*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmp.h,v 1.79 2012/05/23 12:26:25 fm Exp $\r
+ * $Id: irmp.h,v 1.80 2012/11/18 17:51:26 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
# ifndef USE_STDPERIPH_DRIVER\r
# warning The STM32 port of IRMP uses the ST standard peripheral drivers which are not enabled in your build configuration.\r
# endif\r
+#elif defined (STELLARIS_ARM_CORTEX_M4)\r
+# define _CONCAT(a,b) a##b\r
+# define CONCAT(a,b) _CONCAT(a,b)\r
+# define IRMP_PORT_PERIPH CONCAT(SYSCTL_PERIPH_GPIO, IRMP_PORT_LETTER)\r
+# define IRMP_PORT_BASE CONCAT(GPIO_PORT, CONCAT(IRMP_PORT_LETTER, _BASE))\r
+# define IRMP_PORT_PIN CONCAT(GPIO_PIN_, IRMP_BIT_NUMBER)\r
+# define IRMP_PIN IRMP_PORT_PIN\r
+# define input(x) ((uint8_t)(ROM_GPIOPinRead(IRMP_PORT_BASE, IRMP_PORT_PIN)))\r
+# define sei() IntMasterEnable()\r
#endif\r
\r
#if IRMP_SUPPORT_DENON_PROTOCOL == 1 && IRMP_SUPPORT_RUWIDO_PROTOCOL == 1\r
*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmpconfig.h,v 1.94 2012/10/26 08:12:17 fm Exp $\r
+ * $Id: irmpconfig.h,v 1.95 2012/11/18 17:51:26 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
# define IRMP_PORT_LETTER C\r
# define IRMP_BIT_NUMBER 13\r
\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * Change hardware pin here for Stellaris ARM Cortex M4\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined (STELLARIS_ARM_CORTEX_M4) // use B4 as IR input on Stellaris LM4F\r
+# define IRMP_PORT_LETTER B\r
+# define IRMP_BIT_NUMBER 4\r
+\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* Handling of unknown target system: DON'T CHANGE\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmpsystem.h,v 1.6 2012/05/23 14:02:45 fm Exp $\r
+ * $Id: irmpsystem.h,v 1.7 2012/11/18 17:51:26 fm Exp $\r
*\r
* This program is free software; you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
# include <stm32f4xx.h>\r
# define ARM_STM32\r
# define ARM_STM32F4XX\r
+#elif defined(TARGET_IS_BLIZZARD_RA2) // TI Stellaris (tested on Stellaris Launchpad with Code Composer Studio)\r
+# define STELLARIS_ARM_CORTEX_M4\r
+# define F_CPU (SysCtlClockGet())\r
#elif defined(unix) || defined(WIN32) // Unix/Linux or Windows\r
# define UNIX_OR_WINDOWS\r
#else\r
# define IRSND_OC0 3 // OC0\r
# define IRSND_OC0A 4 // OC0A\r
# define IRSND_OC0B 5 // OC0B\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+# include "inc/hw_ints.h"\r
+# include "inc/hw_memmap.h"\r
+# include "inc/hw_types.h"\r
+# include "inc/hw_gpio.h"\r
+# include "driverlib/fpu.h"\r
+# include "driverlib/sysctl.h"\r
+# include "driverlib/interrupt.h"\r
+# include "driverlib/gpio.h"\r
+# include "driverlib/rom.h"\r
+# include "driverlib/systick.h"\r
+# include "driverlib/pin_map.h"\r
+# include "driverlib/timer.h"\r
+# define PROGMEM volatile\r
+# define memcpy_P memcpy\r
+# define APP_SYSTICKS_PER_SEC 32\r
#else\r
# define PROGMEM\r
# define memcpy_P memcpy\r
#endif\r
\r
-#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32)\r
+#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32) || defined(STELLARIS_ARM_CORTEX_M4)\r
typedef unsigned char uint8_t;\r
typedef unsigned short uint16_t;\r
#endif\r
*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: main.c,v 1.14 2012/05/15 10:25:21 fm Exp $\r
+ * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
#endif\r
\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
+ TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
+\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
+ IntEnable(INT_TIMER1A);\r
+ TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+ TimerEnable(TIMER1_BASE, TIMER_A);\r
+ // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
#else // ATmegaXX:\r
OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
-#ifdef TIMSK1\r
+#if (!defined(STELLARIS_ARM_CORTEX_M4))\r
+# ifdef TIMSK1\r
TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
-#else\r
+# else\r
TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+# endif\r
#endif\r
}\r
\r
*/\r
#ifdef TIM1_COMPA_vect // ATtiny84\r
ISR(TIM1_COMPA_vect)\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+void Timer1IntHandler(void)\r
#else\r
ISR(TIMER1_COMPA_vect)\r
#endif\r
{\r
IRMP_DATA irmp_data;\r
\r
+#if defined(STELLARIS_ARM_CORTEX_M4)\r
+ ROM_FPUEnable();\r
+ ROM_FPUStackingEnable();\r
+ ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
+#endif\r
+\r
irmp_init(); // initialize irmp\r
timer1_init(); // initialize timer 1\r
sei (); // enable interrupts\r