Version 2.3.3: port to Stellaris ARM Cortex M4

git-svn-id: svn://mikrocontroller.net/irmp@108 aeb2e35e-bfc4-4214-b83c-9e8de998ed28

diff --git a/README.txt b/README.txt
index d431f7e747ee0e60dc8e69eb0ca77efca8ef9a93..00ad31c915b09432c4b591766bea67e6060f776a 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -1,7 +1,7 @@
 IRMP - Infrared Multi Protocol Decoder\r
 --------------------------------------\r
 \r
-Version IRMP:  2.3.2 06.11.2012\r
+Version IRMP:  2.3.3 19.11.2012\r
 Version IRSND: 2.3.2 29.10.2012\r
 \r
 Dokumentation:\r

diff --git a/irmp.c b/irmp.c
index ab3d59f7c0626ce90abc79b434f784545eeb4343..c8bc29f0acce60f7a951c36d44a5056a6e86b970 100644 (file)
--- a/irmp.c
+++ b/irmp.c
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmp.c,v 1.130 2012/11/06 10:19:41 fm Exp $\r
+ * $Id: irmp.c,v 1.131 2012/11/18 17:51:26 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -1292,6 +1292,15 @@ irmp_init (void)
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
  #endif\r
    GPIO_Init(IRMP_PORT, &GPIO_InitStructure);\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+     // Enable the GPIO port\r
+     ROM_SysCtlPeripheralEnable(IRMP_PORT_PERIPH);\r
+\r
+     // Set as an input\r
+     ROM_GPIODirModeSet(IRMP_PORT_BASE, IRMP_PORT_PIN, GPIO_DIR_MODE_IN);\r
+     ROM_GPIOPadConfigSet(IRMP_PORT_BASE, IRMP_PORT_PIN,\r
+                          GPIO_STRENGTH_2MA,\r
+                          GPIO_PIN_TYPE_STD_WPU);\r
 #else                                                                   // AVR\r
     IRMP_PORT &= ~(1<<IRMP_BIT);                                        // deactivate pullup\r
     IRMP_DDR &= ~(1<<IRMP_BIT);                                         // set pin to input\r
@@ -3235,6 +3244,12 @@ irmp_ISR (void)
             }\r
         }\r
     }\r
+\r
+#if defined(STELLARIS_ARM_CORTEX_M4)\r
+    // Clear the timer interrupt\r
+    TimerIntClear(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+#endif\r
+\r
     return (irmp_ir_detected);\r
 }\r
 \r

diff --git a/irmp.h b/irmp.h
index 8427be5b39032855fdf7b27dbb9c84b299a28107..84138013c98fb61c8f7a73be4c7a5df6ffb409ff 100644 (file)
--- a/irmp.h
+++ b/irmp.h
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmp.h,v 1.79 2012/05/23 12:26:25 fm Exp $\r
+ * $Id: irmp.h,v 1.80 2012/11/18 17:51:26 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -52,6 +52,15 @@
 #  ifndef USE_STDPERIPH_DRIVER\r
 #    warning The STM32 port of IRMP uses the ST standard peripheral drivers which are not enabled in your build configuration.\r
 #  endif\r
+#elif defined (STELLARIS_ARM_CORTEX_M4)\r
+#  define _CONCAT(a,b)                          a##b\r
+#  define CONCAT(a,b)                           _CONCAT(a,b)\r
+#  define IRMP_PORT_PERIPH                      CONCAT(SYSCTL_PERIPH_GPIO, IRMP_PORT_LETTER)\r
+#  define IRMP_PORT_BASE                        CONCAT(GPIO_PORT, CONCAT(IRMP_PORT_LETTER, _BASE))\r
+#  define IRMP_PORT_PIN                         CONCAT(GPIO_PIN_, IRMP_BIT_NUMBER)\r
+#  define IRMP_PIN                              IRMP_PORT_PIN\r
+#  define input(x)                              ((uint8_t)(ROM_GPIOPinRead(IRMP_PORT_BASE, IRMP_PORT_PIN)))\r
+#  define sei()                                 IntMasterEnable()\r
 #endif\r
 \r
 #if IRMP_SUPPORT_DENON_PROTOCOL == 1 && IRMP_SUPPORT_RUWIDO_PROTOCOL == 1\r

diff --git a/irmpconfig.h b/irmpconfig.h
index 08fdc4950919521bd5a594f1382c90e8598d2921..646bb427eb8a456a33785131c6a1cf67537dd34f 100644 (file)
--- a/irmpconfig.h
+++ b/irmpconfig.h
@@ -5,7 +5,7 @@
  *\r
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmpconfig.h,v 1.94 2012/10/26 08:12:17 fm Exp $\r
+ * $Id: irmpconfig.h,v 1.95 2012/11/18 17:51:26 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -113,6 +113,14 @@
 #  define IRMP_PORT_LETTER                      C\r
 #  define IRMP_BIT_NUMBER                       13\r
 \r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * Change hardware pin here for Stellaris ARM Cortex M4\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined (STELLARIS_ARM_CORTEX_M4)                                 // use B4 as IR input on Stellaris LM4F\r
+#  define IRMP_PORT_LETTER                      B\r
+#  define IRMP_BIT_NUMBER                       4\r
+\r
 /*---------------------------------------------------------------------------------------------------------------------------------------------------\r
  * Handling of unknown target system: DON'T CHANGE\r
  *---------------------------------------------------------------------------------------------------------------------------------------------------\r

diff --git a/irmpsystem.h b/irmpsystem.h
index 1e2e4df06852fdd1c414c95bada4280d5ee51ff6..b73d81f9918f3ac56554ab3caeaad08c2e5d322a 100644 (file)
--- a/irmpsystem.h
+++ b/irmpsystem.h
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmpsystem.h,v 1.6 2012/05/23 14:02:45 fm Exp $\r
+ * $Id: irmpsystem.h,v 1.7 2012/11/18 17:51:26 fm Exp $\r
  *\r
  * This program is free software; you can redistribute it and/or modify\r
  * it under the terms of the GNU General Public License as published by\r
@@ -38,6 +38,9 @@
 #  include <stm32f4xx.h>\r
 #  define ARM_STM32\r
 #  define ARM_STM32F4XX\r
+#elif defined(TARGET_IS_BLIZZARD_RA2)                                                                                           // TI Stellaris (tested on Stellaris Launchpad with Code Composer Studio)\r
+#  define STELLARIS_ARM_CORTEX_M4\r
+#  define F_CPU (SysCtlClockGet())\r
 #elif defined(unix) || defined(WIN32)                                               // Unix/Linux or Windows\r
 #  define UNIX_OR_WINDOWS\r
 #else\r
@@ -74,12 +77,28 @@ typedef unsigned short                  uint16_t;
 #  define IRSND_OC0                     3       // OC0\r
 #  define IRSND_OC0A                    4       // OC0A\r
 #  define IRSND_OC0B                    5       // OC0B\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+#  include "inc/hw_ints.h"\r
+#  include "inc/hw_memmap.h"\r
+#  include "inc/hw_types.h"\r
+#  include "inc/hw_gpio.h"\r
+#  include "driverlib/fpu.h"\r
+#  include "driverlib/sysctl.h"\r
+#  include "driverlib/interrupt.h"\r
+#  include "driverlib/gpio.h"\r
+#  include "driverlib/rom.h"\r
+#  include "driverlib/systick.h"\r
+#  include "driverlib/pin_map.h"\r
+#  include "driverlib/timer.h"\r
+#  define PROGMEM volatile\r
+#  define memcpy_P memcpy\r
+#  define APP_SYSTICKS_PER_SEC          32\r
 #else\r
 #  define PROGMEM\r
 #  define memcpy_P                      memcpy\r
 #endif\r
 \r
-#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32)\r
+#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32) || defined(STELLARIS_ARM_CORTEX_M4)\r
 typedef unsigned char                   uint8_t;\r
 typedef unsigned short                  uint16_t;\r
 #endif\r

diff --git a/main.c b/main.c
index dbcd57f548a50f5bfc4b69d8d83923cf05b3463f..2327ac6bc5adda3e94dbbc7229c2e0c27736a0ae 100644 (file)
--- a/main.c
+++ b/main.c
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: main.c,v 1.14 2012/05/15 10:25:21 fm Exp $\r
+ * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -35,15 +35,26 @@ timer1_init (void)
     TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4\r
 #endif\r
 \r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
+    TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
+\r
+    TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
+    IntEnable(INT_TIMER1A);\r
+    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+    TimerEnable(TIMER1_BASE, TIMER_A);\r
+    // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
 #else                                                                       // ATmegaXX:\r
     OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency\r
     TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1\r
 #endif\r
 \r
-#ifdef TIMSK1\r
+#if (!defined(STELLARIS_ARM_CORTEX_M4))\r
+#  ifdef TIMSK1\r
     TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
-#else\r
+#  else\r
     TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
+#  endif\r
 #endif\r
 }\r
 \r
@@ -53,6 +64,8 @@ timer1_init (void)
  */\r
 #ifdef TIM1_COMPA_vect                                                      // ATtiny84\r
 ISR(TIM1_COMPA_vect)\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+void Timer1IntHandler(void)\r
 #else\r
 ISR(TIMER1_COMPA_vect)\r
 #endif\r
@@ -67,6 +80,12 @@ main (void)
 {\r
     IRMP_DATA irmp_data;\r
 \r
+#if defined(STELLARIS_ARM_CORTEX_M4)\r
+    ROM_FPUEnable();\r
+    ROM_FPUStackingEnable();\r
+    ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
+#endif\r
+\r
     irmp_init();                                                            // initialize irmp\r
     timer1_init();                                                          // initialize timer 1\r
     sei ();                                                                 // enable interrupts\r