*\r
* Copyright (c) 2009-2011 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmp.c,v 1.113 2012/02/16 10:40:07 fm Exp $\r
+ * $Id: irmp.c,v 1.115 2012/02/21 08:41:46 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
IRMP_SUPPORT_RC6_PROTOCOL == 1 || \\r
IRMP_SUPPORT_GRUNDIG_NOKIA_IR60_PROTOCOL == 1 || \\r
IRMP_SUPPORT_SIEMENS_OR_RUWIDO_PROTOCOL == 1 || \\r
+ IRMP_SUPPORT_GRUNDIG2_PROTOCOL == 1 || \\r
IRMP_SUPPORT_IR60_PROTOCOL\r
#define IRMP_SUPPORT_MANCHESTER 1\r
#else\r
#define SIEMENS_OR_RUWIDO_BIT_PAUSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
#define SIEMENS_OR_RUWIDO_BIT_PAUSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
\r
+#define GRUNDIG2_START_BIT_PULSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * GRUNDIG2_START_BIT_PULSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define GRUNDIG2_START_BIT_PULSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * GRUNDIG2_START_BIT_PULSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+#define GRUNDIG2_START_BIT_PAUSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * GRUNDIG2_START_BIT_PAUSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define GRUNDIG2_START_BIT_PAUSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * GRUNDIG2_START_BIT_PAUSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+#define GRUNDIG2_BIT_PULSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * GRUNDIG2_BIT_PULSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define GRUNDIG2_BIT_PULSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * GRUNDIG2_BIT_PULSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+#define GRUNDIG2_BIT_PAUSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * GRUNDIG2_BIT_PAUSE_TIME * MIN_TOLERANCE_10 + 0.5) - 1)\r
+#define GRUNDIG2_BIT_PAUSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * GRUNDIG2_BIT_PAUSE_TIME * MAX_TOLERANCE_10 + 0.5) + 1)\r
+\r
#define FDC_START_BIT_PULSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME * MIN_TOLERANCE_05 + 0.5) - 1) // 5%: avoid conflict with NETBOX\r
#define FDC_START_BIT_PULSE_LEN_MAX ((uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME * MAX_TOLERANCE_05 + 0.5))\r
#define FDC_START_BIT_PAUSE_LEN_MIN ((uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME * MIN_TOLERANCE_05 + 0.5) - 1)\r
#define UART0_TXEN_BIT_VALUE (1<<TXEN0)\r
#define UART0_UDR UDR0\r
#define UART0_U2X U2X0\r
- \r
+ \r
#else\r
\r
#define UART0_UBRRH UBRRH\r
UART0_UCSRC = UART0_UCSZ1_BIT_VALUE | UART0_UCSZ0_BIT_VALUE | UART0_URSEL_BIT_VALUE;\r
UART0_UCSRB |= UART0_TXEN_BIT_VALUE; // enable UART TX\r
#else // other log method\r
- initextlog(); \r
+ initextlog(); \r
#endif //IRMP_EXT_LOGGING\r
}\r
\r
\r
#endif\r
\r
+#if IRMP_SUPPORT_GRUNDIG2_PROTOCOL == 1\r
+\r
+static const PROGMEM IRMP_PARAMETER grundig2_param =\r
+{\r
+ IRMP_GRUNDIG2_PROTOCOL, // protocol: ir protocol\r
+ GRUNDIG2_BIT_PULSE_LEN_MIN, // pulse_1_len_min: here: minimum length of short pulse\r
+ GRUNDIG2_BIT_PULSE_LEN_MAX, // pulse_1_len_max: here: maximum length of short pulse\r
+ GRUNDIG2_BIT_PAUSE_LEN_MIN, // pause_1_len_min: here: minimum length of short pause\r
+ GRUNDIG2_BIT_PAUSE_LEN_MAX, // pause_1_len_max: here: maximum length of short pause\r
+ 0, // pulse_0_len_min: here: not used\r
+ 0, // pulse_0_len_max: here: not used\r
+ 0, // pause_0_len_min: here: not used\r
+ 0, // pause_0_len_max: here: not used\r
+ GRUNDIG2_ADDRESS_OFFSET, // address_offset: address offset\r
+ GRUNDIG2_ADDRESS_OFFSET + GRUNDIG2_ADDRESS_LEN, // address_end: end of address\r
+ GRUNDIG2_COMMAND_OFFSET, // command_offset: command offset\r
+ GRUNDIG2_COMMAND_OFFSET + GRUNDIG2_COMMAND_LEN, // command_end: end of command\r
+ GRUNDIG2_COMPLETE_DATA_LEN, // complete_len: complete length of frame\r
+ GRUNDIG2_STOP_BIT, // stop_bit: flag: frame has stop bit\r
+ GRUNDIG2_LSB, // lsb_first: flag: LSB first\r
+ GRUNDIG2_FLAGS // flags: some flags\r
+};\r
+\r
+#endif\r
+\r
#if IRMP_SUPPORT_FDC_PROTOCOL == 1\r
\r
static const PROGMEM IRMP_PARAMETER fdc_param =\r
}\r
break;\r
#endif\r
+#if IRMP_SUPPORT_GRUNDIG2_PROTOCOL == 1\r
+ case IRMP_GRUNDIG2_PROTOCOL:\r
+ if (irmp_command & 0x0001)\r
+ {\r
+ irmp_command >>= 1;\r
+ rtc = TRUE;\r
+ }\r
+ break;\r
+#endif\r
#if IRMP_SUPPORT_KATHREIN_PROTOCOL == 1\r
case IRMP_KATHREIN_PROTOCOL:\r
if (irmp_command != 0x0000)\r
{\r
irmp_tmp_command |= (((uint16_t) (value)) << (irmp_bit - 8)); // store 4 system bits (genre 1) in upper nibble with LSB first\r
}\r
- else if (irmp_bit >= 24 && irmp_bit < 28)\r
+ else if (irmp_bit >= 24 && irmp_bit < 28)\r
{\r
genre2 |= (((uint8_t) (value)) << (irmp_bit - 20)); // store 4 system bits (genre 2) in upper nibble with LSB first\r
}\r
else\r
#endif // IRMP_SUPPORT_SIEMENS_OR_RUWIDO_PROTOCOL == 1\r
\r
+#if IRMP_SUPPORT_GRUNDIG2_PROTOCOL == 1\r
+ if ((irmp_pulse_time >= GRUNDIG2_START_BIT_PULSE_LEN_MIN && irmp_pulse_time <= GRUNDIG2_START_BIT_PULSE_LEN_MAX) &&\r
+ (irmp_pause_time >= GRUNDIG2_START_BIT_PAUSE_LEN_MIN && irmp_pause_time <= GRUNDIG2_START_BIT_PAUSE_LEN_MAX))\r
+ { // it's GRUNDIG2\r
+ ANALYZE_PRINTF ("protocol = GRUNDIG2, start bit timings: pulse: %3d - %3d or %3d - %3d, pause: %3d - %3d or %3d - %3d\n",\r
+ GRUNDIG2_START_BIT_PULSE_LEN_MIN, GRUNDIG2_START_BIT_PULSE_LEN_MAX,\r
+ 2 * GRUNDIG2_START_BIT_PULSE_LEN_MIN, 2 * GRUNDIG2_START_BIT_PULSE_LEN_MAX,\r
+ GRUNDIG2_START_BIT_PAUSE_LEN_MIN, GRUNDIG2_START_BIT_PAUSE_LEN_MAX,\r
+ 2 * GRUNDIG2_START_BIT_PAUSE_LEN_MIN, 2 * GRUNDIG2_START_BIT_PAUSE_LEN_MAX);\r
+ irmp_param_p = (IRMP_PARAMETER *) &grundig2_param;\r
+ last_pause = irmp_pause_time;\r
+ last_value = 1;\r
+ }\r
+ else\r
+#endif // IRMP_SUPPORT_SIEMENS_OR_RUWIDO_PROTOCOL == 1\r
+\r
#if IRMP_SUPPORT_FDC_PROTOCOL == 1\r
if (irmp_pulse_time >= FDC_START_BIT_PULSE_LEN_MIN && irmp_pulse_time <= FDC_START_BIT_PULSE_LEN_MAX &&\r
irmp_pause_time >= FDC_START_BIT_PAUSE_LEN_MIN && irmp_pause_time <= FDC_START_BIT_PAUSE_LEN_MAX)\r
irmp_ir_detected = FALSE;\r
}\r
\r
- irmp_flags |= genre2; // write the genre2 bits into MSB of the flag byte\r
+ irmp_flags |= genre2; // write the genre2 bits into MSB of the flag byte\r
}\r
#endif // IRMP_SUPPORT_KASEIKYO_PROTOCOL == 1\r
\r
2 * SIEMENS_OR_RUWIDO_BIT_PULSE_LEN_MIN, 2 * SIEMENS_OR_RUWIDO_BIT_PULSE_LEN_MAX,\r
2 * SIEMENS_OR_RUWIDO_BIT_PAUSE_LEN_MIN, 2 * SIEMENS_OR_RUWIDO_BIT_PAUSE_LEN_MAX);\r
\r
+ printf ("GRUNDIG2 1 %3d - %3d %3d - %3d %3d - %3d %3d - %3d %3d - %3d %3d - %3d\n",\r
+ GRUNDIG2_START_BIT_PULSE_LEN_MIN, GRUNDIG2_START_BIT_PULSE_LEN_MAX,\r
+ GRUNDIG2_START_BIT_PAUSE_LEN_MIN, GRUNDIG2_START_BIT_PAUSE_LEN_MAX,\r
+ GRUNDIG2_BIT_PULSE_LEN_MIN, GRUNDIG2_BIT_PULSE_LEN_MAX,\r
+ GRUNDIG2_BIT_PAUSE_LEN_MIN, GRUNDIG2_BIT_PAUSE_LEN_MAX,\r
+ 2 * GRUNDIG2_BIT_PULSE_LEN_MIN, 2 * GRUNDIG2_BIT_PULSE_LEN_MAX,\r
+ 2 * GRUNDIG2_BIT_PAUSE_LEN_MIN, 2 * GRUNDIG2_BIT_PAUSE_LEN_MAX);\r
+\r
printf ("FDC 1 %3d - %3d %3d - %3d %3d - %3d %3d - %3d %3d - %3d %3d - %3d\n",\r
FDC_START_BIT_PULSE_LEN_MIN, FDC_START_BIT_PULSE_LEN_MAX, FDC_START_BIT_PAUSE_LEN_MIN, FDC_START_BIT_PAUSE_LEN_MAX,\r
FDC_PULSE_LEN_MIN, FDC_PULSE_LEN_MAX, FDC_0_PAUSE_LEN_MIN, FDC_0_PAUSE_LEN_MAX,\r
*\r
* Copyright (c) 2009-2011 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irmp.h,v 1.68 2012/02/13 10:55:50 fm Exp $\r
+ * $Id: irmp.h,v 1.70 2012/02/21 08:41:46 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
#define IRMP_NEC42_PROTOCOL 28 // NEC with 42 bits\r
#define IRMP_LEGO_PROTOCOL 29 // LEGO Power Functions RC\r
#define IRMP_THOMSON_PROTOCOL 30 // Thomson\r
+#define IRMP_GRUNDIG2_PROTOCOL 31 // Grundig, e.g. TP400\r
\r
-#define IRMP_N_PROTOCOLS 30 // number of supported protocols\r
+#define IRMP_N_PROTOCOLS 31 // number of supported protocols\r
\r
// some flags of struct IRMP_PARAMETER:\r
#define IRMP_PARAM_FLAG_IS_MANCHESTER 0x01\r
#define SAMSUNG32_COMPLETE_DATA_LEN 32 // complete length\r
#define SAMSUNG32_FRAMES 1 // SAMSUNG32 sends each frame 1 times\r
#define SAMSUNG32_AUTO_REPETITION_PAUSE_TIME 47.0e-3 // repetition after 47 ms\r
-#define SAMSUNG32_FRAME_REPEAT_PAUSE_TIME 47.0e-3 // frame repeat after 40ms\r
+#define SAMSUNG32_FRAME_REPEAT_PAUSE_TIME 47.0e-3 // frame repeat after 47ms\r
\r
#define MATSUSHITA_START_BIT_PULSE_TIME 3488.0e-6 // 3488 usec pulse\r
#define MATSUSHITA_START_BIT_PAUSE_TIME 3488.0e-6 // 3488 usec pause\r
#define THOMSON_LSB 0 // MSB...LSB\r
#define THOMSON_FLAGS 0 // flags\r
\r
+#define GRUNDIG2_START_BIT_PULSE_TIME 550.0e-6 // 550 usec pulse\r
+#define GRUNDIG2_START_BIT_PAUSE_TIME 2700.0e-6 // 2700 usec pause\r
+#define GRUNDIG2_BIT_PULSE_TIME 550.0e-6 // 550 usec short pulse\r
+#define GRUNDIG2_BIT_PAUSE_TIME 550.0e-6 // 550 usec short pause\r
+#define GRUNDIG2_FRAME_REPEAT_PAUSE_TIME 100.0e-3 // frame repeat after 100ms\r
+#define GRUNDIG2_STOP_BIT 0 // has no stop bit\r
+#define GRUNDIG2_LSB 1 // MSB...LSB\r
+#define GRUNDIG2_FLAGS (IRMP_PARAM_FLAG_IS_MANCHESTER | IRMP_PARAM_FLAG_1ST_PULSE_IS_1) // flags\r
+#define GRUNDIG2_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define GRUNDIG2_ADDRESS_LEN 0 // read 0 bits\r
+#define GRUNDIG2_COMMAND_OFFSET 0 // skip 0 bits\r
+#define GRUNDIG2_COMMAND_LEN 7 // read 6 + 1 command bits, last bit is always 1\r
+#define GRUNDIG2_COMPLETE_DATA_LEN 7 // complete length\r
+\r
#define AUTO_FRAME_REPETITION_TIME 80.0e-3 // SIRCS/SAMSUNG32/NUBERT: automatic repetition after 25-50ms\r
// KASEIKYO: automatic repetition after 75ms\r
\r
*\r
* Copyright (c) 2010-2011 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: irsndconfig.h,v 1.27 2011/09/20 10:45:28 fm Exp $\r
+ * $Id: irsndconfig.h,v 1.29 2012/02/16 12:39:36 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
#define IRSND_PIC_CCP1 1 // PIC C18 RC2 = PWM1 module\r
#define IRSND_PIC_CCP2 2 // PIC C18 RC1 = PWM2 module\r
\r
-#ifndef PIC_C18 // AVR part\r
+#ifndef PIC_C18 // AVR part\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* AVR\r
* IRSND_OC0 = OC0 on ATmegas supporting OC0, e.g. ATmega162\r
* IRSND_OC0A = OC0A on ATmegas/ATtinys supporting OC0A, e.g. ATtiny84, ATtiny85\r
* IRSND_OC0B = OC0B on ATmegas/ATtinys supporting OC0B, e.g. ATtiny84, ATtiny85\r
- * IRSND_PIC_CCP1 = RC2 on PIC 18F2550/18F4550, ...\r
- * IRSND_PIC_CCP2 = RC1 on PIC 18F2550/18F4550, ...\r
+ * IRSND_PIC_CCP1 = RC2 on PIC 18F2550/18F4550, ...\r
+ * IRSND_PIC_CCP2 = RC1 on PIC 18F2550/18F4550, ...\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
\r
* PIC C18\r
*\r
* Change hardware pin here: IRSND_PIC_CCP1 = RC2 on PIC 18F2550/18F4550, ...\r
- * IRSND_PIC_CCP2 = RC1 on PIC 18F2550/18F4550, ...\r
+ * IRSND_PIC_CCP2 = RC1 on PIC 18F2550/18F4550, ...\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
\r
#else\r
-#define IRSND_OCx IRSND_PIC_CCP2 // Use PWMx for PIC\r
+#define IRSND_OCx IRSND_PIC_CCP2 // Use PWMx for PIC\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* PIC C18 - change other PIC specific settings - ignore it when using AVR\r
#if IRSND_OCx == IRSND_PIC_CCP2 \r
#define IRSND_PIN TRISCbits.TRISC1 // RC1 = PWM2\r
\r
-#define SetDCPWM(x) SetDCPWM2(x) \r
-#define ClosePWM ClosePWM2\r
-#define OpenPWM(x) OpenPWM2(x) \r
+#define SetDCPWM(x) SetDCPWM2(x) \r
+#define ClosePWM ClosePWM2\r
+#define OpenPWM(x) OpenPWM2(x) \r
#endif\r
\r
#if IRSND_OCx == IRSND_PIC_CCP1 \r