[z180-stamp-cpm3.git] / cbios / ascii.180

\r
; Interrupt drivers for ASCI0 and ASCI1\r
\r
	global	as0_dev,as1_dev\r
\r
	extrn	@ctbl,f_cpu\r
	extrn	ff_empty,ff_get,ff_full,ff_put\r
	extrn	ff_puth,ff_cnt,ff_gech\r
	extrn	bufinit\r
	extrn	isv_sw,ijphl,add_hla,div32_r\r
	extrn	b_st_a,b_ld_a\r
\r
\r
\r
	maclib z180reg.inc\r
	maclib config.inc\r
	maclib ioctl.inc\r
	maclib modebaud.inc\r
\r
\r
	m2b	mbxon_bit,mb$xon$xoff\r
\r
;-----------------------------------------------------\r
\r
	dseg\r
\r
	dw	asci0_out\r
	dw	asci0_osta\r
	dw	asci0_inp\r
	dw	asci0_ista\r
	dw	asci_ioctl\r
as0_dev:\r
	db	0			;absolute device #\r
	db	0			;relative device\r
	db	0			;iflags\r
	db	M_CREAD+M_CRTS_IFLOW+M_CCTS_OFLOW	;fflags\r
	db	M_CS8			;cflags\r
o.absdev	equ	0\r
o.reldev	equ	1\r
o.iflags	equ	2\r
o.fflags	equ	3\r
o.cflags	equ	4\r
\r
	db	0\r
o.stat		equ	5\r
	b2m	SXOFF,0\r
	b2m	TDC1,1\r
	b2m	TDC3,2\r
	db	0\r
oint.iflags	equ	as0_dev+o.iflags-s0.inbuf\r
oint.fflags	equ	as0_dev+o.fflags-s0.inbuf\r
oint.stat	equ	as0_dev+o.stat-s0.inbuf\r
	mkbuf	s0.rx_id, s0.inbuf, s0.rx_len\r
	mkbuf	s0.tx_id, s0.outbuf,s0.tx_len\r
\r
\r
	dw	asci1_out\r
	dw	asci1_osta\r
	dw	asci1_inp\r
	dw	asci1_ista\r
	dw	asci_ioctl\r
as1_dev:\r
	db	0			;absolute device #\r
	db	1			;relative device\r
	db	0			;iflags\r
	db	M_CREAD+M_IXOFF		;fflags\r
	db	M_CS8			;cflags\r
\r
	db	0\r
	db	0\r
	mkbuf	s1.rx_id, s1.inbuf, s1.rx_len\r
	mkbuf	s1.tx_id, s1.outbuf,s1.tx_len\r
\r
\r
\r
	dseg\r
\r
\r
ioctl_ftab:\r
	dw	func_tcinit		;(00h) CP/M 3 DEVINI function\r
	dw	func_tcgeta		;(01h) Get the current serial port settings.\r
	dw	func_tcseta		;(02h) Set the current serial port settings.\r
	dw	func_tcsetaw		;(03h) Allow the output buffer to drain\r
	dw	func_tcsetaf		;(04h) Allow the output buffer to drain, discard pending input\r
	dw	func_tcsbrk		;(05h) Sending a break (250ms .. 500ms)\r
	dw	func_tcsbrkp		;(06h) arg is timeinterval in 0.1sec\r
	dw	func_tiocsbrk		;(07h) Turn break on\r
	dw	func_tioccbrk		;(08h) Turn break off\r
	dw	func_tcxonc		;(09h) Software flow control (TCOOFF, TCOON, TCIOFF, TCION)\r
	dw	func_tcflsh		;(0Ah) Flush input/output buffer (TCIFLUSH, TCOFLUSH, TCIOFLUSH)\r
	dw	func_fionread		;(0Bh) Get the number of bytes in the input buffer.\r
	dw	func_tiocoutq		;(0Ch) Get the number of bytes in the output buffer.\r
	dw	func_tiocmget		;(0Dh) get the status of modem bits.\r
	dw	func_tiocmbis		;(0Eh) set the indicated modem bits.\r
	dw	func_tiocmbic		;(0Fh) clear the indicated modem bits.\r
	dw	func_tiocmset		;(10h) set the status of modem bits.\r
	dw	func_tiocgsoftcar	;(11h) Get the status of the CLOCAL flag in the c_cflag field\r
	dw	func_tiocssoftcar	;(12h) Set the CLOCAL flag when  *argp  is nonzero, and clear it otherwise.\r
\r
IOCTL_MAX equ	($-ioctl_ftab)/2\r
	dw	nofunc\r
\r
\r
;--------------------------------------------------------------\r
;\r
; b:  device number\r
; c:  command\r
; de: ioctl arg pointer\r
; hl: ptr to driver local data\r
;\r
\r
asci_ioctl:\r
	ld	a,b\r
	cp	1\r
	jr	nz,asioc_1\r
	ld	a,(inidone)\r
	cp	inidoneval\r
	ret	z\r
asioc_1:\r
	push	hl\r
	ex	(sp),ix\r
	ld	(ix+o.absdev),b\r
	ld	hl,ioctl_ftab\r
	ld	a,IOCTL_MAX\r
	cp	c\r
	jr	c,$+3\r
	 ld	a,c\r
	add	a,a\r
	call	add_hla\r
	ld	a,(hl)\r
	inc	hl\r
	ld	h,(hl)\r
	ld	l,a\r
	call	ijphl\r
	pop	ix\r
nofunc:\r
	or	a\r
	ret\r
\r
;--------------------------------------------------------------\r
; CP/M 3 DEVINI function\r
; Init Serial I/O for input and output (ASCI 0/1)\r
\r
func_tcinit:\r
	call	asci_stop\r
\r
init_st:\r
	ld	c,asext0		;Enable baud rate generator\r
	ld	a,M_BRGMOD+M_DCD0DIS 	; +M_CTS0DIS +M_BREAKEN\r
	bit	CCTS_OFLOW,(ix+o.fflags)\r
	jr	nz,$+4\r
	 or	M_CTS0DIS\r
	call	out_asci_reg\r
\r
	ld	b,(ix+o.absdev)\r
	ld	c,8			;\r
	mlt	bc			;\r
	ld	hl,@ctbl+7		;\r
	add	hl,bc			;\r
	ld	a,(hl)			;get baudrate index\r
	call	as_br_div\r
	ld	c,astc0l\r
	call	out_asci_reg_hl\r
\r
	ld	c,cntlb0\r
	ld	a,M_MPBT		;No MP Mode, X16\r
	bit	PARODD,(ix+o.iflags)\r
	jr	z,$+4\r
	 or	M_PEO\r
	call	out_asci_reg\r
\r
	ld	c,cntla0\r
	ld	a,(ix+o.cflags)\r
	srlan	CS8\r
	ld	hl,mod_tab\r
	call	add_hla\r
	ld	a,(hl)\r
	or	a,M_RE+M_TE+M_RTS0+M_EFR ;Rx/Tx enable\r
	call	out_asci_reg\r
\r
	bit	0,(ix+o.reldev)\r
	push	ix\r
	jr	nz,init_1\r
	ld	hl,rtxisvjmp0		;rx/tx int vector\r
	ld	(ivtab + IV$ASCI0),hl	;\r
	ld	ix,s0.outbuf\r
	call	bufinit\r
	ld	ix,s0.inbuf\r
	jr	init_2\r
init_1:\r
	ld	hl,rtxisvjmp1		;rx/tx int vector\r
	ld	(ivtab + IV$ASCI1),hl	;\r
	ld	ix,s1.outbuf\r
	call	bufinit\r
	ld	ix,s1.inbuf\r
init_2:\r
	call	bufinit\r
	pop	ix\r
	call	asci_start\r
	ret\r
\r
;--------------------------------------------------------------\r
\r
mod_tab:\r
	db	000B			; 7N1\r
	db	100B			; 8N1\r
	db	001B			; 7N2\r
	db	101B			; 8N2\r
	db	010B			; 7P1\r
	db	110B			; 8P1\r
	db	011B			; 7P2\r
	db	111B			; 8P2\r
\r
\r
;--------------------------------------------------------------\r
; Get the current serial port settings.\r
\r
func_tcgeta:\r
	call	chk_ptr\r
\r
	ld	a,(ix+o.iflags)\r
	call	b_st_a\r
	inc	de\r
	ld	a,(ix+o.fflags)\r
	call	b_st_a\r
	inc	de\r
\r
	ld	b,(ix+o.absdev)\r
	ld	c,8			;\r
	mlt	bc			;\r
	ld	hl,@ctbl+7		;\r
	add	hl,bc			;\r
	ld	a,(hl)			;get baudrate index\r
	and	M_CBAUD\r
	ld	b,a\r
	ld	a,(ix+o.cflags)\r
	and	~M_CBAUD\r
	or	b\r
	call	b_st_a\r
	dec	de\r
	dec	de\r
	xor	a\r
	ret\r
\r
;--------------------------------------------------------------\r
; Set the current serial port settings.\r
\r
func_tcseta:\r
	call	chk_ptr\r
\r
	call	asci_stop\r
\r
	call	b_ld_a\r
	ld	(ix+o.iflags),a\r
	inc	de\r
	call	b_ld_a\r
	ld	(ix+o.fflags),a\r
	inc	de\r
\r
	ld	b,(ix+o.absdev)\r
	ld	c,8			;\r
	mlt	bc			;\r
	ld	hl,@ctbl+7		;\r
	add	hl,bc			;\r
	call	b_ld_a\r
	ld	(ix+o.cflags),a\r
	and	M_CBAUD\r
	ld	(hl),a			;set baudrate index\r
	dec	de\r
	dec	de\r
	push	de\r
	call	init_st\r
	pop	de\r
	xor	a\r
	ret\r
\r
;--------------------------------------------------------------\r
; Allow the output buffer to drain\r
\r
func_tcsetaw:\r
\r
;--------------------------------------------------------------\r
; Allow the output buffer to drain, discard pending input\r
\r
func_tcsetaf:\r
\r
;--------------------------------------------------------------\r
; Sending a break (250ms .. 500ms)\r
\r
func_tcsbrk:\r
\r
;--------------------------------------------------------------\r
; arg is timeinterval in 0.1sec\r
\r
func_tcsbrkp:\r
\r
;--------------------------------------------------------------\r
; Turn break on\r
\r
func_tiocsbrk:\r
\r
;--------------------------------------------------------------\r
; Turn break off\r
\r
func_tioccbrk:\r
\r
;--------------------------------------------------------------\r
; Software flow control (TCOOFF, TCOON, TCIOFF, TCION)\r
\r
func_tcxonc:\r
\r
;--------------------------------------------------------------\r
; Flush input/output buffer (TCIFLUSH, TCOFLUSH, TCIOFLUSH)\r
\r
func_tcflsh:\r
\r
;--------------------------------------------------------------\r
; Get the number of bytes in the input buffer.\r
\r
func_fionread:\r
\r
;--------------------------------------------------------------\r
; Get the number of bytes in the output buffer.\r
\r
func_tiocoutq:\r
\r
;--------------------------------------------------------------\r
; get the status of modem bits.\r
\r
func_tiocmget:\r
\r
;--------------------------------------------------------------\r
; set the indicated modem bits.\r
\r
func_tiocmbis:\r
\r
;--------------------------------------------------------------\r
; clear the indicated modem bits.\r
\r
func_tiocmbic:\r
\r
;--------------------------------------------------------------\r
; set the status of modem bits.\r
\r
func_tiocmset:\r
\r
;--------------------------------------------------------------\r
; Get the status of the CLOCAL flag in the c_cflag field\r
\r
func_tiocgsoftcar:\r
\r
;--------------------------------------------------------------\r
; Set the CLOCAL flag when  *argp  is nonzero, and clear it otherwise.\r
\r
func_tiocssoftcar:\r
\r
	or	0ffh\r
	ret\r
\r
;--------------------------------------------------------------\r
\r
chk_ptr:\r
	ld	a,e\r
	or	d\r
	ret	nz\r
	cpl\r
	pop	hl\r
	ret\r
\r
;--------------------------------------------------------------\r
\r
asci_stop:\r
	ld	c,stat0			;Disable rx/tx interrupts\r
	xor	a			;\r
	call	out_asci_reg\r
\r
	ld	c,cntla0		;Disable receiver and transmitter\r
	ld	a,M_RTS0+M_EFR		;RTS/CKA1\r
	jr	out_asci_reg\r
\r
;--------------------------------------------------------------\r
\r
asci_start:\r
	bit	0,(ix+o.reldev)\r
	jr	nz,asci_st1\r
	in0	a,cntla0		;asci0\r
	and	~M_RTS0			;Activate RTS\r
	or	M_EFR\r
	out0	(cntla0),a\r
asci_st1:\r
	ld	c,stat0			;\r
	ld	a,M_RIE\r
	jr	out_asci_reg\r
\r
;--------------------------------------------------------------\r
; output to asci0/1 register\r
;\r
; c:  register address\r
; a:  value\r
;\r
\r
out_asci_reg:\r
	push	bc\r
	bit	0,(ix+o.reldev)\r
	jr	z,$+3\r
	 inc	c\r
	ld	b,0\r
	out	(c),a\r
	pop	bc\r
	ret\r
\r
;--------------------------------------------------------------\r
; output 16 bit value to asci0/1 register\r
;\r
; c:   register address\r
; hl:  value\r
; a destroyed\r
\r
out_asci_reg_hl:\r
	ld	a,b			;save b\r
	bit	0,(ix+o.reldev)\r
	jr	z,$+4\r
	 inc	c\r
	 inc	c\r
	ld	b,0\r
	out	(c),l\r
	inc	c\r
	out	(c),h\r
	ld	b,a\r
	ret\r
\r
;--------------------------------------------------------------\r
; baud rate divider\r
;\r
;   a: index\r
; return\r
;   hl: divider\r
\r
as_br_div:\r
	push	de\r
	push	bc\r
	and	0fh\r
	add	a,a			;get factor\r
	ld	hl,bd150_tab\r
	call	add_hla\r
	ld	c,(hl)\r
	inc	hl\r
	ld	b,(hl)\r
	ld	hl,(f_cpu)\r
	ld	de,(f_cpu+2)\r
	call	div32_r\r
	ld	bc,32*150\r
	call	div32_r\r
	ld	de,2\r
	or	a\r
	sbc	hl,de\r
	pop	bc\r
	pop	de\r
	ret	nc\r
	ld	hl,0\r
	ret\r
\r
bd150_tab:\r
;		factor		index   baudrate	orig. cp/m\r
	dw	19200/150	; 0	19200		-\r
	dw	28800/150	; 1	28800		50\r
	dw	38400/150	; 2	38400		75\r
	dw	57600/150	; 3	57600		110\r
	dw	11520/15	; 4	115200		134.5\r
	dw	150/150		; 5	150\r
	dw	300/150		; 6	300\r
	dw	600/150		; 7	600\r
	dw	1200/150	; 8	1200\r
	dw	1800/150	; 9	1800\r
	dw	2400/150	;10	2400\r
	dw	3600/150	;11	3600\r
	dw	4800/150	;12	4800\r
	dw	7200/150	;13	7200\r
	dw	9600/150	;14	9600\r
	dw	19200/150	;15	19200\r
\r
\r
;--------------------------------------------------------------\r
\r
   if 0\r
\r
initab0:\r
	db	1,stat0,0		;Disable rx/tx interrupts\r
					;Enable baud rate generator\r
	db	1,asext0,M_BRGMOD+M_DCD0DIS ; +M_CTS0DIS\r
	db	2,astc0l\r
init_br_off equ $ - initab0\r
	dw	28\r
	db	1,cntlb0,M_MPBT		;No MP Mode, X16\r
	db	1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
	db	0\r
\r
initab1:\r
	db	1,stat1,0		;Disable rx/tx ints, disable CTS1\r
	db	1,asext1,M_BRGMOD	;Enable baud rate generator\r
	db	2,astc1l,low 3, high 3\r
	db	1,cntlb1,M_MPBT		;No MP Mode, X16\r
	db	1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
	db	0\r
   endif\r
\r
;--------------------------------------------------------------\r
\r
	dseg\r
asci0_ista:\r
	push	ix\r
	ld	ix,s0.inbuf		;\r
	call	ff_empty\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
\r
asci1_ista:\r
	push	ix\r
	ld	ix,s1.inbuf		;\r
	call	ff_empty\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; Get an input character\r
\r
if 0\r
asci0_inp:\r
	push	ix\r
	ld	ix,s0.inbuf		;\r
	call	ff_cnt\r
	cp	32\r
	jr	nc,a0i_1\r
	di\r
	in0	a,(cntla0)\r
	res	RTS0,a\r
	set	EFR,a\r
	out0	(cntla0),a\r
	ei\r
a0i_1:\r
	call	ff_get\r
	pop	ix\r
	ret\r
endif\r
\r
\r
asci0_inp:\r
	push	ix\r
	ld	ix,s0.inbuf		;\r
	call	ff_gech\r
	ld	a,b			;remaining chrs in buffer\r
	cp	s0.rx_len/4		; < 32?\r
	jr	nc,a0i_2			; no, just get char\r
	ld	b,(ix+oint.fflags)	; yes, enable RTS if needed\r
	bit	CRTS_IFLOW,b		; yes, enable RTS if needed\r
	jr	z,a0i_1			; no needed\r
	di				; needed, enable\r
	in0	a,(cntla0)\r
	and	~M_RTS0			;assert RTS\r
	or	M_EFR			;don't reset error flags\r
	ei\r
	out0	(cntla0),a\r
a0i_1:\r
	bit	IXOFF,b			; XON/XOFF on input?\r
	jr	z,a0i_2			; no\r
	di\r
	set	TDC1,(ix+oint.stat)	;\r
	in0	a,(stat0)		;\r
	or	M_TIE			;\r
	ei\r
	out0	(stat0),a		;\r
a0i_2:\r
	ld	a,c\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; Get an input character\r
\r
asci1_inp:\r
	push	ix\r
	ld	ix,s1.inbuf		;\r
	call	ff_gech\r
	ld	a,b			; remaining chars in buffer\r
	cp	s0.rx_len/4		; == 25% full?\r
	jr	nz,a1i_2		; no, just get char\r
	bit	IXOFF,(ix+oint.fflags)	; XON/XOFF on input?\r
	jr	z,a1i_2			; no\r
	di\r
	set	TDC1,(ix+oint.stat)	;\r
	in0	a,(stat1)		;\r
	or	M_TIE,			;\r
	out0	(stat1),a		;\r
	ei\r
a1i_2:\r
	ld	a,c			; get back the char\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; Output status\r
\r
asci0_osta:\r
	push	ix\r
	ld	ix,s0.outbuf		;\r
	call	ff_full\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; Output status\r
\r
asci1_osta:\r
	push	ix\r
	ld	ix,s1.outbuf		;\r
	call	ff_full\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; put character in c in buffer\r
; destroys hl, bc\r
; returns output char in a\r
\r
asci0_out:\r
	push	ix			;\r
	ld	ix,s0.outbuf		;\r
	call	ff_puth\r
	pop	ix			;\r
	di				;\r
	in0	c,(stat0)		;\r
	set	TIE,c			;\r
	out0	(stat0),c		;\r
	ei				;\r
	ret\r
\r
;--------------------------------------------------------------\r
; put character in c in buffer\r
; destroys hl, bc\r
; returns output char in a\r
\r
asci1_out:\r
	push	ix			;\r
	ld	ix,s1.outbuf		;\r
	call	ff_puth\r
	pop	ix			;\r
	di				;\r
	in0	c,(stat1)		;\r
	set	TIE,c			;\r
	out0	(stat1),c		;\r
	ei				;\r
	ret\r
\r
\r
;--------------------------------------------------------------\r
\r
	cseg\r
rtxisvjmp0:\r
	call	isv_sw\r
	dw	asci0_int\r
\r
rtxisvjmp1:\r
	call	isv_sw\r
	dw	asci1_int\r
\r
;--------------------------------------------------------------\r
; ASCI 0/1 Transmit/Receive interupt routines\r
\r
	.lall\r
asci_int macro	dev\r
	local	rxi_2,rxi_3\r
\r
	push	ix\r
rxtxi&dev&_lp0:\r
	ld	ix,s&dev&.inbuf		;\r
rxtxi&dev&_lp1:\r
	in0	a,(stat&dev)		;receive flag set?\r
	jp	p,txi&dev		;RDRF == Bit 7\r
	and	M_OVRN+M_PERR+M_FE\r
	ld	e,a\r
\r
	in0	a,(asext&dev)\r
	and	M_BREAK\r
	or	e\r
	ld	e,a\r
\r
	in0	d,(cntla&dev)		;\r
	res	EFR,d			;\r
	out0	(cntla&dev),d\r
\r
	ld	c,(ix+o.in_idx)		;input buffer pointer\r
	ld	b,0\r
	ld	hl,s&dev&.inbuf		;\r
	add	hl,bc\r
\r
	in0	a,(rdr&dev)		;get char\r
	ld	(hl),a\r
					;todo: break detection\r
					;todo: parity, framing overrun error\r
\r
	ld	e,(ix+oint.fflags)\r
;	bit	IXON,e\r
;	jr	z,rxi_2\r
					;todo: test XON/XOFF\r
rxi_2:\r
\r
	ld	a,c			;increment buffer in pointer\r
	inc	a			;\r
	ld	b,(ix+o.mask)		;\r
	and	b			;\r
	ld	c,a\r
\r
	sub	(ix+o.out_idx)		;\r
	jr	z,rxtxi&dev&_lp1	;skip if buffer is full\r
\r
	ld	(ix+o.in_idx),c		;input buffer pointer\r
\r
	jr	nc,$+3			;\r
	 adc	b			;\r
\r
	cp	s&dev&.tx_len*3/4\r
	jr	nz,rxtxi&dev&_lp1\r
\r
   if dev=0				; only channel 0 has rts line\r
	bit	CRTS_IFLOW,e\r
	jr	z,rxi0_nocrts\r
\r
	set	EFR,d\r
	set	RTS0,d			;RTS inactive\r
	out0	(cntla0),d		;\r
rxi0_nocrts:\r
   endif\r
\r
	bit	IXOFF,e\r
	jr	z,rxtxi&dev&_lp1\r
					;send XOFF\r
	set	TDC3,(ix+oint.stat)\r
	in0	a,(stat&dev)		;\r
	set	TIE,a			;\r
	out0	(stat&dev),a		;\r
	jr	rxtxi&dev&_lp1\r
\r
txi&dev:\r
	ld	e,a\r
	bit	TDRE,e			;TX int?\r
	jr	z,rxtxi&dev&_exit\r
					;todo: xon/xoff\r
	bit	IXOFF,(ix+oint.fflags)\r
	jr	z,txi&dev&_char\r
txi&dev&_dc1:\r
	bit	TDC1,(ix+oint.stat)\r
	jr	z,txi&dev&_dc3\r
	res	TDC1,(ix+oint.stat)\r
	ld	a,DC1\r
	jr	txi&dev&_dc1dc3\r
\r
txi&dev&_dc3:\r
	bit	TDC3,(ix+oint.stat)\r
	jr	z,txi&dev&_char\r
	res	TDC3,(ix+oint.stat)\r
	ld	a,DC3\r
txi&dev&_dc1dc3:\r
	out0	(tdr&dev),a		;\r
	jp	rxtxi&dev&_lp0\r
\r
txi&dev&_char:\r
	ld	hl,s&dev&.outbuf+o.in_idx	;[in]\r
	ld	a,(hl)			;\r
	inc	hl			;[out]\r
	ld	c,(hl)			;\r
	cp	c			;\r
	jr	z,txi&dev&_empty	;\r
	inc	hl			;fifo base\r
	ld	b,0			;\r
	add	hl,bc			;\r
	ld	a,(hl)			;\r
	out0	(tdr&dev),a		;\r
	inc	c			;\r
	ld	a,(s&dev&.outbuf+o.mask)	;\r
	and	c			;\r
	ld	(s&dev&.outbuf+o.out_idx),a	;\r
\r
	jp	rxtxi&dev&_lp0\r
\r
txi&dev&_empty:\r
	res	TIE,e			;disable tx-int\r
	out0	(stat&dev),e		;			5\r
\r
rxtxi&dev&_exit:\r
	pop	ix\r
	ret\r
	endm\r
\r
	dseg\r
;--------------------------------------------------------------\r
; ASCI 0 Transmit/Receive interupt routines\r
\r
asci0_int:\r
	asci_int 0\r
\r
;--------------------------------------------------------------\r
; ASCI 1 Transmit/Receive interupt routines\r
\r
asci1_int:\r
	asci_int 1\r
\r
	end\r
Commit	Line	Data
d6829fd3 L	1	\r
	2	; Interrupt drivers for ASCI0 and ASCI1\r
	3	\r
6dd88c25	4	global as0_dev,as1_dev\r
d6829fd3	5	\r
1c7e3963	6	extrn @ctbl,f_cpu\r
81ba3c84 L	7	extrn ff_empty,ff_get,ff_full,ff_put\r
81ba3c84 L	8	extrn ff_puth,ff_cnt,ff_gech\r
d6829fd3	9	extrn bufinit\r
1c7e3963 L	10	extrn isv_sw,ijphl,add_hla,div32_r\r
1c7e3963 L	11	extrn b_st_a,b_ld_a\r
d6829fd3 L	12	\r
	13	\r
	14	\r
1c7e3963 L	15	maclib z180reg.inc\r
	16	maclib config.inc\r
	17	maclib ioctl.inc\r
	18	maclib modebaud.inc\r
d6829fd3 L	19	\r
d6829fd3 L	20	\r
1c7e3963	21	m2b mbxon_bit,mb$xon$xoff\r
d6829fd3 L	22	\r
	23	;-----------------------------------------------------\r
	24	\r
	25	dseg\r
	26	\r
6dd88c25 L	27	dw asci0_out\r
	28	dw asci0_osta\r
	29	dw asci0_inp\r
	30	dw asci0_ista\r
	31	dw asci_ioctl\r
	32	as0_dev:\r
1c7e3963 L	33	db 0 ;absolute device #\r
	34	db 0 ;relative device\r
	35	db 0 ;iflags\r
99b8d89e	36	db M_CREAD+M_CRTS_IFLOW+M_CCTS_OFLOW ;fflags\r
1c7e3963	37	db M_CS8 ;cflags\r
6dd88c25 L	38	o.absdev equ 0\r
6dd88c25 L	39	o.reldev equ 1\r
1c7e3963 L	40	o.iflags equ 2\r
	41	o.fflags equ 3\r
	42	o.cflags equ 4\r
	43	\r
	44	db 0\r
6d39b0ff L	45	o.stat equ 5\r
	46	b2m SXOFF,0\r
	47	b2m TDC1,1\r
	48	b2m TDC3,2\r
1c7e3963 L	49	db 0\r
	50	oint.iflags equ as0_dev+o.iflags-s0.inbuf\r
	51	oint.fflags equ as0_dev+o.fflags-s0.inbuf\r
6d39b0ff	52	oint.stat equ as0_dev+o.stat-s0.inbuf\r
1c7e3963 L	53	mkbuf s0.rx_id, s0.inbuf, s0.rx_len\r
	54	mkbuf s0.tx_id, s0.outbuf,s0.tx_len\r
	55	\r
6dd88c25 L	56	\r
	57	dw asci1_out\r
	58	dw asci1_osta\r
	59	dw asci1_inp\r
	60	dw asci1_ista\r
	61	dw asci_ioctl\r
	62	as1_dev:\r
1c7e3963 L	63	db 0 ;absolute device #\r
	64	db 1 ;relative device\r
	65	db 0 ;iflags\r
3134af6c	66	db M_CREAD+M_IXOFF ;fflags\r
1c7e3963	67	db M_CS8 ;cflags\r
6dd88c25	68	\r
6dd88c25	69	db 0\r
6dd88c25	70	db 0\r
d6829fd3	71	mkbuf s1.rx_id, s1.inbuf, s1.rx_len\r
81ba3c84	72	mkbuf s1.tx_id, s1.outbuf,s1.tx_len\r
d6829fd3 L	73	\r
	74	\r
	75	\r
	76	dseg\r
	77	\r
6dd88c25 L	78	\r
6dd88c25 L	79	ioctl_ftab:\r
1c7e3963 L	80	dw func_tcinit ;(00h) CP/M 3 DEVINI function\r
	81	dw func_tcgeta ;(01h) Get the current serial port settings.\r
	82	dw func_tcseta ;(02h) Set the current serial port settings.\r
	83	dw func_tcsetaw ;(03h) Allow the output buffer to drain\r
	84	dw func_tcsetaf ;(04h) Allow the output buffer to drain, discard pending input\r
	85	dw func_tcsbrk ;(05h) Sending a break (250ms .. 500ms)\r
	86	dw func_tcsbrkp ;(06h) arg is timeinterval in 0.1sec\r
	87	dw func_tiocsbrk ;(07h) Turn break on\r
	88	dw func_tioccbrk ;(08h) Turn break off\r
	89	dw func_tcxonc ;(09h) Software flow control (TCOOFF, TCOON, TCIOFF, TCION)\r
	90	dw func_tcflsh ;(0Ah) Flush input/output buffer (TCIFLUSH, TCOFLUSH, TCIOFLUSH)\r
	91	dw func_fionread ;(0Bh) Get the number of bytes in the input buffer.\r
	92	dw func_tiocoutq ;(0Ch) Get the number of bytes in the output buffer.\r
	93	dw func_tiocmget ;(0Dh) get the status of modem bits.\r
	94	dw func_tiocmbis ;(0Eh) set the indicated modem bits.\r
	95	dw func_tiocmbic ;(0Fh) clear the indicated modem bits.\r
	96	dw func_tiocmset ;(10h) set the status of modem bits.\r
	97	dw func_tiocgsoftcar ;(11h) Get the status of the CLOCAL flag in the c_cflag field\r
	98	dw func_tiocssoftcar ;(12h) Set the CLOCAL flag when *argp is nonzero, and clear it otherwise.\r
	99	\r
6dd88c25 L	100	IOCTL_MAX equ ($-ioctl_ftab)/2\r
	101	dw nofunc\r
	102	\r
1c7e3963	103	\r
d6829fd3	104	;--------------------------------------------------------------\r
d6829fd3	105	;\r
6dd88c25 L	106	; b: device number\r
	107	; c: command\r
	108	; de: ioctl arg pointer\r
	109	; hl: ptr to driver local data\r
d6829fd3 L	110	;\r
d6829fd3 L	111	\r
6dd88c25	112	asci_ioctl:\r
72ba3737 L	113	ld a,b\r
	114	cp 1\r
	115	jr nz,asioc_1\r
3134af6c L	116	ld a,(inidone)\r
3134af6c L	117	cp inidoneval\r
72ba3737 L	118	ret z\r
72ba3737 L	119	asioc_1:\r
6dd88c25 L	120	push hl\r
	121	ex (sp),ix\r
	122	ld (ix+o.absdev),b\r
	123	ld hl,ioctl_ftab\r
	124	ld a,IOCTL_MAX\r
	125	cp c\r
	126	jr c,$+3\r
	127	ld a,c\r
	128	add a,a\r
	129	call add_hla\r
	130	ld a,(hl)\r
	131	inc hl\r
	132	ld h,(hl)\r
	133	ld l,a\r
	134	call ijphl\r
	135	pop ix\r
	136	nofunc:\r
1c7e3963	137	or a\r
6dd88c25 L	138	ret\r
6dd88c25 L	139	\r
6dd88c25	140	;--------------------------------------------------------------\r
1c7e3963	141	; CP/M 3 DEVINI function\r
6dd88c25	142	; Init Serial I/O for input and output (ASCI 0/1)\r
d6829fd3	143	\r
1c7e3963 L	144	func_tcinit:\r
	145	call asci_stop\r
	146	\r
	147	init_st:\r
	148	ld c,asext0 ;Enable baud rate generator\r
	149	ld a,M_BRGMOD+M_DCD0DIS ; +M_CTS0DIS +M_BREAKEN\r
	150	bit CCTS_OFLOW,(ix+o.fflags)\r
	151	jr nz,$+4\r
	152	or M_CTS0DIS\r
	153	call out_asci_reg\r
d6829fd3	154	\r
6dd88c25	155	ld b,(ix+o.absdev)\r
1c7e3963 L	156	ld c,8 ;\r
	157	mlt bc ;\r
	158	ld hl,@ctbl+7 ;\r
	159	add hl,bc ;\r
	160	ld a,(hl) ;get baudrate index\r
	161	call as_br_div\r
	162	ld c,astc0l\r
99b8d89e	163	call out_asci_reg_hl\r
1c7e3963 L	164	\r
	165	ld c,cntlb0\r
	166	ld a,M_MPBT ;No MP Mode, X16\r
	167	bit PARODD,(ix+o.iflags)\r
	168	jr z,$+4\r
	169	or M_PEO\r
	170	call out_asci_reg\r
	171	\r
	172	ld c,cntla0\r
	173	ld a,(ix+o.cflags)\r
	174	srlan CS8\r
	175	ld hl,mod_tab\r
	176	call add_hla\r
	177	ld a,(hl)\r
	178	or a,M_RE+M_TE+M_RTS0+M_EFR ;Rx/Tx enable\r
	179	call out_asci_reg\r
	180	\r
6dd88c25	181	bit 0,(ix+o.reldev)\r
2f8aa307	182	push ix\r
6dd88c25 L	183	jr nz,init_1\r
	184	ld hl,rtxisvjmp0 ;rx/tx int vector\r
	185	ld (ivtab + IV$ASCI0),hl ;\r
d6829fd3	186	ld ix,s0.outbuf\r
1c7e3963 L	187	call bufinit\r
1c7e3963 L	188	ld ix,s0.inbuf\r
6dd88c25 L	189	jr init_2\r
	190	init_1:\r
	191	ld hl,rtxisvjmp1 ;rx/tx int vector\r
	192	ld (ivtab + IV$ASCI1),hl ;\r
d6829fd3	193	ld ix,s1.outbuf\r
1c7e3963 L	194	call bufinit\r
1c7e3963 L	195	ld ix,s1.inbuf\r
6dd88c25	196	init_2:\r
d6829fd3	197	call bufinit\r
1c7e3963 L	198	pop ix\r
	199	call asci_start\r
	200	ret\r
	201	\r
	202	;--------------------------------------------------------------\r
	203	\r
	204	mod_tab:\r
	205	db 000B ; 7N1\r
	206	db 100B ; 8N1\r
	207	db 001B ; 7N2\r
	208	db 101B ; 8N2\r
	209	db 010B ; 7P1\r
	210	db 110B ; 8P1\r
	211	db 011B ; 7P2\r
	212	db 111B ; 8P2\r
	213	\r
	214	\r
	215	;--------------------------------------------------------------\r
	216	; Get the current serial port settings.\r
	217	\r
	218	func_tcgeta:\r
99b8d89e	219	call chk_ptr\r
1c7e3963 L	220	\r
	221	ld a,(ix+o.iflags)\r
	222	call b_st_a\r
	223	inc de\r
	224	ld a,(ix+o.fflags)\r
	225	call b_st_a\r
	226	inc de\r
	227	\r
	228	ld b,(ix+o.absdev)\r
	229	ld c,8 ;\r
	230	mlt bc ;\r
	231	ld hl,@ctbl+7 ;\r
	232	add hl,bc ;\r
	233	ld a,(hl) ;get baudrate index\r
	234	and M_CBAUD\r
	235	ld b,a\r
	236	ld a,(ix+o.cflags)\r
	237	and ~M_CBAUD\r
	238	or b\r
	239	call b_st_a\r
	240	dec de\r
	241	dec de\r
	242	xor a\r
1c7e3963 L	243	ret\r
1c7e3963 L	244	\r
1c7e3963 L	245	;--------------------------------------------------------------\r
	246	; Set the current serial port settings.\r
	247	\r
	248	func_tcseta:\r
99b8d89e	249	call chk_ptr\r
1c7e3963 L	250	\r
	251	call asci_stop\r
	252	\r
	253	call b_ld_a\r
	254	ld (ix+o.iflags),a\r
	255	inc de\r
	256	call b_ld_a\r
	257	ld (ix+o.fflags),a\r
	258	inc de\r
	259	\r
	260	ld b,(ix+o.absdev)\r
	261	ld c,8 ;\r
	262	mlt bc ;\r
	263	ld hl,@ctbl+7 ;\r
	264	add hl,bc ;\r
	265	call b_ld_a\r
	266	ld (ix+o.cflags),a\r
	267	and M_CBAUD\r
	268	ld (hl),a ;set baudrate index\r
	269	dec de\r
	270	dec de\r
	271	push de\r
	272	call init_st\r
	273	pop de\r
	274	xor a\r
1c7e3963 L	275	ret\r
1c7e3963 L	276	\r
1c7e3963 L	277	;--------------------------------------------------------------\r
	278	; Allow the output buffer to drain\r
	279	\r
	280	func_tcsetaw:\r
	281	\r
	282	;--------------------------------------------------------------\r
	283	; Allow the output buffer to drain, discard pending input\r
	284	\r
	285	func_tcsetaf:\r
	286	\r
	287	;--------------------------------------------------------------\r
	288	; Sending a break (250ms .. 500ms)\r
	289	\r
	290	func_tcsbrk:\r
	291	\r
	292	;--------------------------------------------------------------\r
	293	; arg is timeinterval in 0.1sec\r
	294	\r
	295	func_tcsbrkp:\r
	296	\r
	297	;--------------------------------------------------------------\r
	298	; Turn break on\r
	299	\r
	300	func_tiocsbrk:\r
	301	\r
	302	;--------------------------------------------------------------\r
	303	; Turn break off\r
	304	\r
	305	func_tioccbrk:\r
	306	\r
	307	;--------------------------------------------------------------\r
	308	; Software flow control (TCOOFF, TCOON, TCIOFF, TCION)\r
	309	\r
	310	func_tcxonc:\r
	311	\r
	312	;--------------------------------------------------------------\r
	313	; Flush input/output buffer (TCIFLUSH, TCOFLUSH, TCIOFLUSH)\r
	314	\r
	315	func_tcflsh:\r
	316	\r
	317	;--------------------------------------------------------------\r
	318	; Get the number of bytes in the input buffer.\r
	319	\r
	320	func_fionread:\r
	321	\r
	322	;--------------------------------------------------------------\r
	323	; Get the number of bytes in the output buffer.\r
	324	\r
	325	func_tiocoutq:\r
	326	\r
	327	;--------------------------------------------------------------\r
	328	; get the status of modem bits.\r
	329	\r
	330	func_tiocmget:\r
	331	\r
	332	;--------------------------------------------------------------\r
	333	; set the indicated modem bits.\r
	334	\r
	335	func_tiocmbis:\r
	336	\r
	337	;--------------------------------------------------------------\r
	338	; clear the indicated modem bits.\r
	339	\r
	340	func_tiocmbic:\r
341	\r
342	;--------------------------------------------------------------\r
343	; set the status of modem bits.\r
344	\r
345	func_tiocmset:\r
346	\r
347	;--------------------------------------------------------------\r
348	; Get the status of the CLOCAL flag in the c_cflag field\r
349	\r
350	func_tiocgsoftcar:\r
351	\r
352	;--------------------------------------------------------------\r
353	; Set the CLOCAL flag when *argp is nonzero, and clear it otherwise.\r
354	\r
355	func_tiocssoftcar:\r
356	\r
357	or 0ffh\r
358	ret\r
359	\r
360	;--------------------------------------------------------------\r
361	\r
99b8d89e L	362	chk_ptr:\r
	363	ld a,e\r
	364	or d\r
	365	ret nz\r
	366	cpl\r
	367	pop hl\r
	368	ret\r
	369	\r
	370	;--------------------------------------------------------------\r
	371	\r
1c7e3963 L	372	asci_stop:\r
	373	ld c,stat0 ;Disable rx/tx interrupts\r
	374	xor a ;\r
	375	call out_asci_reg\r
	376	\r
	377	ld c,cntla0 ;Disable receiver and transmitter\r
	378	ld a,M_RTS0+M_EFR ;RTS/CKA1\r
	379	jr out_asci_reg\r
	380	\r
	381	;--------------------------------------------------------------\r
	382	\r
	383	asci_start:\r
2f8aa307 L	384	bit 0,(ix+o.reldev)\r
	385	jr nz,asci_st1\r
	386	in0 a,cntla0 ;asci0\r
	387	and ~M_RTS0 ;Activate RTS\r
	388	or M_EFR\r
	389	out0 (cntla0),a\r
	390	asci_st1:\r
1c7e3963	391	ld c,stat0 ;\r
d6829fd3	392	ld a,M_RIE\r
1c7e3963 L	393	jr out_asci_reg\r
	394	\r
	395	;--------------------------------------------------------------\r
	396	; output to asci0/1 register\r
	397	;\r
	398	; c: register address\r
	399	; a: value\r
	400	;\r
	401	\r
	402	out_asci_reg:\r
	403	push bc\r
99b8d89e L	404	bit 0,(ix+o.reldev)\r
	405	jr z,$+3\r
	406	inc c\r
1c7e3963 L	407	ld b,0\r
	408	out (c),a\r
	409	pop bc\r
d6829fd3 L	410	ret\r
d6829fd3 L	411	\r
99b8d89e L	412	;--------------------------------------------------------------\r
	413	; output 16 bit value to asci0/1 register\r
	414	;\r
	415	; c: register address\r
	416	; hl: value\r
	417	; a destroyed\r
	418	\r
	419	out_asci_reg_hl:\r
	420	ld a,b ;save b\r
	421	bit 0,(ix+o.reldev)\r
	422	jr z,$+4\r
	423	inc c\r
	424	inc c\r
	425	ld b,0\r
	426	out (c),l\r
	427	inc c\r
	428	out (c),h\r
	429	ld b,a\r
	430	ret\r
	431	\r
1c7e3963 L	432	;--------------------------------------------------------------\r
	433	; baud rate divider\r
	434	;\r
	435	; a: index\r
	436	; return\r
	437	; hl: divider\r
	438	\r
	439	as_br_div:\r
	440	push de\r
	441	push bc\r
	442	and 0fh\r
	443	add a,a ;get factor\r
	444	ld hl,bd150_tab\r
	445	call add_hla\r
	446	ld c,(hl)\r
	447	inc hl\r
	448	ld b,(hl)\r
	449	ld hl,(f_cpu)\r
	450	ld de,(f_cpu+2)\r
	451	call div32_r\r
	452	ld bc,32*150\r
	453	call div32_r\r
	454	ld de,2\r
	455	or a\r
	456	sbc hl,de\r
	457	pop bc\r
	458	pop de\r
	459	ret nc\r
	460	ld hl,0\r
	461	ret\r
	462	\r
	463	bd150_tab:\r
	464	; factor index baudrate orig. cp/m\r
	465	dw 19200/150 ; 0 19200 -\r
	466	dw 28800/150 ; 1 28800 50\r
	467	dw 38400/150 ; 2 38400 75\r
	468	dw 57600/150 ; 3 57600 110\r
	469	dw 11520/15 ; 4 115200 134.5\r
	470	dw 150/150 ; 5 150\r
	471	dw 300/150 ; 6 300\r
	472	dw 600/150 ; 7 600\r
	473	dw 1200/150 ; 8 1200\r
	474	dw 1800/150 ; 9 1800\r
	475	dw 2400/150 ;10 2400\r
	476	dw 3600/150 ;11 3600\r
	477	dw 4800/150 ;12 4800\r
	478	dw 7200/150 ;13 7200\r
	479	dw 9600/150 ;14 9600\r
	480	dw 19200/150 ;15 19200\r
	481	\r
	482	\r
	483	;--------------------------------------------------------------\r
	484	\r
	485	if 0\r
	486	\r
	487	initab0:\r
	488	db 1,stat0,0 ;Disable rx/tx interrupts\r
	489	;Enable baud rate generator\r
	490	db 1,asext0,M_BRGMOD+M_DCD0DIS ; +M_CTS0DIS\r
	491	db 2,astc0l\r
	492	init_br_off equ $ - initab0\r
	493	dw 28\r
	494	db 1,cntlb0,M_MPBT ;No MP Mode, X16\r
	495	db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
496	db 0\r
497	\r
498	initab1:\r
499	db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r
500	db 1,asext1,M_BRGMOD ;Enable baud rate generator\r
501	db 2,astc1l,low 3, high 3\r
502	db 1,cntlb1,M_MPBT ;No MP Mode, X16\r
503	db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
504	db 0\r
505	endif\r
d6829fd3	506	\r
d6829fd3 L	507	;--------------------------------------------------------------\r
	508	\r
	509	dseg\r
6dd88c25	510	asci0_ista:\r
d6829fd3 L	511	push ix\r
	512	ld ix,s0.inbuf ;\r
	513	call ff_empty\r
	514	pop ix\r
	515	ret\r
	516	\r
	517	;--------------------------------------------------------------\r
	518	\r
6dd88c25	519	asci1_ista:\r
d6829fd3 L	520	push ix\r
	521	ld ix,s1.inbuf ;\r
	522	call ff_empty\r
	523	pop ix\r
	524	ret\r
	525	\r
	526	;--------------------------------------------------------------\r
	527	; Get an input character\r
	528	\r
2f8aa307 L	529	if 0\r
	530	asci0_inp:\r
	531	push ix\r
	532	ld ix,s0.inbuf ;\r
	533	call ff_cnt\r
	534	cp 32\r
	535	jr nc,a0i_1\r
	536	di\r
	537	in0 a,(cntla0)\r
	538	res RTS0,a\r
	539	set EFR,a\r
	540	out0 (cntla0),a\r
	541	ei\r
	542	a0i_1:\r
	543	call ff_get\r
	544	pop ix\r
	545	ret\r
	546	endif\r
	547	\r
	548	\r
6dd88c25	549	asci0_inp:\r
d6829fd3 L	550	push ix\r
d6829fd3 L	551	ld ix,s0.inbuf ;\r
81ba3c84	552	call ff_gech\r
3134af6c L	553	ld a,b ;remaining chrs in buffer\r
3134af6c L	554	cp s0.rx_len/4 ; < 32?\r
59a12b33 L	555	jr nc,a0i_2 ; no, just get char\r
	556	ld b,(ix+oint.fflags) ; yes, enable RTS if needed\r
	557	bit CRTS_IFLOW,b ; yes, enable RTS if needed\r
3134af6c L	558	jr z,a0i_1 ; no needed\r
3134af6c L	559	di ; needed, enable\r
b8ad769f	560	in0 a,(cntla0)\r
46c2044d L	561	and ~M_RTS0 ;assert RTS\r
46c2044d L	562	or M_EFR ;don't reset error flags\r
b8ad769f	563	ei\r
46c2044d	564	out0 (cntla0),a\r
b8ad769f	565	a0i_1:\r
59a12b33 L	566	bit IXOFF,b ; XON/XOFF on input?\r
	567	jr z,a0i_2 ; no\r
	568	di\r
	569	set TDC1,(ix+oint.stat) ;\r
	570	in0 a,(stat0) ;\r
	571	or M_TIE ;\r
	572	ei\r
	573	out0 (stat0),a ;\r
	574	a0i_2:\r
81ba3c84	575	ld a,c\r
d6829fd3 L	576	pop ix\r
	577	ret\r
	578	\r
	579	;--------------------------------------------------------------\r
	580	; Get an input character\r
	581	\r
6dd88c25	582	asci1_inp:\r
d6829fd3 L	583	push ix\r
d6829fd3 L	584	ld ix,s1.inbuf ;\r
81ba3c84	585	call ff_gech\r
3134af6c L	586	ld a,b ; remaining chars in buffer\r
	587	cp s0.rx_len/4 ; == 25% full?\r
	588	jr nz,a1i_2 ; no, just get char\r
	589	bit IXOFF,(ix+oint.fflags) ; XON/XOFF on input?\r
	590	jr z,a1i_2 ; no\r
6d39b0ff L	591	di\r
	592	set TDC1,(ix+oint.stat) ;\r
	593	in0 a,(stat1) ;\r
59a12b33	594	or M_TIE, ;\r
6d39b0ff L	595	out0 (stat1),a ;\r
6d39b0ff L	596	ei\r
3134af6c L	597	a1i_2:\r
3134af6c L	598	ld a,c ; get back the char\r
d6829fd3 L	599	pop ix\r
	600	ret\r
	601	\r
	602	;--------------------------------------------------------------\r
	603	; Output status\r
	604	\r
6dd88c25	605	asci0_osta:\r
d6829fd3 L	606	push ix\r
	607	ld ix,s0.outbuf ;\r
	608	call ff_full\r
	609	pop ix\r
	610	ret\r
	611	\r
	612	;--------------------------------------------------------------\r
	613	; Output status\r
	614	\r
6dd88c25	615	asci1_osta:\r
d6829fd3 L	616	push ix\r
	617	ld ix,s1.outbuf ;\r
	618	call ff_full\r
	619	pop ix\r
	620	ret\r
	621	\r
	622	;--------------------------------------------------------------\r
	623	; put character in c in buffer\r
	624	; destroys hl, bc\r
	625	; returns output char in a\r
	626	\r
6dd88c25	627	asci0_out:\r
d6829fd3 L	628	push ix ;\r
d6829fd3 L	629	ld ix,s0.outbuf ;\r
81ba3c84 L	630	call ff_puth\r
81ba3c84 L	631	pop ix ;\r
d6829fd3 L	632	di ;\r
	633	in0 c,(stat0) ;\r
	634	set TIE,c ;\r
	635	out0 (stat0),c ;\r
	636	ei ;\r
d6829fd3 L	637	ret\r
	638	\r
	639	;--------------------------------------------------------------\r
	640	; put character in c in buffer\r
	641	; destroys hl, bc\r
	642	; returns output char in a\r
	643	\r
6dd88c25	644	asci1_out:\r
d6829fd3 L	645	push ix ;\r
d6829fd3 L	646	ld ix,s1.outbuf ;\r
81ba3c84 L	647	call ff_puth\r
81ba3c84 L	648	pop ix ;\r
d6829fd3 L	649	di ;\r
	650	in0 c,(stat1) ;\r
	651	set TIE,c ;\r
	652	out0 (stat1),c ;\r
	653	ei ;\r
d6829fd3 L	654	ret\r
	655	\r
	656	\r
6dd88c25 L	657	;--------------------------------------------------------------\r
	658	\r
	659	cseg\r
	660	rtxisvjmp0:\r
	661	call isv_sw\r
5d7663e1 L	662	dw asci0_int\r
5d7663e1 L	663	\r
6dd88c25 L	664	rtxisvjmp1:\r
6dd88c25 L	665	call isv_sw\r
5d7663e1	666	dw asci1_int\r
6dd88c25 L	667	\r
6dd88c25 L	668	;--------------------------------------------------------------\r
5d7663e1 L	669	; ASCI 0/1 Transmit/Receive interupt routines\r
	670	\r
	671	.lall\r
	672	asci_int macro dev\r
fd06cceb	673	local rxi_2,rxi_3\r
d6829fd3	674	\r
46c2044d	675	push ix\r
5d7663e1 L	676	rxtxi&dev&_lp0:\r
	677	ld ix,s&dev&.inbuf ;\r
	678	rxtxi&dev&_lp1:\r
	679	in0 a,(stat&dev) ;receive flag set?\r
	680	jp p,txi&dev ;RDRF == Bit 7\r
6dd88c25 L	681	and M_OVRN+M_PERR+M_FE\r
6dd88c25 L	682	ld e,a\r
81ba3c84	683	\r
5d7663e1	684	in0 a,(asext&dev)\r
46c2044d L	685	and M_BREAK\r
	686	or e\r
	687	ld e,a\r
d6829fd3	688	\r
5d7663e1	689	in0 d,(cntla&dev) ;\r
b8ad769f	690	res EFR,d ;\r
5d7663e1	691	out0 (cntla&dev),d\r
d6829fd3	692	\r
3134af6c	693	ld c,(ix+o.in_idx) ;input buffer pointer\r
d6829fd3	694	ld b,0\r
5d7663e1	695	ld hl,s&dev&.inbuf ;\r
d6829fd3	696	add hl,bc\r
6dd88c25	697	\r
3134af6c	698	in0 a,(rdr&dev) ;get char\r
b8ad769f	699	ld (hl),a\r
6dd88c25 L	700	;todo: break detection\r
	701	;todo: parity, framing overrun error\r
	702	\r
1c7e3963	703	ld e,(ix+oint.fflags)\r
fd06cceb L	704	; bit IXON,e\r
	705	; jr z,rxi_2\r
	706	;todo: test XON/XOFF\r
5d7663e1	707	rxi_2:\r
46c2044d L	708	\r
	709	ld a,c ;increment buffer in pointer\r
	710	inc a ;\r
81ba3c84 L	711	ld b,(ix+o.mask) ;\r
81ba3c84 L	712	and b ;\r
b8ad769f	713	ld c,a\r
81ba3c84 L	714	\r
81ba3c84 L	715	sub (ix+o.out_idx) ;\r
5d7663e1	716	jr z,rxtxi&dev&_lp1 ;skip if buffer is full\r
6dd88c25	717	\r
3134af6c	718	ld (ix+o.in_idx),c ;input buffer pointer\r
6dd88c25	719	\r
81ba3c84 L	720	jr nc,$+3 ;\r
81ba3c84 L	721	adc b ;\r
6dd88c25	722	\r
5d7663e1	723	cp s&dev&.tx_len*3/4\r
fd06cceb	724	jr nz,rxtxi&dev&_lp1\r
6dd88c25	725	\r
fd06cceb	726	if dev=0 ; only channel 0 has rts line\r
6dd88c25	727	bit CRTS_IFLOW,e\r
fd06cceb	728	jr z,rxi0_nocrts\r
6dd88c25 L	729	\r
	730	set EFR,d\r
	731	set RTS0,d ;RTS inactive\r
fd06cceb L	732	out0 (cntla0),d ;\r
fd06cceb L	733	rxi0_nocrts:\r
5d7663e1	734	endif\r
fd06cceb	735	\r
3134af6c	736	bit IXOFF,e\r
fd06cceb	737	jr z,rxtxi&dev&_lp1\r
6d39b0ff L	738	;send XOFF\r
	739	set TDC3,(ix+oint.stat)\r
	740	in0 a,(stat&dev) ;\r
	741	set TIE,a ;\r
	742	out0 (stat&dev),a ;\r
5d7663e1	743	jr rxtxi&dev&_lp1\r
81ba3c84	744	\r
5d7663e1	745	txi&dev:\r
6dd88c25	746	ld e,a\r
46c2044d	747	bit TDRE,e ;TX int?\r
5d7663e1	748	jr z,rxtxi&dev&_exit\r
5d7663e1	749	;todo: xon/xoff\r
6d39b0ff L	750	bit IXOFF,(ix+oint.fflags)\r
	751	jr z,txi&dev&_char\r
	752	txi&dev&_dc1:\r
	753	bit TDC1,(ix+oint.stat)\r
	754	jr z,txi&dev&_dc3\r
	755	res TDC1,(ix+oint.stat)\r
	756	ld a,DC1\r
	757	jr txi&dev&_dc1dc3\r
	758	\r
	759	txi&dev&_dc3:\r
	760	bit TDC3,(ix+oint.stat)\r
	761	jr z,txi&dev&_char\r
	762	res TDC3,(ix+oint.stat)\r
	763	ld a,DC3\r
	764	txi&dev&_dc1dc3:\r
	765	out0 (tdr&dev),a ;\r
	766	jp rxtxi&dev&_lp0\r
5d7663e1	767	\r
6d39b0ff	768	txi&dev&_char:\r
5d7663e1 L	769	ld hl,s&dev&.outbuf+o.in_idx ;[in]\r
	770	ld a,(hl) ;\r
	771	inc hl ;[out]\r
	772	ld c,(hl) ;\r
	773	cp c ;\r
	774	jr z,txi&dev&_empty ;\r
	775	inc hl ;fifo base\r
	776	ld b,0 ;\r
	777	add hl,bc ;\r
	778	ld a,(hl) ;\r
	779	out0 (tdr&dev),a ;\r
	780	inc c ;\r
	781	ld a,(s&dev&.outbuf+o.mask) ;\r
	782	and c ;\r
	783	ld (s&dev&.outbuf+o.out_idx),a ;\r
d6829fd3	784	\r
6d39b0ff	785	jp rxtxi&dev&_lp0\r
81ba3c84	786	\r
5d7663e1	787	txi&dev&_empty:\r
d6829fd3	788	res TIE,e ;disable tx-int\r
5d7663e1	789	out0 (stat&dev),e ; 5\r
46c2044d	790	\r
5d7663e1	791	rxtxi&dev&_exit:\r
d6829fd3 L	792	pop ix\r
d6829fd3 L	793	ret\r
5d7663e1	794	endm\r
d6829fd3 L	795	\r
d6829fd3 L	796	dseg\r
5d7663e1 L	797	;--------------------------------------------------------------\r
5d7663e1 L	798	; ASCI 0 Transmit/Receive interupt routines\r
d6829fd3	799	\r
5d7663e1 L	800	asci0_int:\r
5d7663e1 L	801	asci_int 0\r
d6829fd3	802	\r
5d7663e1 L	803	;--------------------------------------------------------------\r
5d7663e1 L	804	; ASCI 1 Transmit/Receive interupt routines\r
d6829fd3	805	\r
5d7663e1 L	806	asci1_int:\r
5d7663e1 L	807	asci_int 1\r
d6829fd3 L	808	\r
d6829fd3 L	809	end\r