cbios/misc.180

   1
   2         public intinit
   3         public cpu_frq
   4         public get_tmr
   5
   6         extrn div32_r,?pmsg
   7         extrn msg.sm,msg.recv,hwl2phy
   8
   9         include config.inc
  10         include z180reg.inc
  11
  12
  13 ;----------------------------------------------------------------------
  14
  15         dseg
  16
  17 intinit:
  18         ld      hl,ivtab        ;
  19         ld      a,h             ;
  20         ld      i,a             ;
  21         out0    (il),l          ;
  22         im      2
  23
  24 ; Let all vectors point to spurious int routines.
  25
  26         ld      de,sp.int0
  27         ld      bc,sp.int.len
  28         ld      a,9
  29 ivt_i1:
  30         ld      (hl),e
  31         inc     l
  32         ld      (hl),d
  33         inc     l
  34         ex      de,hl
  35         add     hl,bc
  36         ex      de,hl
  37         dec     a
  38         jr      nz,ivt_i1
  39         ret
  40
  41
  42 ;--------------------------------------------------------------------
  43 ; Spurious interrupt handler
  44
  45         cseg    ; common area
  46 sp.int0:
  47         ld      a,00h
  48         jr      sp.i.1
  49 sp.int.len equ  $-sp.int0
  50         ld      a,01h
  51         jr      sp.i.1
  52         ld      a,02h
  53         jr      sp.i.1
  54         ld      a,03h
  55         jr      sp.i.1
  56         ld      a,04h
  57         jr      sp.i.1
  58         ld      a,05h
  59         jr      sp.i.1
  60         ld      a,06h
  61         jr      sp.i.1
  62         ld      a,07h
  63         jr      sp.i.1
  64         ld      a,08h
  65 sp.i.1:
  66 ;       out     (80h),a
  67
  68         add     a,'0'
  69         ld      (spi$nr),a
  70         ld      hl,spi$msg
  71         call    ?pmsg
  72 sp.i.2:
  73         halt
  74         jr      sp.i.2
  75
  76 spi$msg:
  77         db      13,10,'Spurious Int: '
  78 spi$nr: db      '0'
  79         db      0
  80
  81 ;--------------------------------------------------------------------
  82 ;
  83 ; Get/compute CPU clock
  84 ;
  85 ;    return:
  86 ;       hlde:   CPU frequency (Hz)
  87 ;
  88
  89         dseg
  90
  91 cpu_frq:
  92         ld      hl,0
  93         ld      d,h
  94         ld      e,l
  95         call    get_tmr
  96         push    de
  97         push    hl
  98
  99 ; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
 100 ; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
 101 ;
 102
 103 ;       ld      hl,8192         ; 147456/18
 104         ld      hl,(10240-100)*5 ; 184320/18
 105         ld      de,1
 106         or      a
 107 dly_lp:
 108         sbc     hl,de           ; 10
 109         jr      nz,dly_lp       ; 6/8  -> 18 cycles
 110
 111         pop     hl
 112         pop     de
 113         call    get_tmr
 114
 115         ld      b,h
 116         ld      c,l
 117         ld      de,036EEh       ;18432000/(2**16) * 50
 118         ld      hl,08000h       ;18432000%(2**16) * 50
 119
 120         ld      a,b
 121         or      a
 122         jr      nz,cpuf_div
 123         ld      a,c
 124         cp      2
 125         jr      c,cpuf_done
 126 cpuf_div:
 127         call    div32_r
 128 cpuf_done:
 129         ret
 130
 131 ;--------------------------------------------------------------------
 132
 133         dseg
 134 get_tmr:
 135         push    de
 136         push    hl
 137         ld      hl,1*256 + 3            ; h = subcommand, l = command
 138         push    hl
 139         ld      hl,0
 140         add     hl,sp
 141         ld      b,6
 142         call    msg.sm
 143
 144         dec     sp
 145         ld      hl,0
 146         add     hl,sp
 147         ld      b,7                     ; max receive message len
 148         call    msg.recv
 149
 150         pop     bc
 151         inc     sp
 152         pop     hl
 153         pop     de
 154         ret
 155
 156 ;----------------------------------------------------------------------
 157
 158         end