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Commit | Line | Data |
---|---|---|
fecee241 L |
1 | \r |
2 | FALSE equ 0\r | |
3 | TRUE equ NOT FALSE\r | |
4 | \r | |
7d60b20b L |
5 | \r |
6 | DEBUG equ true\r | |
7 | \r | |
2fa1a706 L |
8 | banked equ true\r |
9 | \r | |
29605004 L |
10 | ;-----------------------------------------------------\r |
11 | ; CPU and BANKING types\r | |
12 | \r | |
a16ba2b0 | 13 | \r |
fecee241 L |
14 | CPU_Z180 equ TRUE\r |
15 | CPU_Z80 equ FALSE\r | |
16 | \r | |
17 | ROMSYS equ FALSE\r | |
a16ba2b0 | 18 | \r |
29605004 L |
19 | AVRCLK equ 18432 ;[KHz]\r |
20 | \r | |
fecee241 | 21 | if CPU_Z180\r |
29605004 L |
22 | \r |
23 | ;-----------------------------------------------------\r | |
845cbdbd L |
24 | ;FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]\r |
25 | ;PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)\r | |
a16ba2b0 | 26 | \r |
7d60b20b L |
27 | ;----------------------------------------------------------------------\r |
28 | ; Baudrate Generator for x16 clock mode:\r | |
29 | ; TC = (f PHI / (32 * baudrate)) - 2\r | |
30 | ;\r | |
31 | ; PHI [MHz]: 9.216 18.432\r | |
32 | ; baudrate TC TC\r | |
33 | ; ----------------------\r | |
34 | ; 115200 - 3\r | |
35 | ; 57600 3 8\r | |
36 | ; 38400 - 13\r | |
37 | ; 19200 13 28\r | |
38 | ; 9600 28 58\r | |
39 | \r | |
40 | \r | |
a16ba2b0 L |
41 | ;-----------------------------------------------------\r |
42 | ; Programmable Reload Timer (PRT)\r | |
43 | \r | |
44 | PRT_PRE equ 20 ;PRT prescaler\r | |
45 | \r | |
a16ba2b0 L |
46 | ;-----------------------------------------------------\r |
47 | ; MMU\r | |
48 | \r | |
cdc4625b | 49 | COMMON_SIZE equ 16*1024 ;Common Area size in bytes\r |
fecee241 L |
50 | ;must be multiple of 4K\r |
51 | \r | |
2fa1a706 | 52 | if (COMMON_SIZE mod 1000h)\r |
fecee241 L |
53 | .printx COMMON_SIZE not multiple of 4K!\r |
54 | end ;stop assembly\r | |
55 | endif\r | |
56 | \r | |
57 | CSK equ COMMON_SIZE/1000h ;\r | |
58 | CA equ 10h - CSK ;common area start\r | |
59 | BA equ 0 ;banked area start\r | |
60 | \r | |
61 | SYS$CBR equ 0\r | |
e4c4b148 L |
62 | SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r |
63 | USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r | |
a16ba2b0 L |
64 | \r |
65 | \r | |
66 | BANKS equ 18 ;max nr. of banks\r | |
67 | \r | |
68 | ;-----------------------------------------------------\r | |
69 | \r | |
70 | CREFSH equ 0 ;Refresh rate register (disable refresh)\r | |
71 | CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States\r | |
e4c4b148 | 72 | PHI_X2 equ 0 ;set to M_X2CM to enable the clock doubler\r |
a16ba2b0 | 73 | \r |
fecee241 L |
74 | endif ;CPU_Z180\r |
75 | if CPU_Z80\r | |
29605004 L |
76 | \r |
77 | PHI equ AVRCLK/5 ;CPU frequency [KHz]\r | |
78 | BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]\r | |
79 | ;BDCLK16 equ\r | |
80 | \r | |
81 | SIOAD EQU 0bch\r | |
82 | SIOAC EQU 0bdh\r | |
83 | SIOBD EQU 0beh\r | |
84 | SIOBC EQU 0bfh\r | |
85 | \r | |
86 | CTC0 EQU 0f4h\r | |
87 | CTC1 EQU 0f5h\r | |
88 | CTC2 EQU 0f6h\r | |
89 | CTC3 EQU 0f7h\r | |
90 | \r | |
91 | ;\r | |
92 | ; Init Serial I/O for console input and output (SIO-A)\r | |
93 | ;\r | |
94 | ; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r | |
95 | ;\r | |
96 | ; Baudrate Divider SIO CTC\r | |
97 | ; ---------------------------------\r | |
98 | ; 115200 16 16 1\r | |
99 | ; 57600 32 16 2\r | |
100 | ; 38400 48 16 3\r | |
101 | ; 19200 96 16 6\r | |
102 | ; 9600 192 16 12\r | |
103 | ; 4800 384 16 24\r | |
104 | ; 2400 768 16 48\r | |
105 | ; 1200 1536 16 96\r | |
106 | ; 600 3072 16 192\r | |
107 | ; 300 6144 64 92\r | |
108 | \r | |
fecee241 | 109 | endif ; CPU_Z80\r |
a16ba2b0 | 110 | \r |
fecee241 | 111 | if ROMSYS\r |
a16ba2b0 L |
112 | c$rom equ 0a5h\r |
113 | ROM_EN equ 0C0h\r | |
114 | ROM_DIS equ ROMEN+1\r | |
fecee241 | 115 | if CPU_Z180\r |
a16ba2b0 | 116 | CWAITROM equ 2 shl MWI0\r |
fecee241 L |
117 | endif\r |
118 | endif\r | |
a16ba2b0 L |
119 | \r |
120 | \r | |
cdc4625b | 121 | DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)\r |
a16ba2b0 | 122 | \r |
cdc4625b L |
123 | INIDONE equ 03Fh ;CP/M skip hw init, if this address\r |
124 | INIDONEVAL equ 080h ; is set to this value.\r | |
a16ba2b0 | 125 | \r |
cdc4625b L |
126 | mtx.fifo_len equ 32 ;Message transfer fifos\r |
127 | mtx.fifo_id equ 0 ; This *must* have #0\r | |
e4c4b148 | 128 | mrx.fifo_len equ 32\r |
cdc4625b | 129 | mrx.fifo_id equ 1\r |
a16ba2b0 | 130 | \r |
e4c4b148 L |
131 | ci.fifo_len equ 32 ;AVRCON Character I/O via AVR\r |
132 | ci.fifo_id equ 2\r | |
133 | co.fifo_len equ 32\r | |
134 | co.fifo_id equ 3\r | |
a16ba2b0 | 135 | \r |
e4c4b148 L |
136 | s1.rx_len equ 128 ;Serial 1 (ASCI1) buffers\r |
137 | s1.rx_id equ 4 ;\r | |
138 | s1.tx_len equ 128 ;\r | |
139 | s1.tx_id equ 5 ;\r | |
a16ba2b0 | 140 | \r |
29605004 L |
141 | AVRINT5 equ 4Fh\r |
142 | AVRINT6 equ 5Fh\r | |
bad2d92d | 143 | ;PMSG equ 80h\r |
a16ba2b0 L |
144 | \r |
145 | ;-----------------------------------------------------\r | |
fecee241 | 146 | ; Definition of (logical) top 2 memory pages\r |
a16ba2b0 L |
147 | \r |
148 | sysram_start equ 0FE00h\r | |
ad9bc17c | 149 | bs$stack$size equ 80\r |
a16ba2b0 L |
150 | \r |
151 | isvsw_loc equ 0FEE0h\r | |
152 | \r | |
153 | ivtab equ 0ffc0h ;int vector table\r | |
154 | iv2tab equ ivtab + 2*9\r | |
155 | \r | |
156 | \r | |
157 | \r | |
158 | ;-----------------------------------------------------\r | |
159 | \r | |
e4c4b148 | 160 | o.id equ -4\r |
a16ba2b0 L |
161 | o.mask equ -3\r |
162 | o.in_idx equ -2\r | |
163 | o.out_idx equ -1\r | |
815c1735 | 164 | \r |
a16ba2b0 L |
165 | .lall\r |
166 | \r | |
e4c4b148 L |
167 | mkbuf macro id,name,size\r |
168 | if ((size AND (size-1)) NE 0) OR (size GT 256)\r | |
a16ba2b0 L |
169 | .printx Error: buffer ^size must be power of 2 and in range 0..256!\r |
170 | name&.mask equ ;wrong size error\r | |
171 | else\r | |
e4c4b148 | 172 | db id\r |
815c1735 | 173 | ds 3\r |
a16ba2b0 L |
174 | name:: ds size\r |
175 | name&.mask equ low (size-1)\r | |
176 | if size ne 0\r | |
177 | name&.end equ $-1\r | |
178 | name&.len equ size\r | |
e4c4b148 | 179 | name&.id equ id\r |
a16ba2b0 L |
180 | endif\r |
181 | endif\r | |
182 | endm\r | |
183 | \r | |
184 | ;-----------------------------------------------------\r | |
185 | \r | |
815c1735 | 186 | inidat macro\r |
a16ba2b0 | 187 | cseg\r |
815c1735 | 188 | ??ps.a defl $\r |
a16ba2b0 L |
189 | endm\r |
190 | \r | |
191 | inidate macro\r | |
192 | ??ps.len defl $ - ??ps.a\r | |
193 | dseg\r | |
194 | ds ??ps.len\r | |
195 | endm\r | |
ad9bc17c L |
196 | \r |
197 | ;-----------------------------------------------------\r | |
198 | \r | |
199 | b0call macro address\r | |
200 | call _b0call\r | |
201 | dw address\r | |
202 | endm\r |