z180/config.inc

   1
   2 FALSE   equ     0
   3 TRUE    equ     NOT FALSE
   4
   5
   6 DEBUG   equ     true
   7
   8 banked  equ     true
   9
  10 ;-----------------------------------------------------
  11 ; CPU and BANKING types
  12
  13
  14 CPU_Z180        equ     TRUE
  15 CPU_Z80         equ     FALSE
  16
  17 ROMSYS          equ     FALSE
  18
  19 AVRCLK          equ     18432           ;[KHz]
  20
  21     if CPU_Z180
  22
  23 ;-----------------------------------------------------
  24 ;FOSC           equ     AVRCLK/2        ;Oscillator frequency [KHz]
  25 ;PHI            equ     FOSC*2          ;CPU frequency (clock doubler enabled)
  26
  27 ;----------------------------------------------------------------------
  28 ; Baudrate Generator for x16 clock mode:
  29 ; TC = (f PHI / (32 * baudrate)) - 2
  30 ;
  31 ;     PHI [MHz]: 9.216 18.432
  32 ;     baudrate     TC     TC
  33 ;     ----------------------
  34 ;      115200       -      3
  35 ;       57600       3      8
  36 ;       38400       -     13
  37 ;       19200      13     28
  38 ;        9600      28     58
  39
  40
  41 ;-----------------------------------------------------
  42 ; Programmable Reload Timer (PRT)
  43
  44 PRT_PRE         equ     20              ;PRT prescaler
  45
  46 ;-----------------------------------------------------
  47 ; MMU
  48
  49 COMMON_SIZE     equ     16*1024         ;Common Area size in bytes
  50                                         ;must be multiple of 4K
  51
  52 if (COMMON_SIZE mod 1000h)
  53         .printx COMMON_SIZE not multiple of 4K!
  54         end     ;stop assembly
  55 endif
  56
  57 CSK     equ     COMMON_SIZE/1000h       ;
  58 CA      equ     10h - CSK               ;common area start
  59 BA      equ     0                       ;banked area start
  60
  61 SYS$CBR         equ     0
  62 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  63 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  64
  65
  66 BANKS           equ     18              ;max nr. of banks
  67
  68 ;-----------------------------------------------------
  69
  70 CREFSH          equ     0               ;Refresh rate register (disable refresh)
  71 CWAITIO         equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States
  72 PHI_X2          equ     0               ;set to M_X2CM to enable the clock doubler
  73
  74     endif               ;CPU_Z180
  75     if  CPU_Z80
  76
  77 PHI             equ     AVRCLK/5        ;CPU frequency [KHz]
  78 BAUDCLCK        equ     AVRCLK/10       ;Baudrate clock [KHz]
  79 ;BDCLK16                equ
  80
  81 SIOAD   EQU     0bch
  82 SIOAC   EQU     0bdh
  83 SIOBD   EQU     0beh
  84 SIOBC   EQU     0bfh
  85
  86 CTC0    EQU     0f4h
  87 CTC1    EQU     0f5h
  88 CTC2    EQU     0f6h
  89 CTC3    EQU     0f7h
  90
  91 ;
  92 ; Init Serial I/O for console input and output (SIO-A)
  93 ;
  94 ; Baudrate clock: 1843200 Hz (Bus connector pin A17)
  95 ;
  96 ; Baudrate   Divider    SIO     CTC
  97 ; ---------------------------------
  98 ; 115200          16     16       1
  99 ;  57600          32     16       2
 100 ;  38400          48     16       3
 101 ;  19200          96     16       6
 102 ;   9600         192     16      12
 103 ;   4800         384     16      24
 104 ;   2400         768     16      48
 105 ;   1200        1536     16      96
 106 ;    600        3072     16     192
 107 ;    300        6144     64      92
 108
 109     endif       ; CPU_Z80
 110
 111     if  ROMSYS
 112 c$rom           equ     0a5h
 113 ROM_EN          equ     0C0h
 114 ROM_DIS         equ     ROMEN+1
 115      if CPU_Z180
 116 CWAITROM        equ     2 shl MWI0
 117      endif
 118     endif
 119
 120
 121 DDTZRSTVEC      equ     030h            ;DDTZ Restart vector (breakpoints)
 122
 123 INIDONE         equ     03Fh            ;CP/M skip hw init, if this address
 124 INIDONEVAL      equ     080h            ;    is set to this value.
 125
 126 mtx.fifo_len    equ     32              ;Message transfer fifos
 127 mtx.fifo_id     equ     0               ;    This *must* have #0
 128 mrx.fifo_len    equ     32
 129 mrx.fifo_id     equ     1
 130
 131 ci.fifo_len     equ     32              ;AVRCON Character I/O via AVR
 132 ci.fifo_id      equ     2
 133 co.fifo_len     equ     32
 134 co.fifo_id      equ     3
 135
 136 s1.rx_len       equ     128             ;Serial 1 (ASCI1) buffers
 137 s1.rx_id        equ     4               ;
 138 s1.tx_len       equ     128             ;
 139 s1.tx_id        equ     5               ;
 140
 141 AVRINT5         equ     4Fh
 142 AVRINT6         equ     5Fh
 143 ;PMSG           equ     80h
 144
 145 ;-----------------------------------------------------
 146 ; Definition of (logical) top 2 memory pages
 147
 148 sysram_start    equ     0FE00h
 149 bs$stack$size   equ     80
 150
 151 isvsw_loc       equ     0FEE0h
 152
 153 ivtab           equ     0ffc0h          ;int vector table
 154 iv2tab          equ     ivtab + 2*9
 155
 156
 157
 158 ;-----------------------------------------------------
 159
 160 o.id            equ     -4
 161 o.mask          equ     -3
 162 o.in_idx        equ     -2
 163 o.out_idx       equ     -1
 164
 165         .lall
 166
 167 mkbuf   macro   id,name,size
 168   if ((size AND (size-1)) NE 0) OR (size GT 256)
 169     .printx Error: buffer ^size must be power of 2 and in range 0..256!
 170     name&.mask equ ;wrong size error
 171   else
 172     db id
 173     ds 3
 174     name:: ds size
 175     name&.mask equ low (size-1)
 176     if size ne 0
 177       name&.end equ $-1
 178       name&.len equ size
 179       name&.id equ id
 180     endif
 181   endif
 182 endm
 183
 184 ;-----------------------------------------------------
 185
 186 inidat  macro
 187         cseg
 188 ??ps.a  defl    $
 189         endm
 190
 191 inidate macro
 192 ??ps.len defl   $ - ??ps.a
 193         dseg
 194         ds      ??ps.len
 195         endm
 196
 197 ;-----------------------------------------------------
 198
 199 b0call  macro   address
 200         call    _b0call
 201         dw      address
 202         endm