[z180-stamp.git] / avr / z80-if.c

/*
 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

/**
 *
 * Pin assignments
 *
 * | Z180-Sig   |   AVR-Port    | Dir   |
 * +------------+---------------+-------+
 * |    A0      | PA    0       |  O    |
 * |    A1      | PA    1       |  O    |
 * |    A2      | PA    2       |  O    |
 * |    A3      | PA    3       |  O    |
 * |    A4      | PA    4       |  O    |
 * |    A5      | PA    5       |  O    |
 * |    A6      | PA    6       |  O    |
 * |    A7      | PA    7       |  O    |
 * |    A8      | PC    0       |  O    |
 * |    A9      | PC    1       |  O    |
 * |    A10     | PC    2       |  O    |
 * |    A11     | PC    3       |  O    |
 * |    A12     | PC    4       |  O    |
 * |    A13     | PC    5       |  O    |
 * |    A14     | PC    6       |  O    |
 * |    A15     | PC    7       |  O    |
 * |    A16     | PE    2       |  O    |
 * |    A17     | PE    3       |  O    |
 * |    A18     | PE    4       |  O    |
 * |    D0      | PF    0       |  I/O  |
 * |    D1      | PF    1       |  I/O  |
 * |    D2      | PF    2       |  I/O  |
 * |    D3      | PF    3       |  I/O  |
 * |    D4      | PF    4       |  I/O  |
 * |    D5      | PF    5       |  I/O  |
 * |    D6      | PF    6       |  I/O  |
 * |    D7      | PF    7       |  I/O  |
 * |    RD      | PD    3       |  O    |
 * |    WR      | PD    2       |  O    |
 * |    MREQ    | PD    4       |  O    |
 * |    RST     | PD    5       |  O    |
 * |    BUSREQ  | PD    7       |  O    |
 * |    BUSACK  | PD    6       |  I    |
 * |
 * | Optional
 * +------------------------------------+
 * |    STEP    | PG    0       |  O    |
 * |    RUN     | PG    1       |  O    |
 * |    WAIT    | PG    2       |  I    |

 */


#include "z80-if.h"
#include <util/atomic.h>
#include "debug.h"
#include "config.h"
#include "env.h"


//#define P_ZCLK		PORTB
//#define ZCLK		5
//#define DDR_ZCLK	DDRB
#define P_MREQ		PORTD
#define MREQ		4
#define DDR_MREQ	DDRD
#define P_RD		PORTD
#define RD		3
#define P_WR		PORTD
#define WR		2
#define P_BUSREQ	PORTD
#define BUSREQ		7
#define DDR_BUSREQ	DDRD
#define P_BUSACK	PORTD
#define PIN_BUSACK	PIND
#define BUSACK		6
#define DDR_BUSACK	DDRD
#define P_RST		PORTD
#define DDR_RST		DDRD
#define RST		5


#define P_DB		PORTF
#define PIN_DB		PINF
#define DDR_DB		DDRF

#define P_ADL		PORTA
#define P_ADH		PORTC
#define P_ADB		PORTE
#define PIN_ADB		PINE
#define DDR_ADL		DDRA
#define DDR_ADH		DDRC
#define DDR_ADB		DDRE

#define ADB_WIDTH	3
#define ADB_SHIFT	2
//#define ADB_PORT	PORTE


//#define Z80_O_ZCLK	SBIT(P_ZCLK, 5)
#define	Z80_O_MREQ	SBIT(P_MREQ, 4)
#define Z80_O_RD	SBIT(P_RD, 3)
#define Z80_O_WR	SBIT(P_WR, 2)
#define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI	SBIT(P_NMI, )
#define Z80_O_RST	SBIT(P_RST, 5)
#define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT	SBIT(P_HALT, )

/* Optional */
#define P_RUN		PORTG
#define RUN			1
#define DDR_RUN		DDRG
#define P_STEP		PORTG
#define STEP		0
#define DDR_STEP	DDRG
#define P_WAIT		PORTG
#define WAIT		2
#define DDR_WAIT	DDRG
/* All three signals are on the same Port (PortG) */
#define PORT_SS		PORTG
#define DDR_SS		DDRG
#define PIN_SS		PING
#define	Z80_O_RUN	SBIT(PORT_SS, RUN)
#define	Z80_O_STEP	SBIT(PORT_SS, STEP)
#define	Z80_I_WAIT	SBIT(PORT_SS, WAIT)


#define BUS_TO 20


#define MASK(n)	((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))


static zstate_t zstate;
static volatile uint8_t timer;		/* used for bus timeout */

/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC4A                  */
/*---------------------------------------------------------*/

ISR(TIMER5_COMPA_vect)
{

	uint8_t i = timer;

	if (i)
		timer = i - 1;
}

/*--------------------------------------------------------------------------*/


static void z80_addrbus_set_in(void)
{
	/* /MREQ, /RD, /WR: Input, no pullup */
	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
	Z80_O_MREQ = 0;
	Z80_O_RD = 0;
	Z80_O_WR = 0;

	P_ADL = 0;
	DDR_ADL = 0;
	P_ADH = 0;
	DDR_ADH = 0;
	PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_addrbus_set_out(void)
{
	/* /MREQ, /RD, /WR: Output and high */
	Z80_O_MREQ = 1;
	Z80_O_RD = 1;
	Z80_O_WR = 1;
	DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);

	DDR_ADL = 0xff;
	DDR_ADH = 0xff;
	DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_dbus_set_in(void)
{
	DDR_DB = 0;
	P_DB = 0;
}


static void z80_dbus_set_out(void)
{
	DDR_DB = 0xff;
}


static void z80_reset_pulse(void)
{
	Z80_O_RST = 0;
	_delay_us(10);
	Z80_O_RST = 1;
}


void z80_setup_bus(void)
{
	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {

		/* /ZRESET: Output and low */
		Z80_O_RST = 0;
		DDR_RST |= _BV(RST);

		/* /BUSREQ: Output and high */
		Z80_O_BUSREQ = 1;
		DDR_BUSREQ |= _BV(BUSREQ);

		/* /BUSACK: Input, no pullup */
		DDR_BUSACK &= ~_BV(BUSACK);
		P_BUSACK &= ~_BV(BUSACK);

		z80_addrbus_set_in();
		z80_dbus_set_in();

		if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
			/* /RUN & /STEP: output, /WAIT: input */

			PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
			DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
		}

		zstate = RESET;
	}

	/* Timer 5 */
	PRR1 &= ~_BV(PRTIM5);
	OCR5A = F_CPU / 1024 / 10 - 1;		  /* Timer: 10Hz interval (OC4A) */
	TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
	TIMSK5 = _BV(OCIE5A);				  /* Enable oca interrupt */

}


zstate_t z80_bus_state(void)
{
	return zstate;
}


static void z80_busreq_hpulse(void)
{
	z80_dbus_set_in();
	z80_addrbus_set_in();

#if 0
	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;
		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
	}
#endif

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;

		do {
			if (Z80_I_BUSACK == 1)  {
				Z80_O_BUSREQ = 0;
				break;
			}
		} while (1);
	}


	if (zstate & ZST_ACQUIRED) {
		timer = BUS_TO;
		while (Z80_I_BUSACK == 1 && timer)
			;
		if (Z80_I_BUSACK == 0)
			z80_addrbus_set_out();
	}
}


/*

 +              |               |               |               |               |
    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
       +        |               |               |               |               |
          +     |       0       |       1       |       2       |       3       |
Event        +  |               |               |               |               |
----------------+---------------+---------------+---------------+---------------+
                |               |               |               |               |
Reset           |       0       |       0       |       0       |       0       |
                |               |               |               |               |
                |               |               |               |               |
Request         |       1       |               |       3       |               |
                |               |               |               |               |
                |               |               |               |               |
Release         |               |       0       |               |       2       |
                |               |               |               |               |
                |               |               |               |               |
Run             |       2       |       3       |               |               |
                |               |               |               |               |
                |               |               |               |               |
Restart         |               |               |       2       |       3       |
                |               |               |               |               |
                |               |               |               |               |
M_Cycle         |               |               |               |       3       |
                |               |               |               |               |
                |               |               |               |               |
*/

zstate_t z80_bus_cmd(bus_cmd_t cmd)
{
	switch (cmd) {

	case Reset:
		z80_dbus_set_in();
		z80_addrbus_set_in();
		Z80_O_RST = 0;
		Z80_O_BUSREQ = 1;
		zstate = RESET;
		break;

	case Request:
		switch (zstate) {
		case RESET:
			Z80_O_BUSREQ = 0;
			Z80_O_RST = 1;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_out();
				zstate = RESET_AQRD;
			} else {
				Z80_O_RST = 0;
				Z80_O_BUSREQ = 1;
			}
			break;

		case RUNNING:
			Z80_O_BUSREQ = 0;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_out();
				zstate = RUNNING_AQRD;
			} else {
				Z80_O_BUSREQ = 1;
			}
			break;

		default:
			break;
		}
		break;

	case Release:
		switch (zstate) {
		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			Z80_O_RST = 0;
			Z80_O_BUSREQ = 1;
			zstate = RESET;
			break;
		case RUNNING_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			Z80_O_BUSREQ = 1;
			zstate = RUNNING;
			break;
		default:
			break;
		}
		break;

	case Run:
		switch (zstate) {
		case RESET:
			Z80_O_RST = 1;
			zstate = RUNNING;
			break;

		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			z80_reset_pulse();
			z80_addrbus_set_out();
			zstate = RUNNING_AQRD;
			break;
		default:
			break;
		}
		break;

	case Restart:
		switch (zstate) {
		case RUNNING:
		case RUNNING_AQRD:
			z80_reset_pulse();
			break;
		default:
			break;
		}
		break;

	case M_Cycle:
		switch (zstate) {
		case RUNNING_AQRD:
			z80_busreq_hpulse();	/* TODO: */
			break;
		default:
			break;
		}
	}
	return zstate;
}


/*--------------------------------------------------------------------------*/

static
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
	P_ADL = addr;
	P_ADH = (addr & 0xff00) >> 8;
	PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
}

void z80_write(uint32_t addr, uint8_t data)
{
	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_out();
	P_DB = data;
	P_DB = data;
	Z80_O_WR = 0;
	Z80_O_WR = 0;
	Z80_O_WR = 1;
	Z80_O_MREQ = 1;
}

uint8_t z80_read(uint32_t addr)
{
	uint8_t data;

	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	data = PIN_DB;
	Z80_O_RD = 1;
	Z80_O_MREQ = 1;

	return data;
}


void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	P_DB = data;
	while(length--) {
		z80_setaddress(addr++);
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
{
	uint8_t data;

	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	while(length--) {
		z80_setaddress(src++);
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		data = PIN_DB;
		Z80_O_RD = 1;
		*dest++ = data;
	}
	Z80_O_MREQ = 1;
}


/*
  0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
  017A'                         rx.in_idx:	ds	1		;
  017B'                         rx.out_idx:	ds	1		;
  017C'                         rx.buf:		ds	rx.buf_len	;
  018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)

  018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
  018D'                         tx.in_idx:	ds	1		;
  018E'                         tx.out_idx:	ds	1		;
  018F'                         tx.buf:		ds	tx.buf_len 	;
  019E'                         tx.buf_end	equ	$-1		; last byte
*/


typedef struct __attribute__((packed)) {
	uint8_t mask;
	uint8_t in_idx;
	uint8_t out_idx;
	uint8_t buf[];
} zfifo_t;


#define FIFO_BUFSIZE_MASK	-3
#define FIFO_INDEX_IN		-2
#define FIFO_INDEX_OUT		-1


static struct {
	uint32_t base;
	uint8_t idx_out,
		idx_in,
		mask;
	} fifo_dsc[NUM_FIFOS];


void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
	fifo_dsc[f].base = addr;

DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);

	if (addr != 0) {
		z80_bus_cmd(Request);
		fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
}


int z80_memfifo_is_empty(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {

		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
		uint8_t idx;

		z80_bus_cmd(Request);
		idx = z80_read(adr);
		z80_bus_cmd(Release);
		rc = idx == fifo_dsc[f].idx_out;
	}

	return rc;
}

int z80_memfifo_is_full(const fifo_t f)
{
	int rc = 0;

	if (fifo_dsc[f].base != 0) {
		z80_bus_cmd(Request);
		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
	return rc;
}


uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
	uint8_t rc, idx;

	while (z80_memfifo_is_empty(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_out;
	rc = z80_read(fifo_dsc[f].base+idx);
	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	z80_bus_cmd(Release);

	return rc;
}

int z80_memfifo_getc(const fifo_t f)
{
	int rc = -1;

	if (fifo_dsc[f].base != 0) {
		uint8_t idx = fifo_dsc[f].idx_out;
		z80_bus_cmd(Request);
		if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
			rc = z80_read(fifo_dsc[f].base+idx);
			fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
			z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
		}
		z80_bus_cmd(Release);
	}

	return rc;
}


void z80_memfifo_putc(fifo_t f, uint8_t val)
{
	int idx;

	while (z80_memfifo_is_full(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_in;
	z80_write(fifo_dsc[f].base+idx, val);
	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
	z80_bus_cmd(Release);
}
Commit	Line	Data
35edb766 L	1	/*
	2	* (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
	3	*
a1595a8e	4	* SPDX-License-Identifier: GPL-2.0
35edb766 L	5	*/
35edb766 L	6
0c5890bb L	7	/**
	8	*
	9	* Pin assignments
	10	*
a1595a8e L	11	* \| Z180-Sig \| AVR-Port \| Dir \|
	12	* +------------+---------------+-------+
	13	* \| A0 \| PA 0 \| O \|
	14	* \| A1 \| PA 1 \| O \|
	15	* \| A2 \| PA 2 \| O \|
	16	* \| A3 \| PA 3 \| O \|
	17	* \| A4 \| PA 4 \| O \|
	18	* \| A5 \| PA 5 \| O \|
	19	* \| A6 \| PA 6 \| O \|
	20	* \| A7 \| PA 7 \| O \|
	21	* \| A8 \| PC 0 \| O \|
	22	* \| A9 \| PC 1 \| O \|
	23	* \| A10 \| PC 2 \| O \|
	24	* \| A11 \| PC 3 \| O \|
	25	* \| A12 \| PC 4 \| O \|
	26	* \| A13 \| PC 5 \| O \|
	27	* \| A14 \| PC 6 \| O \|
	28	* \| A15 \| PC 7 \| O \|
	29	* \| A16 \| PE 2 \| O \|
	30	* \| A17 \| PE 3 \| O \|
	31	* \| A18 \| PE 4 \| O \|
	32	* \| D0 \| PF 0 \| I/O \|
	33	* \| D1 \| PF 1 \| I/O \|
	34	* \| D2 \| PF 2 \| I/O \|
	35	* \| D3 \| PF 3 \| I/O \|
	36	* \| D4 \| PF 4 \| I/O \|
	37	* \| D5 \| PF 5 \| I/O \|
	38	* \| D6 \| PF 6 \| I/O \|
	39	* \| D7 \| PF 7 \| I/O \|
	40	* \| RD \| PD 3 \| O \|
	41	* \| WR \| PD 2 \| O \|
	42	* \| MREQ \| PD 4 \| O \|
	43	* \| RST \| PD 5 \| O \|
	44	* \| BUSREQ \| PD 7 \| O \|
	45	* \| BUSACK \| PD 6 \| I \|
	46	* \|
	47	* \| Optional
	48	* +------------------------------------+
	49	* \| STEP \| PG 0 \| O \|
	50	* \| RUN \| PG 1 \| O \|
	51	* \| WAIT \| PG 2 \| I \|
0c5890bb	52
0c5890bb L	53	*/
0c5890bb L	54
ea6971b8	55
a1595a8e	56	#include "z80-if.h"
f338df2a	57	#include <util/atomic.h>
0c5890bb	58	#include "debug.h"
a1595a8e L	59	#include "config.h"
a1595a8e L	60	#include "env.h"
0c5890bb	61
0c5890bb	62
41d36f28 L	63	//#define P_ZCLK PORTB
	64	//#define ZCLK 5
	65	//#define DDR_ZCLK DDRB
0c5890bb L	66	#define P_MREQ PORTD
	67	#define MREQ 4
	68	#define DDR_MREQ DDRD
	69	#define P_RD PORTD
	70	#define RD 3
	71	#define P_WR PORTD
	72	#define WR 2
	73	#define P_BUSREQ PORTD
	74	#define BUSREQ 7
	75	#define DDR_BUSREQ DDRD
	76	#define P_BUSACK PORTD
9b6b4b31	77	#define PIN_BUSACK PIND
0c5890bb L	78	#define BUSACK 6
0c5890bb L	79	#define DDR_BUSACK DDRD
0c5890bb L	80	#define P_RST PORTD
	81	#define DDR_RST DDRD
	82	#define RST 5
	83
	84
	85	#define P_DB PORTF
	86	#define PIN_DB PINF
	87	#define DDR_DB DDRF
	88
	89	#define P_ADL PORTA
	90	#define P_ADH PORTC
	91	#define P_ADB PORTE
	92	#define PIN_ADB PINE
9b6b4b31 L	93	#define DDR_ADL DDRA
9b6b4b31 L	94	#define DDR_ADH DDRC
0c5890bb L	95	#define DDR_ADB DDRE
	96
	97	#define ADB_WIDTH 3
	98	#define ADB_SHIFT 2
	99	//#define ADB_PORT PORTE
	100
	101
41d36f28	102	//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
0c5890bb L	103	#define Z80_O_MREQ SBIT(P_MREQ, 4)
	104	#define Z80_O_RD SBIT(P_RD, 3)
	105	#define Z80_O_WR SBIT(P_WR, 2)
	106	#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
	107	//#define Z80_O_NMI SBIT(P_NMI, )
	108	#define Z80_O_RST SBIT(P_RST, 5)
9b6b4b31	109	#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
0c5890bb L	110	//#define Z80_I_HALT SBIT(P_HALT, )
0c5890bb L	111
a1595a8e L	112	/* Optional */
	113	#define P_RUN PORTG
	114	#define RUN 1
	115	#define DDR_RUN DDRG
	116	#define P_STEP PORTG
	117	#define STEP 0
	118	#define DDR_STEP DDRG
	119	#define P_WAIT PORTG
	120	#define WAIT 2
	121	#define DDR_WAIT DDRG
	122	/* All three signals are on the same Port (PortG) */
	123	#define PORT_SS PORTG
	124	#define DDR_SS DDRG
	125	#define PIN_SS PING
	126	#define Z80_O_RUN SBIT(PORT_SS, RUN)
	127	#define Z80_O_STEP SBIT(PORT_SS, STEP)
	128	#define Z80_I_WAIT SBIT(PORT_SS, WAIT)
	129
9b6b4b31	130
ea6971b8 L	131	#define BUS_TO 20
	132
	133
0c5890bb L	134	#define MASK(n) ((1<<(n))-1)
	135	#define SMASK(w,s) (MASK(w) << (s))
	136
0c5890bb	137
f338df2a	138	static zstate_t zstate;
ea6971b8 L	139	static volatile uint8_t timer; /* used for bus timeout */
	140
	141	/---------------------------------------------------------/
	142	/* 10Hz timer interrupt generated by OC4A */
	143	/---------------------------------------------------------/
	144
a1595a8e	145	ISR(TIMER5_COMPA_vect)
ea6971b8 L	146	{
	147
	148	uint8_t i = timer;
	149
	150	if (i)
	151	timer = i - 1;
	152	}
eded7ec4	153
0c5890bb L	154	/--------------------------------------------------------------------------/
0c5890bb L	155
6035a17b	156
a1595a8e	157	static void z80_addrbus_set_in(void)
0c5890bb	158	{
9b6b4b31 L	159	/* /MREQ, /RD, /WR: Input, no pullup */
	160	DDR_MREQ &= ~(_BV(MREQ) \| _BV(RD) \| _BV(WR));
	161	Z80_O_MREQ = 0;
	162	Z80_O_RD = 0;
	163	Z80_O_WR = 0;
	164
0c5890bb L	165	P_ADL = 0;
	166	DDR_ADL = 0;
	167	P_ADH = 0;
	168	DDR_ADH = 0;
6353e862	169	PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
0c5890bb L	170	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	171	}
	172
54678798	173
a1595a8e	174	static void z80_addrbus_set_out(void)
0c5890bb	175	{
9b6b4b31 L	176	/* /MREQ, /RD, /WR: Output and high */
	177	Z80_O_MREQ = 1;
	178	Z80_O_RD = 1;
	179	Z80_O_WR = 1;
	180	DDR_MREQ \|= _BV(MREQ) \| _BV(RD) \| _BV(WR);
	181
0c5890bb L	182	DDR_ADL = 0xff;
	183	DDR_ADH = 0xff;
	184	DDR_ADB = DDR_ADB \| (MASK(ADB_WIDTH) << ADB_SHIFT);
	185	}
	186
	187
6035a17b	188	static void z80_dbus_set_in(void)
0c5890bb L	189	{
	190	DDR_DB = 0;
	191	P_DB = 0;
	192	}
	193
62f624d3	194
6035a17b	195	static void z80_dbus_set_out(void)
0c5890bb L	196	{
	197	DDR_DB = 0xff;
	198	}
	199
62f624d3 L	200
	201	static void z80_reset_pulse(void)
	202	{
	203	Z80_O_RST = 0;
	204	_delay_us(10);
	205	Z80_O_RST = 1;
	206	}
	207
	208
0c5890bb L	209	void z80_setup_bus(void)
0c5890bb L	210	{
a1595a8e L	211	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
	212
	213	/* /ZRESET: Output and low */
	214	Z80_O_RST = 0;
	215	DDR_RST \|= _BV(RST);
0c5890bb	216
a1595a8e L	217	/* /BUSREQ: Output and high */
	218	Z80_O_BUSREQ = 1;
	219	DDR_BUSREQ \|= _BV(BUSREQ);
0c5890bb	220
a1595a8e L	221	/* /BUSACK: Input, no pullup */
	222	DDR_BUSACK &= ~_BV(BUSACK);
	223	P_BUSACK &= ~_BV(BUSACK);
0c5890bb	224
a1595a8e L	225	z80_addrbus_set_in();
a1595a8e L	226	z80_dbus_set_in();
0c5890bb	227
a1595a8e L	228	if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
a1595a8e L	229	/* /RUN & /STEP: output, /WAIT: input */
72f58822	230
a1595a8e L	231	PORT_SS = (PORT_SS & ~_BV(RUN)) \| _BV(STEP);
	232	DDR_SS = (DDR_SS & ~_BV(WAIT)) \| _BV(RUN) \| _BV(STEP);
	233	}
	234
	235	zstate = RESET;
	236	}
ea6971b8	237
a1595a8e L	238	/* Timer 5 */
	239	PRR1 &= ~_BV(PRTIM5);
	240	OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
	241	TCCR5B = (0b01<<WGM52)\|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
	242	TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */
ea6971b8	243
0c5890bb L	244	}
0c5890bb L	245
f338df2a	246
62f624d3	247	zstate_t z80_bus_state(void)
f338df2a L	248	{
	249	return zstate;
	250	}
	251
62f624d3 L	252
62f624d3 L	253	static void z80_busreq_hpulse(void)
0c5890bb	254	{
6035a17b	255	z80_dbus_set_in();
a1595a8e	256	z80_addrbus_set_in();
72f58822	257
a1595a8e	258	#if 0
8a7decea	259	ATOMIC_BLOCK(ATOMIC_FORCEON) {
62f624d3 L	260	Z80_O_BUSREQ = 1;
	261	Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
	262	Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
f338df2a	263	}
a1595a8e L	264	#endif
	265
	266	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	267	Z80_O_BUSREQ = 1;
	268
	269	do {
	270	if (Z80_I_BUSACK == 1) {
	271	Z80_O_BUSREQ = 0;
	272	break;
	273	}
	274	} while (1);
	275	}
	276
72f58822	277
62f624d3	278	if (zstate & ZST_ACQUIRED) {
ea6971b8 L	279	timer = BUS_TO;
ea6971b8 L	280	while (Z80_I_BUSACK == 1 && timer)
f338df2a	281	;
ea6971b8	282	if (Z80_I_BUSACK == 0)
a1595a8e	283	z80_addrbus_set_out();
f338df2a	284	}
f338df2a L	285	}
f338df2a L	286
f338df2a L	287
f338df2a L	288	/*
f338df2a	289
ea6971b8	290	+ \| \| \| \| \|
62f624d3	291	+ State \| RESET \| RESET_AQRD \| RUNNING \| RUNNING_AQRD \|
ea6971b8 L	292	+ \| \| \| \| \|
	293	+ \| 0 \| 1 \| 2 \| 3 \|
	294	Event + \| \| \| \| \|
62f624d3	295	----------------+---------------+---------------+---------------+---------------+
ea6971b8 L	296	\| \| \| \| \|
	297	Reset \| 0 \| 0 \| 0 \| 0 \|
	298	\| \| \| \| \|
	299	\| \| \| \| \|
	300	Request \| 1 \| \| 3 \| \|
	301	\| \| \| \| \|
	302	\| \| \| \| \|
	303	Release \| \| 0 \| \| 2 \|
	304	\| \| \| \| \|
	305	\| \| \| \| \|
	306	Run \| 2 \| 3 \| \| \|
	307	\| \| \| \| \|
	308	\| \| \| \| \|
	309	Restart \| \| \| 2 \| 3 \|
	310	\| \| \| \| \|
	311	\| \| \| \| \|
	312	M_Cycle \| \| \| \| 3 \|
	313	\| \| \| \| \|
	314	\| \| \| \| \|
62f624d3	315	*/
f338df2a	316
62f624d3	317	zstate_t z80_bus_cmd(bus_cmd_t cmd)
f338df2a	318	{
62f624d3	319	switch (cmd) {
f338df2a	320
62f624d3	321	case Reset:
6035a17b	322	z80_dbus_set_in();
a1595a8e	323	z80_addrbus_set_in();
f338df2a	324	Z80_O_RST = 0;
62f624d3 L	325	Z80_O_BUSREQ = 1;
62f624d3 L	326	zstate = RESET;
f338df2a L	327	break;
f338df2a L	328
62f624d3 L	329	case Request:
	330	switch (zstate) {
	331	case RESET:
	332	Z80_O_BUSREQ = 0;
	333	Z80_O_RST = 1;
ea6971b8 L	334	timer = BUS_TO;
ea6971b8 L	335	while (Z80_I_BUSACK == 1 && timer)
62f624d3	336	;
ea6971b8	337	if (Z80_I_BUSACK == 0) {
a1595a8e	338	z80_addrbus_set_out();
ea6971b8 L	339	zstate = RESET_AQRD;
	340	} else {
	341	Z80_O_RST = 0;
	342	Z80_O_BUSREQ = 1;
	343	}
62f624d3 L	344	break;
	345
	346	case RUNNING:
	347	Z80_O_BUSREQ = 0;
ea6971b8 L	348	timer = BUS_TO;
ea6971b8 L	349	while (Z80_I_BUSACK == 1 && timer)
62f624d3	350	;
ea6971b8	351	if (Z80_I_BUSACK == 0) {
a1595a8e	352	z80_addrbus_set_out();
ea6971b8 L	353	zstate = RUNNING_AQRD;
	354	} else {
	355	Z80_O_BUSREQ = 1;
	356	}
62f624d3 L	357	break;
	358
	359	default:
	360	break;
	361	}
f338df2a	362	break;
f338df2a	363
62f624d3 L	364	case Release:
	365	switch (zstate) {
	366	case RESET_AQRD:
6035a17b	367	z80_dbus_set_in();
a1595a8e	368	z80_addrbus_set_in();
62f624d3 L	369	Z80_O_RST = 0;
	370	Z80_O_BUSREQ = 1;
	371	zstate = RESET;
	372	break;
	373	case RUNNING_AQRD:
6035a17b	374	z80_dbus_set_in();
a1595a8e	375	z80_addrbus_set_in();
62f624d3 L	376	Z80_O_BUSREQ = 1;
	377	zstate = RUNNING;
	378	break;
	379	default:
	380	break;
	381	}
	382	break;
f338df2a	383
62f624d3 L	384	case Run:
	385	switch (zstate) {
	386	case RESET:
	387	Z80_O_RST = 1;
	388	zstate = RUNNING;
	389	break;
	390
	391	case RESET_AQRD:
6035a17b	392	z80_dbus_set_in();
a1595a8e	393	z80_addrbus_set_in();
62f624d3	394	z80_reset_pulse();
a1595a8e	395	z80_addrbus_set_out();
62f624d3 L	396	zstate = RUNNING_AQRD;
	397	break;
	398	default:
	399	break;
	400	}
	401	break;
f338df2a	402
62f624d3 L	403	case Restart:
	404	switch (zstate) {
	405	case RUNNING:
	406	case RUNNING_AQRD:
	407	z80_reset_pulse();
	408	break;
	409	default:
	410	break;
	411	}
	412	break;
f338df2a	413
62f624d3 L	414	case M_Cycle:
	415	switch (zstate) {
	416	case RUNNING_AQRD:
ea6971b8	417	z80_busreq_hpulse(); /* TODO: */
62f624d3 L	418	break;
	419	default:
	420	break;
	421	}
f338df2a	422	}
62f624d3	423	return zstate;
9b6b4b31 L	424	}
9b6b4b31 L	425
62f624d3	426
9b6b4b31 L	427	/--------------------------------------------------------------------------/
9b6b4b31 L	428
54678798	429	static
9b6b4b31 L	430	//inline __attribute__ ((always_inline))
	431	void z80_setaddress(uint32_t addr)
	432	{
a1595a8e L	433	P_ADL = addr;
	434	P_ADH = (addr & 0xff00) >> 8;
	435	PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
0c5890bb L	436	}
	437
	438	void z80_write(uint32_t addr, uint8_t data)
	439	{
	440	z80_setaddress(addr);
	441	Z80_O_MREQ = 0;
6035a17b	442	z80_dbus_set_out();
9b6b4b31 L	443	P_DB = data;
	444	P_DB = data;
	445	Z80_O_WR = 0;
0c5890bb L	446	Z80_O_WR = 0;
	447	Z80_O_WR = 1;
	448	Z80_O_MREQ = 1;
	449	}
	450
	451	uint8_t z80_read(uint32_t addr)
	452	{
	453	uint8_t data;
	454
	455	z80_setaddress(addr);
	456	Z80_O_MREQ = 0;
6035a17b	457	z80_dbus_set_in();
0c5890bb L	458	Z80_O_RD = 0;
0c5890bb L	459	Z80_O_RD = 0;
9b6b4b31	460	Z80_O_RD = 0;
0c5890bb L	461	data = PIN_DB;
	462	Z80_O_RD = 1;
	463	Z80_O_MREQ = 1;
	464
	465	return data;
	466	}
	467
	468
	469	void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
	470	{
6035a17b	471	z80_dbus_set_out();
0c5890bb	472	Z80_O_MREQ = 0;
ea6971b8	473	P_DB = data;
0c5890bb L	474	while(length--) {
0c5890bb L	475	z80_setaddress(addr++);
ea6971b8 L	476	Z80_O_WR = 0;
	477	Z80_O_WR = 0;
	478	Z80_O_WR = 1;
	479	}
	480	Z80_O_MREQ = 1;
	481	}
	482
	483	void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
	484	{
	485	uint8_t data;
	486
	487	z80_dbus_set_out();
	488	Z80_O_MREQ = 0;
	489	while(length--) {
	490	z80_setaddress(dest++);
	491	data = *src++;
0c5890bb	492	P_DB = data;
9b6b4b31 L	493	P_DB = data;
9b6b4b31 L	494	Z80_O_WR = 0;
0c5890bb L	495	Z80_O_WR = 0;
	496	Z80_O_WR = 1;
	497	}
	498	Z80_O_MREQ = 1;
	499	}
	500
ea6971b8	501	void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
0c5890bb L	502	{
0c5890bb L	503	uint8_t data;
54678798	504
6035a17b	505	z80_dbus_set_out();
0c5890bb L	506	Z80_O_MREQ = 0;
	507	while(length--) {
	508	z80_setaddress(dest++);
	509	data = *src++;
	510	P_DB = data;
9b6b4b31 L	511	P_DB = data;
9b6b4b31 L	512	Z80_O_WR = 0;
0c5890bb L	513	Z80_O_WR = 0;
	514	Z80_O_WR = 1;
	515	}
	516	Z80_O_MREQ = 1;
	517	}
	518
ea6971b8 L	519	void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
	520	{
	521	uint8_t data;
	522
	523	Z80_O_MREQ = 0;
	524	z80_dbus_set_in();
	525	while(length--) {
	526	z80_setaddress(src++);
	527	Z80_O_RD = 0;
	528	Z80_O_RD = 0;
	529	Z80_O_RD = 0;
	530	data = PIN_DB;
	531	Z80_O_RD = 1;
	532	*dest++ = data;
	533	}
	534	Z80_O_MREQ = 1;
	535	}
	536
	537
0c5890bb L	538	/*
	539	0179' rx.bs_mask: ds 1 ; (buf_len - 1)
	540	017A' rx.in_idx: ds 1 ;
	541	017B' rx.out_idx: ds 1 ;
	542	017C' rx.buf: ds rx.buf_len ;
	543	018B' rx.buf_end equ $-1 ; last byte (start+len-1)
54678798	544
0c5890bb L	545	018C' tx.bs_mask: ds 1 ; (buf_len - 1)
	546	018D' tx.in_idx: ds 1 ;
	547	018E' tx.out_idx: ds 1 ;
	548	018F' tx.buf: ds tx.buf_len ;
	549	019E' tx.buf_end equ $-1 ; last byte
	550	*/
	551
	552
	553	typedef struct __attribute__((packed)) {
	554	uint8_t mask;
	555	uint8_t in_idx;
	556	uint8_t out_idx;
	557	uint8_t buf[];
	558	} zfifo_t;
	559
	560
	561
	562	#define FIFO_BUFSIZE_MASK -3
	563	#define FIFO_INDEX_IN -2
	564	#define FIFO_INDEX_OUT -1
	565
	566
	567	static struct {
	568	uint32_t base;
	569	uint8_t idx_out,
	570	idx_in,
	571	mask;
	572	} fifo_dsc[NUM_FIFOS];
54678798	573
0c5890bb	574
8a7decea	575	void z80_memfifo_init(const fifo_t f, uint32_t addr)
0c5890bb	576	{
8a7decea	577	fifo_dsc[f].base = addr;
0c5890bb	578
8a7decea	579	DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
0c5890bb	580
bbd45c46	581	if (addr != 0) {
8a7decea L	582	z80_bus_cmd(Request);
	583	fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
	584	fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
	585	fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
	586	z80_bus_cmd(Release);
	587	}
0c5890bb L	588	}
	589
	590
	591	int z80_memfifo_is_empty(const fifo_t f)
	592	{
	593	int rc = 1;
	594
89adce76	595	if (fifo_dsc[f].base != 0) {
0c5890bb L	596
	597	uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
	598	uint8_t idx;
	599
62f624d3	600	z80_bus_cmd(Request);
0c5890bb	601	idx = z80_read(adr);
62f624d3	602	z80_bus_cmd(Release);
0c5890bb L	603	rc = idx == fifo_dsc[f].idx_out;
	604	}
	605
	606	return rc;
	607	}
	608
	609	int z80_memfifo_is_full(const fifo_t f)
	610	{
ce47d431	611	int rc = 0;
54678798	612
0c5890bb	613	if (fifo_dsc[f].base != 0) {
62f624d3	614	z80_bus_cmd(Request);
0c5890bb L	615	rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
0c5890bb L	616	== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
62f624d3	617	z80_bus_cmd(Release);
0c5890bb L	618	}
	619	return rc;
	620	}
	621
89adce76 L	622
89adce76 L	623	uint8_t z80_memfifo_getc_wait(const fifo_t f)
0c5890bb L	624	{
0c5890bb L	625	uint8_t rc, idx;
54678798	626
0c5890bb L	627	while (z80_memfifo_is_empty(f))
	628	;
	629
62f624d3	630	z80_bus_cmd(Request);
0c5890bb L	631	idx = fifo_dsc[f].idx_out;
	632	rc = z80_read(fifo_dsc[f].base+idx);
	633	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	634	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
62f624d3	635	z80_bus_cmd(Release);
54678798	636
0c5890bb L	637	return rc;
	638	}
	639
89adce76 L	640	int z80_memfifo_getc(const fifo_t f)
	641	{
	642	int rc = -1;
	643
	644	if (fifo_dsc[f].base != 0) {
	645	uint8_t idx = fifo_dsc[f].idx_out;
	646	z80_bus_cmd(Request);
	647	if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
	648	rc = z80_read(fifo_dsc[f].base+idx);
	649	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	650	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	651	}
	652	z80_bus_cmd(Release);
	653	}
	654
	655	return rc;
	656	}
	657
0c5890bb L	658
	659	void z80_memfifo_putc(fifo_t f, uint8_t val)
	660	{
	661	int idx;
54678798	662
0c5890bb L	663	while (z80_memfifo_is_full(f))
	664	;
	665
62f624d3	666	z80_bus_cmd(Request);
0c5890bb L	667	idx = fifo_dsc[f].idx_in;
	668	z80_write(fifo_dsc[f].base+idx, val);
	669	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	670	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
62f624d3	671	z80_bus_cmd(Release);
0c5890bb	672	}