switch fifos conin,conout

[z180-stamp.git] / avr / z180-serv.c

/*
 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "common.h"
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include <util/atomic.h>

#include "background.h"
#include "env.h"
#include "ff.h"
#include "serial.h"
#include "z80-if.h"
#include "debug.h"
#include "print-utils.h"
#include "z180-serv.h"
#include "timer.h"


#define DEBUG_CPM_SDIO	0	/* set to 1 to debug */

#define debug_cpmsd(fmt, args...)		                                            \
	debug_cond(DEBUG_CPM_SDIO, fmt, ##args)



/*--------------------------------------------------------------------------*/


uint8_t z80_get_byte(uint32_t adr)
{
	uint8_t data;

	z80_bus_cmd(Request);
	data = z80_read(adr);
	z80_bus_cmd(Release);

	return data;
}


/*--------------------------------------------------------------------------*/

struct msg_item {
	uint8_t fct;
	uint8_t sub_min, sub_max;
	void (*func)(uint8_t, int, uint8_t *);
};

uint32_t msg_to_addr(uint8_t *msg)
{
	union {
		uint32_t as32;
		uint8_t as8[4];
	} addr;

	addr.as8[0] = msg[0];
	addr.as8[1] = msg[1];
	addr.as8[2] = msg[2];
	addr.as8[3] = 0;

	return addr.as32;
}


static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
{
	z80_memfifo_putc(fifo_msgout, 0xAE);
	z80_memfifo_putc(fifo_msgout, len+2);
	z80_memfifo_putc(fifo_msgout, func);
	z80_memfifo_putc(fifo_msgout, subf);

	return 0;
}

int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
{
	msg_xmit_header(func, subf, len);
	while (len--)
		z80_memfifo_putc(fifo_msgout, *msg++);

	return 0;
}

void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
{
	(void)len;

	z80_memfifo_init(subf, msg_to_addr(msg));
}


void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	while (len--)
		putchar(*msg++);
}

/* echo message */
void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	/* send re-echo */
	msg_xmit(1, 3, len, msg);
}

/* get timer */
void do_msg_get_timer(uint8_t subf, int len, uint8_t * msg)
{
	uint32_t time_ms = (len >= 4) ? *(uint32_t *) msg : 0;

	time_ms = get_timer(time_ms);
	msg_xmit(3, subf, sizeof(time_ms), (uint8_t *) &time_ms);
}

/* ---------------------------------------------------------------------------*/

#define MAX_DRIVE	4
#define BLOCK_SIZE	512
#define TPA_BASE	0x10000
#define COMMON_BASE	0xC000

struct cpm_drive_s {
	uint8_t drv;
	uint8_t device;
	char *img_name;
	bool dirty;
	FIL fd;
};

static uint8_t disk_buffer[BLOCK_SIZE];
static struct cpm_drive_s drv_table[MAX_DRIVE];
static int handle_cpm_drv_to;

#define f_dirty(fp) ((fp)->fs->wflag != 0)


int cpm_drv_to(int state)
{
	static uint32_t ts;

	switch(state) {
	case 0:
		break;

	case 1:
		ts = get_timer(0);
		state = 2;
		break;

	case 2:
		if (get_timer(ts) > 1000) {
			for (uint_fast8_t i=0; i < MAX_DRIVE; i++) {
//				if (&drv_table[i].fd && f_dirty(&drv_table[i].fd)) {
				if (drv_table[i].dirty) {
					f_sync(&drv_table[i].fd);
					drv_table[i].dirty = false;
					debug_cpmsd("## %7lu f_sync: %c:\n", get_timer(0), i+'A');
				}
			}
			state = 0;
		}
	}
	return state;
}


void msg_cpm_result(uint8_t subf, uint8_t rc, int res)
{
	uint8_t result_msg[3];

	if (res)
		rc |= 0x80;

	result_msg[0] = rc;
	result_msg[1] = res;
	result_msg[2] = res >> 8;

	if (rc) {
		debug_cpmsd("###%7lu  error rc: %.02x, res: %d\n", get_timer(0), rc, res);
	}

	msg_xmit(2, subf, sizeof(result_msg), result_msg);
}

/*
 	db	2	; disk command
	ds	1	; subcommand (login/read/write)
	ds	1	; @adrv (8 bits)	+0
	ds	1	; @rdrv (8 bits)	+1
	ds	3	; @xdph (24 bits)	+2
*/

void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
{

	FRESULT res = 0;
	uint8_t drv;
	char *np;

	(void)subf;

	if (len != 5) {     /* TODO: check adrv, rdrv */
		return msg_cpm_result(subf, 0x01, res);
	}

	debug_cpmsd("\n## %7lu  login: %c:\n", get_timer(0), msg[0]+'A');


	drv = msg[0];
	if ( drv>= MAX_DRIVE) {
		return msg_cpm_result(subf, 0x02, res);
	}

/*
	uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
*/

	if (drv_table[drv].img_name != NULL) {
		debug_cpmsd("## %7lu  close: '%s'\n", get_timer(0), drv_table[drv].img_name);
		f_close(&drv_table[drv].fd);
		drv_table[drv].dirty = false;
		free(drv_table[drv].img_name);
		drv_table[drv].img_name = NULL;
	}

	strcpy_P((char *)disk_buffer, PSTR("dsk0"));
	disk_buffer[3] = msg[0] + '0';
	if (((np = getenv((char*)disk_buffer)) == NULL) ||
			((drv_table[drv].img_name = strdup(np)) == NULL)) {
		return msg_cpm_result(subf, 0x03, res);
	}


	res = f_open(&drv_table[drv].fd, drv_table[drv].img_name,
			FA_WRITE | FA_READ);

    debug_cpmsd("## %7lu   open: '%s', (env: '%s'), res: %d\n", get_timer(0),
			drv_table[drv].img_name, disk_buffer, res);

	/* send  result*/
	msg_cpm_result(subf, 0x00, res);
}


/*
 	db	2	; disk command
	ds	1	; subcommand (login/read/write)
	ds	1	; @adrv (8 bits)		+0
	ds	1	; @rdrv (8 bits)		+1
	ds	2	; @trk (16 bits)		+2
	ds	2	; @sect(16 bits)		+4
	ds	1	; @cnt  (8 bits)		+6
	ds	3	; phys. transfer addr	+7
*/

#define ADRV	0
#define RDRV	1
#define TRK		2
#define SEC		4
#define CNT		6
#define ADDR	7

void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
{
	uint8_t drv;
	uint32_t addr;
	uint32_t pos;
	uint8_t secs;
	bool dowrite = (subf == 2);
	FRESULT res = 0;
	uint8_t rc = 0;
	bool buserr = 0;

	if (len != 10) {     /* TODO: check adrv, rdrv */
		return msg_cpm_result(subf, 0x01, res);
	}

	drv = msg[ADRV];
	if ( drv>= MAX_DRIVE) {
		return msg_cpm_result(subf, 0x02, res);
	}

	secs = msg[CNT];
	addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];


	/* TODO: tracks per sector from dpb */
	pos = (((uint16_t)(msg[TRK+1] << 8) + msg[TRK]) * 8
			+ ((uint32_t)(msg[SEC+1] << 8) + msg[SEC])) * BLOCK_SIZE;

	debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
			"addr: %.5lx\n", get_timer(0), dowrite ? "write" : " read",
			msg[ADRV]+'A', ((uint16_t)(msg[TRK+1] << 8) + msg[TRK]), msg[SEC],
			pos, msg[CNT], addr);

	res = f_lseek(&drv_table[drv].fd, pos);
	while (!res && secs--) {
		unsigned int cnt, br;

		/* check bank boundary crossing */
		cnt = 0;
		if (addr < (TPA_BASE + COMMON_BASE) &&
					(addr + BLOCK_SIZE) > (TPA_BASE + COMMON_BASE)) {
			cnt = (TPA_BASE + COMMON_BASE) - addr;
		}

		if (cnt) {
			debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr, cnt);
			debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr+cnt-TPA_BASE, BLOCK_SIZE-cnt);
		}

		if (dowrite) {
			if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
				buserr = 1;
				break;
			} else {
				if (cnt) {
					z80_read_block(disk_buffer, addr, cnt);
					addr = addr + cnt - TPA_BASE;
				}
				z80_read_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
				z80_bus_cmd(Release);
			}
			res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
		} else {
			res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
			if (res == FR_OK && br == BLOCK_SIZE) {
				if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
					buserr = 1;
					break;
				} else {
					if (cnt) {
						z80_write_block(disk_buffer, addr, cnt);
						addr = addr + cnt - TPA_BASE;
					}
					z80_write_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
					z80_bus_cmd(Release);
				}
			}
		}

		if (br != BLOCK_SIZE) {
			debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, br);
			dump_ram(disk_buffer, 0, 64, "Read Data");
			res = -1;
		}

		addr += BLOCK_SIZE;
	}

	if (dowrite && !res) {
//		res = f_sync(&drv_table[drv].fd);
		drv_table[drv].dirty = true;
		bg_setstat(handle_cpm_drv_to, 1);
	}


	if (buserr) {
		debug_cpmsd("Bus timeout\n");
		rc = 0x03;
	}

	/* send  result*/
	msg_cpm_result(subf, rc, res);
}


const FLASH struct msg_item z80_messages[] =
{
	{ 0,			/* fct nr. */
	  1, 3,			/* sub fct nr. from, to */
	  do_msg_ini_memfifo},
	{ 1,
	  1, 1,
	  do_msg_char_out},
	{ 1,
	  2, 2,
	  do_msg_echo},
	{ 2,
	  0, 0,
	  do_msg_cpm_login},
	{ 2,
	  1, 2,
	  do_msg_cpm_rw},
	{ 3,
	  1, 1,
	  do_msg_get_timer},
	{ 0xff,				/* end mark */
	  0, 0,
	  0},

};




void do_message(int len, uint8_t *msg)
{
	uint8_t fct, sub_fct;
	int_fast8_t i = 0;

	if (len >= 2) {
		fct = *msg++;
		sub_fct = *msg++;
		len -= 2;

		while (fct != z80_messages[i].fct) {
			if (z80_messages[i].fct == 0xff) {
				DBG_P(1, "do_message: Unknown function: %i, %i\n",
						fct, sub_fct);
				return; /* TODO: unknown message # */
			}

			++i;
		}

		while (fct == z80_messages[i].fct) {
			if (sub_fct >= z80_messages[i].sub_min &&
					sub_fct <= z80_messages[i].sub_max )
				break;
			++i;
		}

		if (z80_messages[i].fct != fct) {
			DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
					fct, sub_fct);
			return; /* TODO: unknown message sub# */
		}

		(z80_messages[i].func)(sub_fct, len, msg);


	} else {
		/* TODO: error */
		DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
	}
}



#define CTRBUF_LEN 256

void check_msg_fifo(void)
{
	int ch;
	static int_fast8_t state;
	static int msglen,idx;
	static uint8_t buffer[CTRBUF_LEN];

	while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
		switch (state) {
		case 0:		/* wait for start of message */
			if (ch == 0xAE)	{ /* TODO: magic number */
				msglen = 0;
				idx = 0;
				state = 1;
			}
			break;
		case 1:		/* get msg len */
			if (ch > 0 && ch <= CTRBUF_LEN) {
				msglen = ch;
				state = 2;
			} else
				state = 0;
			break;
		case 2: 	/* get message */
			buffer[idx++] = ch;
			if (idx == msglen) {
				do_message(msglen, buffer);
				state = 0;
			}
			break;
		}
	}
}


int msg_handling(int state)
{
	uint8_t pending;

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		pending = (Stat & S_MSG_PENDING) != 0;
		Stat &= ~S_MSG_PENDING;
	}
/*
 * TODO: if pending but no message chr --> special condition. ie init,...
 */

	if (pending) {
		switch (state) {
		case 0:			/* need init */
			/* Get address of fifo_list */
			z80_bus_cmd(Request);
			uint32_t fifo_list = z80_read(0x40) +
				((uint16_t) z80_read(0x41) << 8) +
				((uint32_t) z80_read(0x42) << 16);
			z80_bus_cmd(Release);
			if (fifo_list != 0) {
				/* Get address of fifo 0 */
				z80_bus_cmd(Request);
				uint32_t fifo_addr = z80_read(fifo_list) +
					((uint16_t) z80_read(fifo_list+1) << 8) +
					((uint32_t) z80_read(fifo_list+2) << 16);
				z80_bus_cmd(Release);
				if (fifo_addr != 0) {
					z80_memfifo_init(fifo_msgin, fifo_addr);
					state = 1;
				}
			}
			break;
		case 1:			/* awaiting messages */
			check_msg_fifo();
			break;
		}
	}

	return state;
}


static int handle_msg_handling;

void setup_z180_serv(void)
{

	handle_msg_handling = bg_register(msg_handling, 0);
	handle_cpm_drv_to = bg_register(cpm_drv_to, 0);
}

void restart_z180_serv(void)
{
	z80_bus_cmd(Request);
	z80_write(0x40, 0);
	z80_write(0x41, 0);
	z80_write(0x42, 0);
	z80_bus_cmd(Release);

	for (int i = 0; i < NUM_FIFOS; i++)
		z80_memfifo_init(i, 0);
	bg_setstat(handle_msg_handling, 0);

}

/*--------------------------------------------------------------------------*/

const FLASH uint8_t iniprog[] = {
	0xAF,			// xor     a
	0xED, 0x39, 0x36,	// out0    (rcr),a         ;disable  DRAM refresh
	0x3E, 0x30,		// ld      a,030h
	0xED, 0x39, 0x32	//out0    (dcntl),a       ;0 mem, max i/0 wait states
};

const FLASH uint8_t sertest[] = {
	0xAF,              //  	xor	a
	0xED, 0x39, 0x36,  //  	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //  	ld	a,030h
	0xED, 0x39, 0x32,  //  	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x3E, 0x80,        //  	ld	a,M_MPBT		;no MP, PS=10, DR=16, SS=0
	0xED, 0x39, 0x03,  //  	out0	(cntlb1),a
	0x3E, 0x64,        //  	ld	a,M_RE + M_TE + M_MOD2	;
	0xED, 0x39, 0x01,  //  	out0	(cntla1),a
	0x3E, 0x00,        //  	ld	a,0
	0xED, 0x39, 0x05,  //  	out0	(stat1),a	;Enable rx interrupts
	0xED, 0x38, 0x05,  //l0:in0	a,(stat1)
	0xE6, 0x80,        //  	and	80h
	0x28, 0xF9,        //  	jr	z,l0
	0xED, 0x00, 0x09,  //  	in0	b,(rdr1)
	0xED, 0x38, 0x05,  //l1:in0	a,(stat1)
	0xE6, 0x02,        //  	and	02h
	0x28, 0xF9,        //  	jr	z,l1
	0xED, 0x01, 0x07,  //  	out0	(tdr1),b
	0x18, 0xEA,        //  	jr	l0
};

const FLASH uint8_t test1[] = {
	0xAF,              //	xor	a
	0xED, 0x39, 0x36,  //	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //	ld	a,030h
	0xED, 0x39, 0x32,  //	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x21, 0x1E, 0x00,  // 	ld	hl,dmclrt	;load DMA registers
	0x06, 0x08,        //	ld	b,dmct_e-dmclrt
	0x0E, 0x20,        //	ld	c,sar0l
	0xED, 0x93,        //	otimr
	0x3E, 0xC3,        //	ld	a,0c3h		;dst +1, src +1, burst
	0xED, 0x39, 0x31,  //	out0	(dmode),a	;
	0x3E, 0x62,        //	ld	a,062h		;enable dma0,
	0xED, 0x39, 0x30,  //cl_1:	out0	(dstat),a	;copy 64k
	0x18, 0xFB,        //	jr	cl_1		;
	0x00, 0x00,        //dmclrt:	dw	0		;src (inc)
	0x00,              //	db 	0		;src
	0x00, 0x00,        //	dw	0		;dst (inc),
	0x00,              //	db	0		;dst
	0x00, 0x00,        //	dw 	0		;count (64k)
};