[z180-stamp.git] / avr / z180-serv.c

/*
 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "common.h"
#include <util/atomic.h>

#include "background.h"
#include "serial.h"
#include "z80-if.h"
#include "debug.h"
#include "z180-serv.h"

/*--------------------------------------------------------------------------*/


uint8_t z80_get_byte(uint32_t adr)
{
	uint8_t data;

	z80_bus_cmd(Request);
	data = z80_read(adr);
	z80_bus_cmd(Release);

	return data;
}


/*--------------------------------------------------------------------------*/

struct msg_item {
	uint8_t fct;
	uint8_t sub_min, sub_max;
	void (*func)(uint8_t, int, uint8_t *);
};

uint32_t msg_to_addr(uint8_t *msg)
{
	union {
		uint32_t as32;
		uint8_t as8[4];
	} addr;

	addr.as8[0] = msg[0];
	addr.as8[1] = msg[1];
	addr.as8[2] = msg[2];
	addr.as8[3] = 0;

	return addr.as32;
}


static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
{
	z80_memfifo_putc(fifo_msgout, 0xAE);
	z80_memfifo_putc(fifo_msgout, len+2);
	z80_memfifo_putc(fifo_msgout, func);
	z80_memfifo_putc(fifo_msgout, subf);

	return 0;
}

int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
{
	msg_xmit_header(func, subf, len);
	while (len--)
		z80_memfifo_putc(fifo_msgout, *msg++);

	return 0;
}

void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
{
	(void)len;

	z80_memfifo_init(subf, msg_to_addr(msg));
}


void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	while (len--)
		putchar(*msg++);
}

/* echo message */
void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	/* send re-echo */
	msg_xmit(1, 3, len, msg);
}


const FLASH struct msg_item z80_messages[] =
{
	{ 0,			/* fct nr. */
	  1, 3,			/* sub fct nr. from, to */
	  do_msg_ini_memfifo},
	{ 1,
	  1, 1,
	  do_msg_char_out},
	{ 1,
	  2, 2,
	  do_msg_echo},
	{ 0xff,				/* end mark */
	  0, 0,
	  0},

};


void do_message(int len, uint8_t *msg)
{
	uint8_t fct, sub_fct;
	int_fast8_t i = 0;

	if (len >= 2) {
		fct = *msg++;
		sub_fct = *msg++;
		len -= 2;

		while (fct != z80_messages[i].fct) {
			if (z80_messages[i].fct == 0xff) {
				DBG_P(1, "do_message: Unknown function: %i, %i\n",
						fct, sub_fct);
				return; /* TODO: unknown message # */
			}

			++i;
		}

		while (fct == z80_messages[i].fct) {
			if (sub_fct >= z80_messages[i].sub_min &&
					sub_fct <= z80_messages[i].sub_max )
				break;
			++i;
		}

		if (z80_messages[i].fct != fct) {
			DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
					fct, sub_fct);
			return; /* TODO: unknown message sub# */
		}

		(z80_messages[i].func)(sub_fct, len, msg);


	} else {
		/* TODO: error */
		DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
	}
}


#define CTRBUF_LEN 256

void check_msg_fifo(void)
{
	int ch;
	static int_fast8_t state;
	static int msglen,idx;
	static uint8_t buffer[CTRBUF_LEN];

	while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
		switch (state) {
		case 0:		/* wait for start of message */
			if (ch == 0xAE)	{ /* TODO: magic number */
				msglen = 0;
				idx = 0;
				state = 1;
			}
			break;
		case 1:		/* get msg len */
			if (ch > 0 && ch <= CTRBUF_LEN) {
				msglen = ch;
				state = 2;
			} else
				state = 0;
			break;
		case 2: 	/* get message */
			buffer[idx++] = ch;
			if (idx == msglen) {
				do_message(msglen, buffer);
				state = 0;
			}
			break;
		}
	}
}


int msg_handling(int state)
{
	uint8_t pending;

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		pending = (Stat & S_MSG_PENDING) != 0;
		Stat &= ~S_MSG_PENDING;
	}

	if (pending) {
		switch (state) {
		case 0:			/* need init */
			/* Get address of fifo_list */
			z80_bus_cmd(Request);
			uint32_t fifo_list = z80_read(0x40) +
				((uint16_t) z80_read(0x41) << 8) +
				((uint32_t) z80_read(0x42) << 16);
			z80_bus_cmd(Release);
			if (fifo_list != 0) {
				/* Get address of fifo 0 */
				z80_bus_cmd(Request);
				uint32_t fifo_addr = z80_read(fifo_list) +
					((uint16_t) z80_read(fifo_list+1) << 8) +
					((uint32_t) z80_read(fifo_list+2) << 16);
				z80_bus_cmd(Release);
				if (fifo_addr != 0) {
					z80_memfifo_init(fifo_msgin, fifo_addr);
					state = 1;
				}
			}
			break;
		case 1:			/* awaiting messages */
			check_msg_fifo();
			break;
		}
	}

	return state;
}


static int handle_msg_handling;

void setup_z180_serv(void)
{

	handle_msg_handling = bg_register(msg_handling, 0);
}

void restart_z180_serv(void)
{
	z80_bus_cmd(Request);
	z80_write(0x40, 0);
	z80_write(0x41, 0);
	z80_write(0x42, 0);
	z80_bus_cmd(Release);

	for (int i = 0; i < NUM_FIFOS; i++)
		z80_memfifo_init(i, 0);
	bg_setstat(handle_msg_handling, 0);
}

/*--------------------------------------------------------------------------*/

const FLASH uint8_t iniprog[] = {
	0xAF,			// xor     a
	0xED, 0x39, 0x36,	// out0    (rcr),a         ;disable  DRAM refresh
	0x3E, 0x30,		// ld      a,030h
	0xED, 0x39, 0x32	//out0    (dcntl),a       ;0 mem, max i/0 wait states
};

const FLASH uint8_t sertest[] = {
	0xAF,              //  	xor	a
	0xED, 0x39, 0x36,  //  	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //  	ld	a,030h
	0xED, 0x39, 0x32,  //  	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x3E, 0x80,        //  	ld	a,M_MPBT		;no MP, PS=10, DR=16, SS=0
	0xED, 0x39, 0x03,  //  	out0	(cntlb1),a
	0x3E, 0x64,        //  	ld	a,M_RE + M_TE + M_MOD2	;
	0xED, 0x39, 0x01,  //  	out0	(cntla1),a
	0x3E, 0x00,        //  	ld	a,0
	0xED, 0x39, 0x05,  //  	out0	(stat1),a	;Enable rx interrupts
	0xED, 0x38, 0x05,  //l0:in0	a,(stat1)
	0xE6, 0x80,        //  	and	80h
	0x28, 0xF9,        //  	jr	z,l0
	0xED, 0x00, 0x09,  //  	in0	b,(rdr1)
	0xED, 0x38, 0x05,  //l1:in0	a,(stat1)
	0xE6, 0x02,        //  	and	02h
	0x28, 0xF9,        //  	jr	z,l1
	0xED, 0x01, 0x07,  //  	out0	(tdr1),b
	0x18, 0xEA,        //  	jr	l0
};

const FLASH uint8_t test1[] = {
	0xAF,              //	xor	a
	0xED, 0x39, 0x36,  //	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //	ld	a,030h
	0xED, 0x39, 0x32,  //	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x21, 0x1E, 0x00,  // 	ld	hl,dmclrt	;load DMA registers
	0x06, 0x08,        //	ld	b,dmct_e-dmclrt
	0x0E, 0x20,        //	ld	c,sar0l
	0xED, 0x93,        //	otimr
	0x3E, 0xC3,        //	ld	a,0c3h		;dst +1, src +1, burst
	0xED, 0x39, 0x31,  //	out0	(dmode),a	;
	0x3E, 0x62,        //	ld	a,062h		;enable dma0,
	0xED, 0x39, 0x30,  //cl_1:	out0	(dstat),a	;copy 64k
	0x18, 0xFB,        //	jr	cl_1		;
	0x00, 0x00,        //dmclrt:	dw	0		;src (inc)
	0x00,              //	db 	0		;src
	0x00, 0x00,        //	dw	0		;dst (inc),
	0x00,              //	db	0		;dst
	0x00, 0x00,        //	dw 	0		;count (64k)
};
Commit	Line	Data
35edb766 L	1	/*
	2	* (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
72f58822	7	#include "common.h"
89adce76	8	#include <util/atomic.h>
72f58822	9
89adce76	10	#include "background.h"
72f58822 L	11	#include "serial.h"
72f58822 L	12	#include "z80-if.h"
889202c4	13	#include "debug.h"
89adce76	14	#include "z180-serv.h"
72f58822	15
72f58822 L	16	/--------------------------------------------------------------------------/
72f58822 L	17
72f58822 L	18
	19	uint8_t z80_get_byte(uint32_t adr)
	20	{
	21	uint8_t data;
8a7decea	22
62f624d3	23	z80_bus_cmd(Request);
89adce76	24	data = z80_read(adr);
62f624d3	25	z80_bus_cmd(Release);
8a7decea	26
72f58822 L	27	return data;
	28	}
	29
	30
	31	/--------------------------------------------------------------------------/
	32
	33	struct msg_item {
	34	uint8_t fct;
	35	uint8_t sub_min, sub_max;
	36	void (func)(uint8_t, int, uint8_t );
	37	};
	38
	39	uint32_t msg_to_addr(uint8_t *msg)
	40	{
	41	union {
	42	uint32_t as32;
	43	uint8_t as8[4];
	44	} addr;
	45
	46	addr.as8[0] = msg[0];
	47	addr.as8[1] = msg[1];
	48	addr.as8[2] = msg[2];
	49	addr.as8[3] = 0;
	50
	51	return addr.as32;
	52	}
	53
72f58822	54
1a2460dc L	55	static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
	56	{
	57	z80_memfifo_putc(fifo_msgout, 0xAE);
	58	z80_memfifo_putc(fifo_msgout, len+2);
	59	z80_memfifo_putc(fifo_msgout, func);
	60	z80_memfifo_putc(fifo_msgout, subf);
	61
	62	return 0;
	63	}
	64
	65	int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
	66	{
	67	msg_xmit_header(func, subf, len);
	68	while (len--)
	69	z80_memfifo_putc(fifo_msgout, *msg++);
	70
	71	return 0;
	72	}
	73
72f58822 L	74	void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
	75	{
	76	(void)len;
	77
89adce76	78	z80_memfifo_init(subf, msg_to_addr(msg));
72f58822 L	79	}
	80
	81
	82	void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
	83	{
	84	(void)subf;
	85
	86	while (len--)
	87	putchar(*msg++);
	88	}
	89
1a2460dc L	90	/* echo message */
	91	void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
	92	{
	93	(void)subf;
	94
	95	/* send re-echo */
	96	msg_xmit(1, 3, len, msg);
	97	}
	98
72f58822 L	99
	100	const FLASH struct msg_item z80_messages[] =
	101	{
	102	{ 0, /* fct nr. */
89adce76	103	1, 3, /* sub fct nr. from, to */
72f58822 L	104	do_msg_ini_memfifo},
	105	{ 1,
	106	1, 1,
	107	do_msg_char_out},
1a2460dc L	108	{ 1,
	109	2, 2,
	110	do_msg_echo},
72f58822 L	111	{ 0xff, /* end mark */
	112	0, 0,
	113	0},
	114
	115	};
	116
	117
	118
	119
	120	void do_message(int len, uint8_t *msg)
	121	{
	122	uint8_t fct, sub_fct;
	123	int_fast8_t i = 0;
	124
	125	if (len >= 2) {
	126	fct = *msg++;
	127	sub_fct = *msg++;
	128	len -= 2;
	129
89adce76 L	130	while (fct != z80_messages[i].fct) {
	131	if (z80_messages[i].fct == 0xff) {
	132	DBG_P(1, "do_message: Unknown function: %i, %i\n",
	133	fct, sub_fct);
	134	return; /* TODO: unknown message # */
	135	}
8a7decea	136
72f58822	137	++i;
72f58822 L	138	}
	139
	140	while (fct == z80_messages[i].fct) {
8a7decea	141	if (sub_fct >= z80_messages[i].sub_min &&
89adce76	142	sub_fct <= z80_messages[i].sub_max )
72f58822 L	143	break;
	144	++i;
	145	}
	146
	147	if (z80_messages[i].fct != fct) {
	148	DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
	149	fct, sub_fct);
	150	return; /* TODO: unknown message sub# */
	151	}
	152
	153	(z80_messages[i].func)(sub_fct, len, msg);
	154
	155
	156	} else {
	157	/* TODO: error */
	158	DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
	159	}
	160	}
	161
	162
	163
	164	#define CTRBUF_LEN 256
	165
	166	void check_msg_fifo(void)
	167	{
	168	int ch;
	169	static int_fast8_t state;
	170	static int msglen,idx;
	171	static uint8_t buffer[CTRBUF_LEN];
	172
89adce76	173	while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
72f58822 L	174	switch (state) {
72f58822 L	175	case 0: /* wait for start of message */
3531528e	176	if (ch == 0xAE) { /* TODO: magic number */
72f58822 L	177	msglen = 0;
	178	idx = 0;
	179	state = 1;
	180	}
	181	break;
	182	case 1: /* get msg len */
	183	if (ch > 0 && ch <= CTRBUF_LEN) {
	184	msglen = ch;
	185	state = 2;
	186	} else
	187	state = 0;
	188	break;
	189	case 2: /* get message */
	190	buffer[idx++] = ch;
89adce76 L	191	if (idx == msglen) {
	192	do_message(msglen, buffer);
	193	state = 0;
	194	}
	195	break;
	196	}
	197	}
	198	}
	199
	200
	201	int msg_handling(int state)
	202	{
	203	uint8_t pending;
8a7decea L	204
8a7decea L	205	ATOMIC_BLOCK(ATOMIC_FORCEON) {
89adce76 L	206	pending = (Stat & S_MSG_PENDING) != 0;
	207	Stat &= ~S_MSG_PENDING;
	208	}
8a7decea	209
89adce76 L	210	if (pending) {
89adce76 L	211	switch (state) {
1a2460dc	212	case 0: /* need init */
cdc4625b	213	/* Get address of fifo_list */
89adce76	214	z80_bus_cmd(Request);
cdc4625b	215	uint32_t fifo_list = z80_read(0x40) +
89adce76 L	216	((uint16_t) z80_read(0x41) << 8) +
	217	((uint32_t) z80_read(0x42) << 16);
	218	z80_bus_cmd(Release);
cdc4625b L	219	if (fifo_list != 0) {
	220	/* Get address of fifo 0 */
	221	z80_bus_cmd(Request);
	222	uint32_t fifo_addr = z80_read(fifo_list) +
	223	((uint16_t) z80_read(fifo_list+1) << 8) +
	224	((uint32_t) z80_read(fifo_list+2) << 16);
	225	z80_bus_cmd(Release);
	226	if (fifo_addr != 0) {
	227	z80_memfifo_init(fifo_msgin, fifo_addr);
	228	state = 1;
	229	}
89adce76 L	230	}
89adce76 L	231	break;
1a2460dc	232	case 1: /* awaiting messages */
89adce76	233	check_msg_fifo();
72f58822 L	234	break;
	235	}
	236	}
	237
89adce76 L	238	return state;
89adce76 L	239	}
89adce76 L	240
	241
	242	static int handle_msg_handling;
	243
	244	void setup_z180_serv(void)
	245	{
8a7decea	246
89adce76	247	handle_msg_handling = bg_register(msg_handling, 0);
72f58822 L	248	}
72f58822 L	249
89adce76 L	250	void restart_z180_serv(void)
	251	{
	252	z80_bus_cmd(Request);
	253	z80_write(0x40, 0);
	254	z80_write(0x41, 0);
	255	z80_write(0x42, 0);
	256	z80_bus_cmd(Release);
8a7decea L	257
	258	for (int i = 0; i < NUM_FIFOS; i++)
	259	z80_memfifo_init(i, 0);
89adce76 L	260	bg_setstat(handle_msg_handling, 0);
89adce76 L	261	}
72f58822 L	262
	263	/--------------------------------------------------------------------------/
	264
72f58822 L	265	const FLASH uint8_t iniprog[] = {
	266	0xAF, // xor a
	267	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	268	0x3E, 0x30, // ld a,030h
	269	0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
	270	};
	271
	272	const FLASH uint8_t sertest[] = {
	273	0xAF, // xor a
	274	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	275	0x3E, 0x30, // ld a,030h
	276	0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
	277	0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
	278	0xED, 0x39, 0x03, // out0 (cntlb1),a
	279	0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
	280	0xED, 0x39, 0x01, // out0 (cntla1),a
	281	0x3E, 0x00, // ld a,0
	282	0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
	283	0xED, 0x38, 0x05, //l0:in0 a,(stat1)
	284	0xE6, 0x80, // and 80h
	285	0x28, 0xF9, // jr z,l0
	286	0xED, 0x00, 0x09, // in0 b,(rdr1)
	287	0xED, 0x38, 0x05, //l1:in0 a,(stat1)
	288	0xE6, 0x02, // and 02h
	289	0x28, 0xF9, // jr z,l1
	290	0xED, 0x01, 0x07, // out0 (tdr1),b
	291	0x18, 0xEA, // jr l0
	292	};
	293
	294	const FLASH uint8_t test1[] = {
	295	0xAF, // xor a
	296	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	297	0x3E, 0x30, // ld a,030h
	298	0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
	299	0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
	300	0x06, 0x08, // ld b,dmct_e-dmclrt
	301	0x0E, 0x20, // ld c,sar0l
8a7decea	302	0xED, 0x93, // otimr
72f58822 L	303	0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
72f58822 L	304	0xED, 0x39, 0x31, // out0 (dmode),a ;
8a7decea	305	0x3E, 0x62, // ld a,062h ;enable dma0,
72f58822 L	306	0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
72f58822 L	307	0x18, 0xFB, // jr cl_1 ;
8a7decea	308	0x00, 0x00, //dmclrt: dw 0 ;src (inc)
72f58822 L	309	0x00, // db 0 ;src
	310	0x00, 0x00, // dw 0 ;dst (inc),
	311	0x00, // db 0 ;dst
	312	0x00, 0x00, // dw 0 ;count (64k)
	313	};