if (pending) {
switch (state) {
case 0: /* need init */
+ /* Get address of fifo_list */
z80_bus_cmd(Request);
- uint32_t addr = z80_read(0x40) +
+ uint32_t fifo_list = z80_read(0x40) +
((uint16_t) z80_read(0x41) << 8) +
((uint32_t) z80_read(0x42) << 16);
z80_bus_cmd(Release);
- if (addr != 0) {
- z80_memfifo_init(fifo_msgin, addr);
- state = 1;
+ if (fifo_list != 0) {
+ /* Get address of fifo 0 */
+ z80_bus_cmd(Request);
+ uint32_t fifo_addr = z80_read(fifo_list) +
+ ((uint16_t) z80_read(fifo_list+1) << 8) +
+ ((uint32_t) z80_read(fifo_list+2) << 16);
+ z80_bus_cmd(Release);
+ if (fifo_addr != 0) {
+ z80_memfifo_init(fifo_msgin, fifo_addr);
+ state = 1;
+ }
}
break;
case 1: /* awaiting messages */
;-----------------------------------------------------\r
; MMU\r
\r
-COMMON_SIZE equ 4*1024 ;Common Area size in bytes\r
+COMMON_SIZE equ 16*1024 ;Common Area size in bytes\r
;must be multiple of 4K\r
\r
if (COMMON_SIZE mod 1000h)\r
endif\r
\r
\r
-DRSTNUM equ 30h ;DDTZ Restart vector (breakpoints)\r
+DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)\r
\r
+INIDONE equ 03Fh ;CP/M skip hw init, if this address\r
+INIDONEVAL equ 080h ; is set to this value.\r
\r
-mtx.fifo_len equ 32 ;Message transfer fifos\r
-mtx.fifo_id equ 0 ; This *must* have #0\r
+mtx.fifo_len equ 32 ;Message transfer fifos\r
+mtx.fifo_id equ 0 ; This *must* have #0\r
mrx.fifo_len equ 32\r
-mrx.fifo_id equ 1\r
+mrx.fifo_id equ 1\r
\r
ci.fifo_len equ 32 ;AVRCON Character I/O via AVR\r
ci.fifo_id equ 2\r
jr z,l10e7h\r
ld l,(ix+002h)\r
ld h,(ix+003h)\r
- ld a,(ddtrst)\r
+ ld a,(ddtzrst)\r
comst\r
cp (hl)\r
comend\r
ld h,(ix+003h)\r
\r
\r
- ld a,(ddtrst)\r
+ ld a,(ddtzrst)\r
comst\r
ld e,(hl)\r
ld (hl),a\r
ret\r
\r
x27ea:\r
- ld a,(ddtrst)\r
+ ld a,(ddtzrst)\r
comst\r
cp (iy+000h)\r
comend\r
; The following 2 params are changeable by user.\r
; Should these moved to top ram?\r
;\r
-ddtrst: rst DRSTNUM ;rst used by ddtz\r
+ddtzrst:\r
+ rst DDTZRSTVEC ;rst used by ddtz\r
ddtei: ei ;ints enabled/disabled while ddtz is running\r
ret ;\r
offs.pc:\r
\r
if CPU_Z180\r
if 0\r
- \r
+\r
ld hl,dmclrt ;load DMA registers\r
call ioiniml\r
ld a,0cbh ;01ef dst +1, src fixed, burst\r
??cl_1:\r
out0 (dstat),a ;01f9 clear (up to) 64k\r
djnz ??cl_1 ; end of RAM?\r
- \r
+\r
endif\r
endif\r
\r
; -- wstart --\r
\r
wstart:\r
- call sysram_init ;027f\r
+ call sysram_init\r
call ivtab_init\r
if CPU_Z180\r
- call prt0_init\r
+; call prt0_init\r
endif\r
\r
call charini\r
call selbnk\r
endif\r
\r
- im 2 ;?030e\r
- ei ;0282\r
+ ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos\r
+ ld (INIDONE),a ; are allready initialized\r
+\r
+ im 2\r
+ ei\r
\r
- call ?const ;0284\r
- call ?const ;0287\r
- or a ;028a\r
- call nz,?conin ;028d\r
+ call ?const\r
+ call ?const\r
+ or a\r
+ call nz,?conin\r
\r
if CPU_Z180\r
ld e,0 ;Sys$Bank\r
else\r
; TODO:\r
endif\r
- jp ddtz ;0290\r
+ jp ddtz\r
\r
\r
if CPU_Z180\r
;----------------------------------------------------------------------\r
;\r
\r
-;TODO: Make a ringbuffer module.\r
-\r
global buf.init\r
\r
buf.init:\r
ld (ix+o.in_idx),0\r
ld (ix+o.out_idx),0\r
ld (ix+o.mask),a\r
+\r
+ ld a,(ix+o.id)\r
+ cp 4\r
+ ret nc\r
+\r
+ push de\r
+ push hl\r
+ ld hl,fifo_list\r
+ push hl ;save fifo_list\r
+ ld e,a\r
+ ld d,0\r
+ add hl,de\r
+ add hl,de\r
+ add hl,de\r
+ push ix\r
+ pop de\r
+; TODO: address transation\r
+ ld (hl),e\r
+ inc hl\r
+ ld (hl),d\r
+ pop hl ;get fifo_list back\r
+ or a\r
+ jr nz,bufi_ex\r
+\r
+ ld (040h),hl\r
+ ld (040h+2),a\r
+bufi_ex:\r
+ pop hl\r
+ pop de\r
+\r
ret\r
\r
+\r
+fifo_list:\r
+ rept 4\r
+ dw 0\r
+ db 0\r
+ endm\r
+\r
;----------------------------------------------------------------------\r
\r
extrn msginit,msg.sout\r
\r
or a\r
jr nz,bfi_2\r
- call hwl2phy\r
- ld (40h+0),hl\r
- ld (40h+2),a\r
+; call hwl2phy\r
+; ld (40h+0),hl\r
+; ld (40h+2),a\r
out (AVRINT5),a\r
- jr bfi_3 \r
+ jr bfi_3\r
bfi_2:\r
call hwl2phy\r
ld (bufdat+1),hl\r
dec a\r
jr nz,ioi_r\r
jr ioi_nxt\r
-ioi_e: \r
+ioi_e:\r
pop bc\r
ret\r
- \r
+\r
else ;(if 1/0)\r
- \r
+\r
push bc\r
jr ioi_nxt\r
ioi_l:\r
djnz ioi_l\r
pop bc\r
ret\r
- \r
+\r
endif ;(1/0)\r
\r
else\r
inc hl\r
cp b\r
jr z,ioml_e\r
- \r
+\r
ld c,(hl)\r
inc hl\r
otimr\r
\r
\r
end\r
-\r
;\r
\r
msginit:\r
- ld ix,mrx.fifo\r
- ld a,mrx.fifo.mask\r
- call buf.init\r
ld ix,mtx.fifo\r
ld a,mtx.fifo.mask\r
+ call buf.init\r
+ ld ix,mrx.fifo\r
+ ld a,mrx.fifo.mask\r
jp buf.init\r
\r
;--------------------------------------------------------------\r