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[z180-stamp.git] / z180 / init.180
1 page 255
2 .z80
3
4 extrn ddtz,bpent
5 extrn $stack
6 extrn charini,?const,?conin
7 extrn ?cono,?conos
8 extrn romend
9
10
11 global iobyte
12 global isv_sw
13
14 include config.inc
15 if CPU_Z180
16 include z180reg.inc
17 include z180.lib
18 endif
19
20
21
22
23 ;----------------------------------------------------------------------
24
25 cseg
26 romstart equ $
27
28 org romstart+0
29 jp start
30
31 iobyte: db 2
32
33 ; restart vectors
34
35 rsti defl 1
36 rept 7
37 org 8*rsti + romstart
38 jp bpent
39 rsti defl rsti+1
40 endm
41
42 ;----------------------------------------------------------------------
43 ; Config space
44 ;
45
46 org romstart+40h
47
48 dw 0
49 db 0
50
51
52 if ROMSYS
53 $crom: defb c$rom ;
54 else
55 db 0 ;
56 endif
57
58 INIWAITS defl CWAITIO
59 if ROMSYS
60 INIWAITS defl INIWAITS+CWAITROM
61 endif
62
63 ;----------------------------------------------------------------------
64
65 org romstart+50h
66 start:
67 jp cstart
68 jp wstart
69 jp ?const
70 jp ?conin
71 jp ?cono
72 jp ?conos
73 jp charini
74
75 ;----------------------------------------------------------------------
76
77 hwini0:
78 if CPU_Z180
79 db 3 ;count
80 db rcr,CREFSH ;configure DRAM refresh
81 db dcntl,INIWAITS ;wait states
82 db cbar,SYS$CBAR
83 endif
84 db 0
85
86 if CPU_Z180
87 dmclrt: ;clear ram per dma
88 db dmct_e-dmclrt-2 ;
89 db sar0l ;first port
90 dw nullbyte ;src (fixed)
91 nullbyte:
92 db 000h ;src
93 dw romend ;dst (inc), start after "rom" code
94 db 00h ;dst
95 dw 0-romend ;count (64k)
96 dmct_e:
97 db 0
98 endif
99
100
101 cstart:
102 if CPU_Z180
103
104 push af
105 in0 a,(itc) ;Illegal opcode trap?
106 jp m,??st01
107 ld a,i ;I register == 0 ?
108 jr z,hw_reset ; yes, harware reset
109
110 ??st01:
111 ; TODO: SYS$CBR
112 ld a,(syscbr)
113 out0 (cbr),a
114 pop af ;restore registers
115 jp bpent ;
116
117 hw_reset:
118 di ;0058
119 ld a,CREFSH
120 out0 (rcr),a ; configure DRAM refresh
121 ld a,CWAITIO
122 out0 (dcntl),a ; wait states
123
124 ld a,M_NCD ;No Clock Divide
125 out0 (ccr),a
126 ; ld a,M_X2CM ;X2 Clock Multiplier
127 ; out0 (cmr),a
128 else
129 di
130 xor a
131 ld (@cbnk),a
132 endif
133
134 ; check warm start mark
135
136 ld ix,mark_55AA ; top of common area
137 ld a,0aah ;
138 cp (ix+000h) ;
139 jr nz,kstart ;
140 cp (ix+002h) ;
141 jr nz,kstart ;
142 cpl ;
143 cp (ix+001h) ;
144 jr nz,kstart ;
145 cp (ix+003h) ;
146 jr nz,kstart ;
147 ld sp,$stack ; mark found, check
148 jp z,wstart ; check ok,
149
150 ; ram not ok, initialize -- kstart --
151
152 kstart:
153 if CPU_Z180
154 ld a,SYS$CBAR
155 out0 (cbar),a
156 ld a,SYS$CBR
157 out0 (cbr),a
158 endif
159
160 ld sp,$stack ;01e1
161
162 ; Clear RAM using DMA0
163
164 if CPU_Z180
165 if 0
166
167 ld hl,dmclrt ;load DMA registers
168 call ioiniml
169 ld a,0cbh ;01ef dst +1, src fixed, burst
170 out0 (dmode),a ;01f1
171
172 ld b,512/64
173 ld a,062h ;01f4 enable dma0,
174 ??cl_1:
175 out0 (dstat),a ;01f9 clear (up to) 64k
176 djnz ??cl_1 ; end of RAM?
177
178 endif
179 endif
180
181 ld hl,055AAh ;set warm start mark
182 ld (mark_55AA),hl
183 ld (mark_55AA+2),hl
184
185 ; -- wstart --
186
187 wstart:
188 call sysram_init
189 call ivtab_init
190 if CPU_Z180
191 ; call prt0_init
192 endif
193
194 call charini
195 call bufferinit
196
197 if CPU_Z80
198 ld a,0
199 call selbnk
200 endif
201
202 ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos
203 ld (INIDONE),a ; are allready initialized
204
205 im 2
206 ei
207
208 call ?const
209 call ?const
210 or a
211 call nz,?conin
212
213 if CPU_Z180
214 ld e,0 ;Sys$Bank
215 else
216 ; TODO:
217 endif
218 jp ddtz
219
220
221 if CPU_Z180
222 ; TODO: SYS$CBR
223 syscbr: db 1
224 endif
225
226 ;
227 ;----------------------------------------------------------------------
228 ;
229
230 global buf.init
231
232 buf.init:
233 ld (ix+o.in_idx),0
234 ld (ix+o.out_idx),0
235 ld (ix+o.mask),a
236
237 ld a,(ix+o.id)
238 cp 4
239 ret nc
240
241 push de
242 push hl
243 ld hl,fifo_list
244 push hl ;save fifo_list
245 ld e,a
246 ld d,0
247 add hl,de
248 add hl,de
249 add hl,de
250 push ix
251 pop de
252 ; TODO: address translation
253 ld (hl),e
254 inc hl
255 ld (hl),d
256 pop hl ;get fifo_list back
257 or a
258 jr nz,bufi_ex
259
260 ld (040h),hl
261 ld (040h+2),a
262 bufi_ex:
263 pop hl
264 pop de
265
266 ret
267
268
269 fifo_list:
270 rept 4
271 dw 0
272 db 0
273 endm
274
275 ;----------------------------------------------------------------------
276
277 extrn msginit,msg.sout
278 extrn mtx.fifo,mrx.fifo
279 extrn co.fifo,ci.fifo
280
281
282 bufferinit:
283 if CPU_Z180
284 call msginit
285
286 ld hl,buffers
287 ld b,buftablen
288 bfi_1:
289 ld a,(hl)
290 inc hl
291 ld (bufdat+0),a
292 ld e,(hl)
293 inc hl
294 ld d,(hl)
295 inc hl
296 ex de,hl
297
298 or a
299 jr nz,bfi_2
300 ; call hwl2phy
301 ; ld (40h+0),hl
302 ; ld (40h+2),a
303 out (AVRINT5),a
304 jr bfi_3
305 bfi_2:
306 call hwl2phy
307 ld (bufdat+1),hl
308 ld (bufdat+3),a
309 ld hl,inimsg
310 call msg.sout
311 bfi_3:
312 ex de,hl
313 djnz bfi_1
314 ret
315
316 else ;CPU_Z180
317
318 call msginit
319
320 ld hl,buffers
321 ld b,buftablen
322 bfi_1:
323 ld a,(hl)
324 inc hl
325 ld (bufdat+0),a
326 ld e,(hl)
327 inc hl
328 ld d,(hl)
329 inc hl
330 ex de,hl
331
332 or a
333 jr nz,bfi_2
334
335 ld a,(@cbnk)
336 call bnk2phy
337
338 ld (40h+0),hl
339 ld (40h+2),a
340 out (AVRINT5),a
341 jr bfi_3
342 bfi_2:
343
344 ld a,(@cbnk)
345 call bnk2phy
346
347 ld (bufdat+1),hl
348 ld (bufdat+3),a
349 ld hl,inimsg
350 call msg.sout
351 bfi_3:
352 ex de,hl
353 djnz bfi_1
354 ret
355 endif
356
357 buffers:
358 db 0
359 dw mtx.fifo
360 db 1
361 dw mrx.fifo
362 db 2
363 dw co.fifo
364 db 3
365 dw ci.fifo
366 buftablen equ ($ - buffers)/3
367
368 inimsg:
369 db inimsg_e - $ -1
370 db 0AEh
371 db inimsg_e - $ -1
372 db 0
373 bufdat:
374 db 0
375 dw 0
376 db 0
377 inimsg_e:
378
379
380 ;
381 ;----------------------------------------------------------------------
382 ;
383
384 sysram_init:
385 ld hl,sysramw
386 ld de,topcodsys
387 ld bc,sysrame-sysramw
388 ldir
389
390 ret
391
392 ;----------------------------------------------------------------------
393
394 ivtab_init:
395 ld hl,ivtab ;
396 ld a,h ;
397 ld i,a ;
398 if CPU_Z180
399 out0 (il),l ;
400 endif
401
402 ; Let all vectors point to spurious int routines.
403
404 ld d,high sp.int0
405 ld a,low sp.int0
406 ld b,9
407 ivt_i1:
408 ld (hl),a
409 inc l
410 ld (hl),d
411 inc l
412 add a,sp.int.len
413 djnz ivt_i1
414 ret
415
416 ;----------------------------------------------------------------------
417
418 if CPU_Z180
419 prt0_init:
420 ld a,i
421 ld h,a
422 in0 a,(il)
423 and 0E0h
424 or IV$PRT0
425 ld l,a
426 ld (hl),low iprt0
427 inc hl
428 ld (hl),high iprt0
429 ld hl,prt0itab
430 call ioiniml
431 ret
432
433 prt0itab:
434 db prt0it_e-prt0itab-2
435 db tmdr0l
436 dw PRT_TC10MS
437 dw PRT_TC10MS
438 db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.
439 prt0it_e:
440 db 0
441 endif
442
443
444 ;
445 ;----------------------------------------------------------------------
446 ;
447
448 if CPU_Z180
449 io.ini:
450 if 0
451 push bc
452 ld b,0 ;high byte port adress
453 ioi_nxt:
454 ld a,(hl) ;count
455 inc hl
456 or a
457 jr z,ioi_e
458
459 ld c,(hl) ;port address
460 inc hl
461 ioi_r:
462 outi
463 inc b ;outi decrements b
464 dec a
465 jr nz,ioi_r
466 jr ioi_nxt
467 ioi_e:
468 pop bc
469 ret
470
471 else ;(if 1/0)
472
473 push bc
474 jr ioi_nxt
475 ioi_l:
476 ld c,(hl) ;port address
477 inc hl
478 inc c
479 ioi_r:
480 dec c ;otim increments c
481 otim
482 jr z,ioi_r
483 ioi_nxt:
484 ld b,(hl) ;count
485 inc hl
486 inc b ;stop if count == 0
487 djnz ioi_l
488 pop bc
489 ret
490
491 endif ;(1/0)
492
493 else
494
495 io.ini:
496 push bc
497 jr ioi_nxt
498 ioi_l:
499 ld c,(hl) ;port address
500 inc hl
501 otir
502 ioi_nxt:
503 ld b,(hl) ;count
504 inc hl
505 inc b
506 djnz ioi_l
507 endif
508 pop bc
509 ret
510
511 ;----------------------------------------------------------------------
512
513 if CPU_Z180
514
515 global ioiniml
516
517 ioiniml:
518 push bc
519 xor a
520 ioml_lp:
521 ld b,(hl)
522 inc hl
523 cp b
524 jr z,ioml_e
525
526 ld c,(hl)
527 inc hl
528 otimr
529 jr ioml_lp
530 ioml_e:
531 pop bc
532 ret z
533 endif
534
535 io.ini.l:
536 ;
537
538
539
540 ;----------------------------------------------------------------------
541 ;
542 if CPU_Z180
543
544 ;--------------------------------------------------------------------
545 ; Return the BBR value for the given bank number
546 ;
547 ; in a: Bank number
548 ; out a: bbr value
549
550 bnk2log:
551 or a ;
552 ret z ; Bank 0 is at physical address 0
553
554 push bc ;
555 ld b,a ;
556 ld c,CA ;
557 mlt bc ;
558 ld a,c ;
559 add a,10h ;
560 pop bc ;
561 ret ;
562
563 ;--------------------------------------------------------------
564
565 ;in hl: Log. Address
566 ; a: Bank number
567 ;
568 ;out ahl: Phys. (linear) Address
569
570
571 bnk2phy:
572 call bnk2log
573 ; fall thru
574
575 ;--------------------------------------------------------------
576 ;
577 ; hl: Log. Address
578 ; a: Bank base (bbr)
579 ;
580 ; 2 0 0
581 ; 0 6 8 0
582 ; hl hhhhhhhhllllllll
583 ; a + bbbbbbbb
584 ;
585 ; OP: ahl = (a<<12) + (h<<8) + l
586 ;
587 ;out ahl: Phys. (linear) Address
588
589 log2phy:
590 push bc ;
591 l2p_i:
592 ld c,a ;
593 ld b,16 ;
594 mlt bc ; bc = a<<4
595 ld a,c ;
596 add a,h ;
597 ld h,a ;
598 ld a,b ;
599 adc a,0 ;
600 pop bc ;
601 ret ;
602
603 ;--------------------------------------------------------------
604 ;
605 ; hl: Log. Address
606 ;
607 ;
608 ; OP: ahl = (bankbase<<12) + (d<<8) + e
609 ;
610 ;out ahl: Phys. (linear) Address
611
612
613 hwl2phy:
614 push bc ;
615 in0 c,(cbar) ;
616 ld a,h ;
617 or 00fh ; log. addr in common1?
618 cp c
619 jr c,hlp_1
620
621 in0 a,(cbr) ; yes, cbr is address base
622 jr hl2p_x
623 hlp_1:
624 ld b,16 ; log. address in baked area?
625 mlt bc
626 ld a,h
627 cp c
628 jr c,hlp_2
629 in0 a,(bbr) ; yes, bbr is address base
630 jr hl2p_x
631 hlp_2:
632 xor a ; common1
633 hl2p_x:
634 jr nz,l2p_i
635
636 pop bc ; bank part is 0, no translation
637 ret ;
638
639
640
641 else ;CPU_Z180
642
643 ;----------------------------------------------------------------------
644 ;
645
646 bnk2phy:
647 sla h
648 jr nc,b2p_1 ;A15=1 --> common
649 ld a,3
650 b2p_1:
651 srl a
652 rr h
653 ret
654
655 endif
656
657 ;--------------------------------------------------------------
658 ;
659 ;return:
660 ; hl = hl + a
661 ; Flags undefined
662 ;
663
664 add_hl_a:
665 add a,l
666 ld l,a
667 ret nc
668 inc h
669 ret
670
671 ; ---------------------------------------------------------
672
673 sysramw:
674
675 .phase isvsw_loc
676 topcodsys:
677
678 ; Trampoline for interrupt routines in banked ram.
679 ; Switch stack pointer to "system" stack in top ram
680 ; Save cbar
681
682 isv_sw: ;
683 ex (sp),hl ;save hl, 'return adr' in hl
684 push de ;
685 push af ;
686 ex de,hl ;'return address' in de
687 ld hl,0 ;
688 add hl,sp ;
689 ld a,h ;
690 cp 0f8h ;
691 jr nc,isw_1 ;stack allready in top ram
692 ld sp,$stack ;
693 isw_1:
694 push hl ;save user stack pointer
695 in0 h,(cbar) ;
696 push hl ;
697 ld a,SYS$CBAR ;
698 out0 (cbar),a ;
699 ex de,hl ;
700 ld e,(hl) ;
701 inc hl ;
702 ld d,(hl) ;
703 ex de,hl ;
704 push bc ;
705 call jphl ;
706
707 pop bc ;
708 pop hl ;
709 out0 (cbar),h ;
710 pop hl ;
711 ld sp,hl ;
712 pop af ;
713 pop de ;
714 pop hl ;
715 ei ;
716 ret ;
717 jphl:
718 jp (hl) ;
719
720 ; ---------------------------------------------------------
721
722 if CPU_Z180
723
724 iprt0:
725 push af
726 push hl
727 in0 a,(tcr)
728 in0 a,(tmdr0l)
729 in0 a,(tmdr0h)
730 ld a,(tim_ms)
731 inc a
732 cp 100
733 jr nz,iprt_1
734 xor a
735 ld hl,(tim_s)
736 inc hl
737 ld (tim_s),hl
738 iprt_1:
739 ld (tim_ms),a
740 pop hl
741 pop af
742 ei
743 ret
744
745 endif
746
747 ; ---------------------------------------------------------
748
749 sp.int0:
750 ld a,0d0h
751 jr sp.i.1
752 sp.int.len equ $-sp.int0
753 ld a,0d1h
754 jr sp.i.1
755 ld a,0d2h
756 jr sp.i.1
757 ld a,0d3h
758 jr sp.i.1
759 ld a,0d4h
760 jr sp.i.1
761 ld a,0d5h
762 jr sp.i.1
763 ld a,0d6h
764 jr sp.i.1
765 ld a,0d7h
766 jr sp.i.1
767 ld a,0d8h
768 sp.i.1:
769 ; out (80h),a
770 halt
771
772 ; ---------------------------------------------------------
773
774 if CPU_Z80
775
776 ; Get IFF2
777 ; This routine may not be loaded in page zero
778 ;
779 ; return Carry clear, if INTs are enabled.
780 ;
781 global getiff
782 getiff:
783 xor a ;clear accu and carry
784 push af ;stack bottom := 00xxh
785 pop af
786 ld a,i ;P flag := IFF2
787 ret pe ;exit carry clear, if enabled
788 dec sp
789 dec sp ;has stack bottom been overwritten?
790 pop af
791 and a ;if not 00xxh, INTs were
792 ret nz ;actually enabled
793 scf ;Otherwise, they really are disabled
794 ret
795
796 ;----------------------------------------------------------------------
797
798 global selbnk
799
800 ; a: bank (0..2)
801
802 selbnk:
803 push bc
804 ld c,a
805 call getiff
806 push af
807
808 ld a,c
809 di
810 ld (@cbnk),a
811 ld a,5
812 out (SIOAC),a
813 ld a,(mm_sio0)
814 rla
815 srl c
816 rra
817 out (SIOAC),a
818 ld (mm_sio0),a
819
820 ld a,5
821 out (SIOBC),a
822 ld a,(mm_sio1)
823 rla
824 srl c
825 rra
826 out (SIOBC),a
827 ld (mm_sio1),a
828 pop af
829 pop bc
830 ret c ;INTs were disabled
831 ei
832 ret
833
834 ;----------------------------------------------------------------------
835
836 ; c: bank (0..2)
837
838 if 0
839
840 selbnk:
841 ld a,(@cbnk)
842 xor c
843 and 3
844 ret z ;no change
845
846 call getiff
847 push af
848 ld a,c
849 di
850 ld (@cbnk),a
851 ld a,5
852 out (SIOAC),a
853 ld a,(mm_sio0)
854 rla
855 srl c
856 rra
857 out (SIOAC),a
858 ld (mm_sio0),a
859
860 ld a,5
861 out (SIOBC),a
862 ld a,(mm_sio1)
863 rla
864 srl c
865 rra
866 out (SIOBC),a
867 ld (mm_sio1),a
868 pop af
869 ret nc ;INTs were disabled
870 ei
871 ret
872
873 endif
874
875 ;----------------------------------------------------------------------
876
877 if 0
878 ex af,af'
879 push af
880 ex af,af'
881
882 rra
883 jr nc,stbk1
884 ex af,af'
885 ld a,5
886 out (SIOAC),a
887 ld a,(mm_sio0)
888 rla
889 srl c
890 rra
891 out (SIOAC),a
892 ld (mm_sio1),a
893 ex af,af'
894
895 stbk1:
896 rra
897 jr nc,stbk2
898 ex af,af'
899 ld a,5
900 out (SIOBC),a
901 ld a,(mm_sio1)
902 rla
903 srl c
904 rra
905 out (SIOBC),a
906 ld (mm_sio1),a
907 ex af,af'
908
909 stbk2:
910 endif
911
912 global @cbnk
913 global mm_sio0, mm_sio1
914
915 @cbnk: db 0 ; current bank (0..2)
916 mm_sio0:
917 ds 1
918 mm_sio1:
919 ds 1
920
921
922 endif
923
924 ;----------------------------------------------------------------------
925
926 curph defl $
927 .dephase
928 sysrame:
929 .phase curph
930 tim_ms: db 0
931 tim_s: dw 0
932 .dephase
933
934 ;-----------------------------------------------------
935
936
937 cseg
938
939 ;.phase 0ffc0h
940 ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table
941 ;.dephase
942
943 ;.phase 0fffah
944 mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack
945 ;ds 4
946 ;.dephase
947
948
949 end
Z180 Stamp Monitor