z180/cpuinfo.180

   1         .z80                            ; for M80, ignored by SLR assembler
   2         include z180reg.inc
   3
   4 RUN_TPA         equ     0
   5
   6 UUNKNOWN        equ     0       ;Unknown CPU
   7 U8080           equ     1       ;8080
   8 U8085           equ     2       ;8085
   9 UZ80            equ     3       ;Z80
  10 UX180           equ     4       ;HD64180 or higher
  11 UHD64180        equ     5       ;HD64180
  12 UZ80180         equ     6       ;Z80180
  13 UZ8S180         equ     7       ;Z8S180, Z8L180
  14
  15
  16 ;-------------------------------------------------------------------------------
  17
  18
  19    if RUN_TPA
  20 base            equ     0100h
  21    else
  22 base            equ     0
  23    endif
  24
  25
  26         aseg
  27         org     base
  28         jp      start
  29
  30 done:   db      0
  31 result: db      0
  32
  33 ;-------------------------------------------------------------------------------
  34 ; Read internal register at address in L and IOBASE in H.
  35 ;
  36
  37 reg_in:
  38         ld      a,h
  39         add     a,l
  40         ld      c,a
  41         ld      b,0
  42         in      a,(c)
  43         ret
  44
  45 ;-------------------------------------------------------------------------------
  46 ; Write internal register at address in L and IOBASE in H.
  47 ;
  48
  49 reg_out:
  50         ld      b,a
  51         ld      a,h
  52         add     a,l
  53         ld      c,a
  54         ld      a,b
  55         ld      b,0
  56         out     (c),a
  57         ret
  58
  59 ;-------------------------------------------------------------------------------
  60 ; Check if register C exists. D holds mask of bit to test.
  61 ;       return nz, if register exists
  62
  63 chk_reg:
  64         call    reg_in
  65         cp      0ffh
  66         ret     nz              ;
  67
  68         ; check, if register is changeable
  69
  70         xor     d               ; set bit(s) in register to 0
  71         call    reg_out
  72         call    reg_in          ; get it back
  73         ex      af,af'
  74         ld      a,0ffh          ; set to register original state
  75         call    reg_out
  76         ex      af,af'
  77         cpl
  78         and     d
  79         ret
  80
  81 ;-------------------------------------------------------------------------------
  82 ; Check CPU
  83 ;
  84 ;
  85 ; return:
  86 ;       E = 0   Unknown
  87 ;       E = 1   8080
  88 ;       E = 2   8085
  89 ;       E = 3   Z80
  90 ;       E = 4   HD64180 or higher
  91 ;       E = 5   HD64180
  92 ;       E = 6   Z80180
  93 ;       E = 7   Z8S180, Z8L180
  94 ;
  95 ;-------------------------------------------------------------------------------
  96 ; Registers only in Z180+, not in HD64180
  97 ;       3E      OMCR
  98 ;
  99 ; Registers only in Z8S180/Z8L180
 100 ;       12      ASEXT0
 101 ;       13      ASEXT1
 102 ;       1A      ASTC0L
 103 ;       1B      ASTC0H
 104 ;       1C      ASTC1L
 105 ;       1D      ASTC1H
 106 ;       1E      CMR
 107 ;       1F      CCR
 108 ;       2D      IAR1B
 109 ;
 110 ; Reserved registers
 111 ;       11
 112 ;       19
 113 ;       35
 114 ;       37
 115 ;       3B - 3D
 116
 117 check:
 118         ld      e,U8080         ; Init return val, assume 8080
 119         xor     a
 120         dec     a               ; 00 --> 0FFH   8080/8085: even parity; Z80+: No overflow
 121         jp      po,chk_z80      ; Z80+ if P/V flag reset
 122
 123         ; The 8085 logical AND instructions always set the auxiliary flag ON.
 124         ; The 8080 logical AND instructions set the flag to reflect the
 125         ; logical OR of bit 3 of the values involved in the AND operation.
 126         ; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)
 127
 128         xor     a
 129         and     a               ; 8085 sets, 8080 resets half carry.
 130         daa                     ; A=06 (8085) or A=00 (8080)
 131         ret     z
 132         inc     e
 133         ret
 134
 135 chk_z80:
 136         ld      e,UZ80          ; Assume Z80
 137         daa                     ; Z80: 099H, x180+: 0F9H
 138         cp      99h             ; Result on 180 type cpus is F9 here. Thanks Hitachi
 139         ret     z
 140         inc     e               ; x180
 141
 142         ; At least Hitachi HD64180
 143         ; Test differences in certain internal registers
 144         ; to determine the 180 variant.
 145         ; First, search the internal register bank.
 146
 147         ld      h,00H           ; I/O Base
 148 find_base_loop:
 149         ld      l,icr
 150         call    reg_in
 151         and     11011111b       ; mask I/O Stop bit
 152         xor     h
 153         cp      01FH
 154         jr      nz,nxt_base
 155
 156         ;TODO: additional plausibility checks
 157
 158         jr      z,base_found
 159 nxt_base:
 160         ld      a,h
 161         add     a,040H
 162         ld      h,a
 163         jr      nc,find_base_loop
 164         ret                     ;I/O registers not found
 165
 166         ; Register (base) found.
 167
 168 base_found:
 169         inc     e               ; HD64180
 170         ld      l,omcr          ; Check, if CPU has OMCR register
 171         ld      d,M_IOC         ;
 172         call    chk_reg         ;
 173         ret     z               ; Register does not exist. It's a HD64180
 174
 175         inc     e               ; Z80180
 176         ld      l,cmr           ; Check, if CPU has CMR register
 177         ld      d,M_LNC         ;
 178         call    chk_reg         ;
 179         ret     z               ; register does not exist. It's a Z80180
 180
 181         inc     e               ; S180/L180 (class) detected.
 182
 183         ret
 184
 185 ;-------------------------------------------------------------------------------
 186
 187 start:
 188         ld      sp,stack
 189         call    check
 190
 191         ld      hl,result
 192         ld      (hl),e
 193         dec     hl
 194         ld      (hl),0ffH
 195         halt
 196         jp      $-1
 197
 198         rept    8
 199           dw    0
 200         endm
 201 stack:
 202         end
 203
 204 ; vim:set ts=8 noet nowrap