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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
5 * | Z180-Sig | AVR-Port | Dir | Special Function |
6 * +------------+---------------+-------+-----------------------+
17 * | A10 | PC 2 | O | |
18 * | A11 | PC 3 | O | |
19 * | A12 | PC 4 | O | |
20 * | A13 | PC 5 | O | |
21 * | A14 | PC 6 | O | |
22 * | A15 | PC 7 | O | |
23 * | A16 | PE 2 | O | |
24 * | A17 | PE 3 | O | |
25 * | A18 | PE 4 | O | |
26 * | D0 | PF 0 | I/O | |
27 * | D1 | PF 1 | I/O | |
28 * | D2 | PF 2 | I/O | |
29 * | D3 | PF 3 | I/O | |
30 * | D4 | PF 4 | I/O | |
31 * | D5 | PF 5 | I/O | |
32 * | D6 | PF 6 | I/O | |
33 * | D7 | PF 7 | I/O | |
36 * | MREQ | PD 4 | O | |
37 * | RST | PD 5 | O | |
38 * | BUSREQ | PD 7 | O | |
39 * | BUSACK | PD 6 | I | |
40 * | IOCS1 | PE 5 | I | |
44 * | | P | | af1 USART1_TX |
45 * | | P | | af1 USART1_RX |
46 * | | P |JTDI | remap SPI1_NSS' |
47 * | | P |JTDO | remap SPI1_SCK' |
48 * | | P |JTRST | remap SPI1_MISO' |
49 * | | P | | remap SPI1_MOSI' |
50 * | | P | | af1 OSC32 |
51 * | | P | | af1 OSC32 |
57 #include <util/delay.h>
58 #include <util/atomic.h>
64 /* Number of array elements */
65 #define NELEMS(x) (sizeof x/sizeof *x)
76 } __attribute__((__packed__
));
78 typedef struct bits pbit_t
;
80 #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
83 //#define P_ZCLK PORTB
85 //#define DDR_ZCLK DDRB
93 #define P_BUSREQ PORTD
95 #define DDR_BUSREQ DDRD
96 #define P_BUSACK PORTD
97 #define PIN_BUSACK PIND
99 #define DDR_BUSACK DDRD
100 //#define P_HALT PORTA
102 #define P_IOCS1 PORTE
104 #define DDR_IOCS1 DDRE
105 //#define P_NMI PORTB
126 //#define ADB_PORT PORTE
129 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
130 #define Z80_O_MREQ SBIT(P_MREQ, 4)
131 #define Z80_O_RD SBIT(P_RD, 3)
132 #define Z80_O_WR SBIT(P_WR, 2)
133 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
134 //#define Z80_O_NMI SBIT(P_NMI, )
135 #define Z80_O_RST SBIT(P_RST, 5)
136 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
137 //#define Z80_I_HALT SBIT(P_HALT, )
140 #define MASK(n) ((1<<(n))-1)
141 #define SMASK(w,s) (MASK(w) << (s))
151 static zstate_t zstate
;
153 /*--------------------------------------------------------------------------*/
156 static void z80_addrbus_set_tristate(void)
158 /* /MREQ, /RD, /WR: Input, no pullup */
159 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
168 PIN_ADB
= P_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
169 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
173 static void z80_addrbus_set_active(void)
175 /* /MREQ, /RD, /WR: Output and high */
179 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
183 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
187 static void z80_dbus_set_in(void)
194 static void z80_dbus_set_out(void)
200 static void z80_reset_pulse(void)
208 void z80_setup_bus(void)
210 /* /ZRESET: Output and low */
214 /* /BUSREQ: Output and high */
216 DDR_BUSREQ
|= _BV(BUSREQ
);
218 /* /BUSACK: Input, no pullup */
219 DDR_BUSACK
&= ~_BV(BUSACK
);
220 P_BUSACK
&= ~_BV(BUSACK
);
222 /* /IOCS1: Input, no pullup */
223 DDR_IOCS1
&= ~_BV(IOCS1
);
224 P_IOCS1
&= ~_BV(IOCS1
);
226 z80_addrbus_set_tristate();
233 zstate_t
z80_bus_state(void)
239 static void z80_busreq_hpulse(void)
242 z80_addrbus_set_tristate();
244 ATOMIC_BLOCK(ATOMIC_RESTORESTATE
) {
246 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
247 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
250 if (zstate
& ZST_ACQUIRED
) {
251 while(Z80_I_BUSACK
== 1)
253 z80_addrbus_set_active();
261 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
265 ----------------+---------------+---------------+---------------+---------------+
267 Reset | 0 | 0 | 0 | 0 |
270 Request | 1 | | 3 | |
273 Release | | 0 | | 2 |
279 Restart | | | 2 | 3 |
287 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
293 z80_addrbus_set_tristate();
304 while(Z80_I_BUSACK
== 1)
306 z80_addrbus_set_active();
312 while(Z80_I_BUSACK
== 1)
314 z80_addrbus_set_active();
315 zstate
= RUNNING_AQRD
;
327 z80_addrbus_set_tristate();
334 z80_addrbus_set_tristate();
352 z80_addrbus_set_tristate();
354 z80_addrbus_set_active();
355 zstate
= RUNNING_AQRD
;
386 /*--------------------------------------------------------------------------*/
389 //inline __attribute__ ((always_inline))
390 void z80_setaddress(uint32_t addr
)
392 addr_t x
; x
.l
= addr
;
396 PIN_ADB
= ((x
.b
[2] << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
399 void z80_write(uint32_t addr
, uint8_t data
)
401 z80_setaddress(addr
);
412 uint8_t z80_read(uint32_t addr
)
416 z80_setaddress(addr
);
430 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
435 z80_setaddress(addr
++);
445 void z80_write_block(const __flash
uint8_t *src
, uint32_t dest
, uint32_t length
)
452 z80_setaddress(dest
++);
464 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
465 017A' rx.in_idx: ds 1 ;
466 017B' rx.out_idx: ds 1 ;
467 017C' rx.buf: ds rx.buf_len ;
468 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
470 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
471 018D' tx.in_idx: ds 1 ;
472 018E' tx.out_idx: ds 1 ;
473 018F' tx.buf: ds tx.buf_len ;
474 019E' tx.buf_end equ $-1 ; last byte
478 typedef struct __attribute__((packed
)) {
487 #define FIFO_BUFSIZE_MASK -3
488 #define FIFO_INDEX_IN -2
489 #define FIFO_INDEX_OUT -1
497 } fifo_dsc
[NUM_FIFOS
];
500 void z80_memfifo_init(const fifo_t f
, uint32_t adr
)
503 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f
, adr
);
505 fifo_dsc
[f
].base
= adr
;
507 z80_bus_cmd(Request
);
509 fifo_dsc
[f
].mask
= z80_read(adr
+ FIFO_BUFSIZE_MASK
);
510 fifo_dsc
[f
].idx_in
= z80_read(adr
+ FIFO_INDEX_IN
);
511 fifo_dsc
[f
].idx_out
= z80_read(adr
+ FIFO_INDEX_OUT
);
513 z80_bus_cmd(Release
);
517 int z80_memfifo_is_empty(const fifo_t f
)
521 if (fifo_dsc
[f
].base
!= 0) {
523 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
526 z80_bus_cmd(Request
);
528 z80_bus_cmd(Release
);
529 rc
= idx
== fifo_dsc
[f
].idx_out
;
535 int z80_memfifo_is_full(const fifo_t f
)
539 if (fifo_dsc
[f
].base
!= 0) {
540 z80_bus_cmd(Request
);
541 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
542 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
543 z80_bus_cmd(Release
);
548 uint8_t z80_memfifo_getc(const fifo_t f
)
552 while (z80_memfifo_is_empty(f
))
555 z80_bus_cmd(Request
);
556 idx
= fifo_dsc
[f
].idx_out
;
557 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
558 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
559 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
560 z80_bus_cmd(Release
);
566 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
570 while (z80_memfifo_is_full(f
))
573 z80_bus_cmd(Request
);
574 idx
= fifo_dsc
[f
].idx_in
;
575 z80_write(fifo_dsc
[f
].base
+idx
, val
);
576 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
577 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
578 z80_bus_cmd(Release
);
581 /*--------------------------------------------------------------------------*/
583 TODO: Rewrite msg_fifo routines for AVR
588 //uint8_t idx_out, idx_in;
593 /*--------------------------------------------------------------------------*/
597 static void tim1_setup(void)
599 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
600 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
606 /* | TIM_SMCR_ETF_CK_INT_N_2 */
611 TIM1_DIER
= TIM_DIER_TDE
;
615 | TIM_CCMR1_OC1M_FORCE_LOW
616 | TIM_CCMR1_CC1S_OUT
;
618 TIM1_SMCR
|= TIM_SMCR_SMS_TM
;
623 /*--------------------------------------------------------------------------*/
625 void z80_setup_msg_fifo(void)
627 // gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
628 // GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
632 // msg_fifo.count = NELEMS(msg_fifo.buf);
639 void z80_init_msg_fifo(uint32_t addr
)
642 DBG_P(1, "z80_init_msg_fifo: %lx\n", addr
);
644 z80_bus_cmd(Request
);
645 z80_write(addr
+FIFO_INDEX_OUT
, z80_read(addr
+FIFO_INDEX_IN
));
646 z80_bus_cmd(Release
);
647 msg_fifo
.base
= addr
;
651 int z80_msg_fifo_getc(void)
656 if (msg_fifo
.count
!= (NELEMS(msg_fifo
.buf
) /*- DMA1_CNDTR4 */ )) {
657 c
= msg_fifo
.buf
[msg_fifo
.count
];
658 if (++msg_fifo
.count
== NELEMS(msg_fifo
.buf
))
661 if (msg_fifo
.base
!= 0) {
662 z80_bus_cmd(Request
);
663 z80_write(msg_fifo
.base
+FIFO_INDEX_OUT
, msg_fifo
.count
);
664 z80_bus_cmd(Release
);