5 * | Z180-Sig | STM32-Port | Buffer | Dir |Special Function |
6 * | -------- | ---------- | ------ | --- | --------------- |
17 * | A10 |C 2 |P |O | |
18 * | A11 |C 3 |P |O | |
19 * | A12 |C 4 |P |O | |
20 * | A13 |C 5 |P |O | |
23 * | A16 |C 10 | |O | |
24 * | A17 |C 11 | |O | |
25 * | A18 |C 12 | |O | |
26 * | D0 |B 8 | |I/O | |
27 * | D1 |B 9 | |I/O | |
28 * | D2 |B 10 | |I/O | |
29 * | D3 |B 11 | |I/O | |
30 * | D4 |B 12 | |I/O | |
31 * | D5 |B 13 | |I/O | |
32 * | D6 |B 14 | |I/O | |
33 * | D7 |B 15 | |I/O | |
34 * | ME |C 13 |P |O | |
37 * | BUSREQ |D 2 | |O | |
38 * | IOCS1 |A 11 | |I |TIM1_CH4 |
39 * | BUSACK |A 12 | |I | |
40 * | HALT |A 12 | |I | |
42 * | RST |B 6 | |O |TIM16_CH1N |
44 * | |A 9 | | |af1 USART1_TX |
45 * | |A 10 | | |af1 USART1_RX |
46 * | |A 15 | |JTDI | remap SPI1_NSS' |
47 * | |B 3 | |JTDO |remap SPI1_SCK' |
48 * | |B 4 | |NJTRST |remap SPI1_MISO' |
49 * | |B 5 | | |remap SPI1_MOSI' |
50 * | |C 14 | | |af1 OSC32 |
51 * | |C 15 | | |af1 OSC32 |
55 AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
61 #include <libopencm3/stm32/gpio.h>
62 #include <libopencm3/stm32/rcc.h>
63 #include <libopencm3/stm32/timer.h>
64 #include <libopencm3/stm32/dma.h>
67 /* Number of array elements */
68 #define NELEMS(x) (sizeof x/sizeof *x)
73 #define CONCAT(x,y) x ## y
74 #define EVALUATOR(x,y) CONCAT(x,y)
76 #define GPIO_(X) CONCAT(GPIO, X)
87 #define P_BUSREQ GPIOD
89 #define P_BUSACK GPIOA
91 //#define P_HALT GPIOA
103 #define ADp1_PORT GPIOA
105 #define ADp2_OFS ADp1_WIDTH
108 #define ADp2_PORT GPIOC
110 #define ADp3_OFS (ADp2_OFS+ADp2_WIDTH)
112 #define ADp3_SHIFT 10
113 #define ADp3_PORT GPIOC
115 #define ADunbuff1_WIDTH 1
116 #define ADunbuff1_SHIFT 8
117 #define ADunbuff1_PORT GPIOA
119 #define ADunbuff2_WIDTH 2
120 #define ADunbuff2_SHIFT 6
121 #define ADunbuff2_PORT GPIOC
123 #define ADunbuff3_WIDTH 3
124 #define ADunbuff3_SHIFT 10
125 #define ADunbuff3_PORT GPIOC
130 #define DB_PORT GPIOB
132 #define GPIO_ME GPIO_(ME)
133 #define GPIO_RD GPIO_(RD)
134 #define GPIO_WR GPIO_(WR)
135 #define GPIO_BUSREQ GPIO_(BUSREQ)
136 #define GPIO_BUSACK GPIO_(BUSACK)
137 //#define GPIO_HALT GPIO_(HALT)
138 #define GPIO_IOCS1 GPIO_(IOCS1)
139 #define GPIO_NMI GPIO_(NMI)
140 #define GPIO_RST GPIO_(RST)
142 #define Z80_O_ME BBIO_PERIPH(P_ME+ODR, ME)
143 #define Z80_O_RD BBIO_PERIPH(P_RD+ODR, RD)
144 #define Z80_O_WR BBIO_PERIPH(P_WR+ODR, WR)
145 #define Z80_O_BUSREQ BBIO_PERIPH(P_BUSREQ+ODR, BUSREQ)
146 #define Z80_O_NMI BBIO_PERIPH(P_NMI+ODR, NMI)
147 #define Z80_O_RST BBIO_PERIPH(P_RST+ODR, RST)
149 #define Z80_I_BUSACK BBIO_PERIPH(P_BUSACK+IDR, BUSACK)
150 //#define Z80_I_HALT BBIO_PERIPH(P_HALT+IDR, HALT)
153 #define MASK(n) ((1<<n)-1)
155 #define IOFIELD_SET(src, ofs, width, shift) \
156 ((((src>>ofs) & MASK(width)) << shift) | ((((~src>>ofs) & MASK(width)) << shift) << 16))
158 #define IOFIELD_GET(src, width, shift) \
159 ((src>>shift) & MASK(width))
161 #define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT)
162 #define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ)
164 #define DB_MODE_INPUT ( (CNF_MODE_I_F << (4 * 0)) \
165 | (CNF_MODE_I_F << (4 * 1)) \
166 | (CNF_MODE_I_F << (4 * 2)) \
167 | (CNF_MODE_I_F << (4 * 3)) \
168 | (CNF_MODE_I_F << (4 * 4)) \
169 | (CNF_MODE_I_F << (4 * 5)) \
170 | (CNF_MODE_I_F << (4 * 6)) \
171 | (CNF_MODE_I_F << (4 * 7)))
173 #define DB_MODE_OUTPUT ( (CNF_MODE_O_PP << (4 * 0)) \
174 | (CNF_MODE_O_PP << (4 * 1)) \
175 | (CNF_MODE_O_PP << (4 * 2)) \
176 | (CNF_MODE_O_PP << (4 * 3)) \
177 | (CNF_MODE_O_PP << (4 * 4)) \
178 | (CNF_MODE_O_PP << (4 * 5)) \
179 | (CNF_MODE_O_PP << (4 * 6)) \
180 | (CNF_MODE_O_PP << (4 * 7)))
183 /*--------------------------------------------------------------------------*/
185 static void tim16_setup(void)
187 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM16RST
;
188 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM16RST
;
190 TIM16_BDTR
= TIM_BDTR_MOE
;
193 | TIM_CCMR1_OC1M_FORCE_LOW
194 | TIM_CCMR1_CC1S_OUT
;
196 TIM16_CCER
= TIM_CCER_CC1NE
199 TIM16_ARR
= 48; /* default */
200 TIM16_CCR1
= 1; /* */
203 /*--------------------------------------------------------------------------*/
205 static void tim16_set(int mode
)
209 cc_mode
= TIM_CCMR1_CC1S_OUT
;
211 TIM16_CR1
= TIM_CR1_OPM
;
214 cc_mode
|= TIM_CCMR1_OC1M_FORCE_LOW
;
216 cc_mode
|= TIM_CCMR1_OC1M_FORCE_HIGH
;
219 cc_mode
|= TIM_CCMR1_OC1M_PWM2
;
222 TIM16_CCMR1
= cc_mode
;
225 TIM16_CR1
|= TIM_CR1_CEN
;
228 /*--------------------------------------------------------------------------*/
233 * A0..A6, A8..A13 are buffered. No need to disable.
234 * A7, A14..A18: set to input.
237 static void z80_setup_adrbus_tristate(void)
240 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_INPUT
,
241 GPIO_CNF_INPUT_FLOAT
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
242 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_INPUT
, GPIO_CNF_INPUT_FLOAT
,
243 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
245 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
246 | (CNF_MODE_I_F
<< (4 * 0));
247 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
248 | ((CNF_MODE_I_F
<< (4 * 6)) | (CNF_MODE_I_F
<< (4 * 7)));
249 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
250 | ((CNF_MODE_I_F
<< (4*2)) | (CNF_MODE_I_F
<< (4*3)) | (CNF_MODE_I_F
<< (4*4)));
255 static void z80_setup_adrbus_active(void)
258 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
259 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
260 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
, GPIO_CNF_OUTPUT_PUSHPULL
,
261 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
263 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
264 | (CNF_MODE_O_PP
<< (4 * 0));
265 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
266 | ((CNF_MODE_O_PP
<< (4 * 6)) | (CNF_MODE_O_PP
<< (4 * 7)));
267 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
268 | ((CNF_MODE_O_PP
<< (4*2)) | (CNF_MODE_O_PP
<< (4*3)) | (CNF_MODE_O_PP
<< (4*4)));
273 static void z80_setup_dbus_in(void)
275 GPIO_CRH(DB_PORT
) = DB_MODE_INPUT
;
278 static void z80_setup_dbus_out(void)
280 GPIO_CRH(DB_PORT
) = DB_MODE_OUTPUT
;
284 static void z80_setaddress(uint32_t addr
)
286 GPIO_BSRR(ADp1_PORT
) = IOFIELD_SET(addr
, ADp1_OFS
, ADp1_WIDTH
, ADp1_SHIFT
);
287 GPIO_BSRR(ADp2_PORT
) = IOFIELD_SET(addr
, ADp2_OFS
, ADp2_WIDTH
, ADp2_SHIFT
);
288 GPIO_BSRR(ADp3_PORT
) = IOFIELD_SET(addr
, ADp3_OFS
, ADp3_WIDTH
, ADp3_SHIFT
);
291 void z80_setup_bus(void)
295 gpio_set_mode(P_RST
, GPIO_MODE_OUTPUT_10_MHZ
,
296 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL
, GPIO_RST
);
298 gpio_set_mode(P_BUSREQ
, GPIO_MODE_OUTPUT_10_MHZ
,
299 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_BUSREQ
);
301 gpio_set_mode(P_NMI
, GPIO_MODE_OUTPUT_10_MHZ
,
302 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_NMI
);
306 gpio_set_mode(P_ME
, GPIO_MODE_OUTPUT_2_MHZ
,
307 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_ME
);
308 gpio_set_mode(P_RD
, GPIO_MODE_OUTPUT_10_MHZ
,
309 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_RD
| GPIO_WR
);
312 //while(Z80_I_BUSACK == 1);
314 gpio_set_mode(ADp1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
315 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp1_WIDTH
) << ADp1_SHIFT
);
316 gpio_set_mode(ADp2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
317 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp2_WIDTH
) << ADp2_SHIFT
);
318 gpio_set_mode(ADp3_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
319 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp3_WIDTH
) << ADp3_SHIFT
);
324 void z80_request_bus(void)
327 while(Z80_I_BUSACK
== 1);
328 z80_setup_adrbus_active();
331 void z80_release_bus(void)
334 z80_setup_adrbus_tristate();
336 while(Z80_I_BUSACK
== 0);
339 void z80_reset(level_t level
)
341 int x
= level
? -1 : 0;
345 // Z80_O_RST = level;
348 void z80_reset_pulse(void)
353 void z80_busreq(level_t level
)
355 Z80_O_BUSREQ
= level
;
359 int z80_stat_halt(void)
365 void z80_write(uint32_t addr
, uint8_t data
)
367 z80_setaddress(addr
);
369 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
370 z80_setup_dbus_out();
376 uint8_t z80_read(uint32_t addr
)
380 z80_setaddress(addr
);
385 data
= IOFIELD_GET(GPIO_IDR(DB_PORT
),DB_WIDTH
, DB_SHIFT
);
393 void z80_memset(uint32_t addr
, uint8_t data
, int length
)
395 z80_setup_dbus_out();
398 z80_setaddress(addr
++);
399 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
406 void z80_write_block(uint8_t *src
, uint32_t dest
, uint32_t length
)
410 z80_setup_dbus_out();
413 z80_setaddress(dest
++);
415 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
423 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
424 017A' rx.in_idx: ds 1 ;
425 017B' rx.out_idx: ds 1 ;
426 017C' rx.buf: ds rx.buf_len ;
427 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
429 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
430 018D' tx.in_idx: ds 1 ;
431 018E' tx.out_idx: ds 1 ;
432 018F' tx.buf: ds tx.buf_len ;
433 019E' tx.buf_end equ $-1 ; last byte
436 #define fifo_bufsize_mask -3
437 #define fifo_index_in -2
438 #define fifo_index_out -1
449 void z80_memfifo_init(void)
452 fifo_dsc
[fifo_in
].base
= tx_fifo
;
453 fifo_dsc
[fifo_in
].idx_out
= z80_read(tx_fifo
+fifo_index_out
);
454 fifo_dsc
[fifo_in
].idx_in
= z80_read(tx_fifo
+fifo_index_in
);
455 fifo_dsc
[fifo_in
].mask
= z80_read(tx_fifo
+fifo_bufsize_mask
);
457 fifo_dsc
[fifo_out
].base
= rx_fifo
;
458 fifo_dsc
[fifo_out
].idx_out
= z80_read(rx_fifo
+fifo_index_out
);
459 fifo_dsc
[fifo_out
].idx_in
= z80_read(rx_fifo
+fifo_index_in
);
460 fifo_dsc
[fifo_out
].mask
= z80_read(rx_fifo
+fifo_bufsize_mask
);
465 int z80_memfifo_is_empty(fifo_t f
)
467 uint32_t adr
= fifo_dsc
[f
].base
+fifo_index_in
;
474 return idx
== fifo_dsc
[f
].idx_out
;
477 int z80_memfifo_is_full(fifo_t f
)
482 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
483 == z80_read(fifo_dsc
[f
].base
+fifo_index_out
);
489 uint8_t z80_memfifo_getc(fifo_t f
)
493 while (z80_memfifo_is_empty(f
))
497 idx
= fifo_dsc
[f
].idx_out
;
498 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
499 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
500 z80_write(fifo_dsc
[f
].base
+fifo_index_out
, fifo_dsc
[f
].idx_out
);
507 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
511 while (z80_memfifo_is_full(f
))
515 idx
= fifo_dsc
[f
].idx_in
;
516 z80_write(fifo_dsc
[f
].base
+idx
, val
);
517 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
518 z80_write(fifo_dsc
[f
].base
+fifo_index_in
, fifo_dsc
[f
].idx_in
);
522 /*--------------------------------------------------------------------------*/
524 //volatile uint8_t io_infifo[256];
533 /*--------------------------------------------------------------------------*/
535 static void tim1_setup(void)
537 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
538 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
544 /* | TIM_SMCR_ETF_CK_INT_N_2 */
549 TIM1_DIER
= TIM_DIER_TDE
;
553 | TIM_CCMR1_OC1M_FORCE_LOW
554 | TIM_CCMR1_CC1S_OUT
;
556 TIM1_SMCR
|= TIM_SMCR_SMS_TM
;
559 /*--------------------------------------------------------------------------*/
561 static void tim1_ch4_setup(void)
564 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
565 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
568 | TIM_CCMR2_CC4S_IN_TI2
570 | TIM_CCMR2_IC4PSC_OFF
;
573 /* | TIM_CCER_CC4P */
576 /* Enable DMA for channel 4 */
577 TIM1_DIER
= TIM_DIER_CC4DE
;
580 /*--------------------------------------------------------------------------*/
582 static void dma1_ch4_setup(void)
591 DMA1_CMAR4
= (uint32_t) io_infifo
.buf
;
593 #if (DB_SHIFT == 0) || (DB_SHIFT == 8)
594 DMA1_CPAR4
= DB_PORT
+ IDR
+ DB_SHIFT
/8;
596 #error "Databus not byte aligned!"
599 DMA1_CNDTR4
= io_infifo
.count
= NELEMS(io_infifo
.buf
);
601 DMA1_CCR4
|= DMA_CCR_EN
;
604 /*--------------------------------------------------------------------------*/
606 void z80_setup_io_infifo(void)
608 gpio_set_mode(P_BUSACK
, GPIO_MODE_INPUT
,
609 GPIO_CNF_INPUT_FLOAT
, GPIO_BUSACK
| GPIO_IOCS1
);
616 int z80_io_infifo_getc(void)
620 if (io_infifo
.count
!= DMA1_CNDTR4
) {
621 c
= io_infifo
.buf
[NELEMS(io_infifo
.buf
) - io_infifo
.count
--];
622 if (io_infifo
.count
== 0)
623 io_infifo
.count
= NELEMS(io_infifo
.buf
);