z180/cpuinfo.180

   1         .z80                            ; for M80, ignored by SLR assembler
   2         include z180reg.inc
   3
   4 RUN_TPA         equ     0
   5
   6 UUNKNOWN        equ     0       ;Unknown CPU
   7 U8080           equ     1       ;8080
   8 U8085           equ     2       ;8085
   9 UZ80            equ     3       ;Z80
  10 UX180           equ     4       ;HD64180 or higher
  11 UHD64180        equ     5       ;HD64180
  12 UZ80180         equ     6       ;Z80180
  13 UZ8S180         equ     7       ;Z8S180, Z8L180
  14
  15
  16 ;-------------------------------------------------------------------------------
  17
  18
  19    if RUN_TPA
  20 base            equ     0100h
  21    else
  22 base            equ     0
  23    endif
  24
  25
  26         aseg
  27         org     base
  28         jp      start
  29
  30 done:   db      0
  31 result: db      0
  32
  33 ;-------------------------------------------------------------------------------
  34 ; Check if register C exists. D holds mask of bit to test.
  35 ;       return z, if register exists
  36
  37 chk_reg:
  38         in      a,(c)
  39         ld      l,a
  40         ; check, if register is changeable
  41         xor     d               ;
  42         out     (c),a
  43         in      a,(c)           ; get it back
  44         xor     d
  45         out     (c),l           ; set register to original state
  46         cp      l
  47         ret
  48
  49 ;-------------------------------------------------------------------------------
  50 ; Check CPU
  51 ;
  52 ;
  53 ; return:
  54 ;       E = 0   Unknown
  55 ;       E = 1   8080
  56 ;       E = 2   8085
  57 ;       E = 3   Z80
  58 ;       E = 4   HD64180 or higher
  59 ;       E = 5   HD64180
  60 ;       E = 6   Z80180
  61 ;       E = 7   Z8S180, Z8L180
  62 ;
  63 ;-------------------------------------------------------------------------------
  64 ; Registers only in Z180+, not in HD64180
  65 ;       3E      OMCR
  66 ;
  67 ; Registers only in Z8S180/Z8L180
  68 ;       12      ASEXT0
  69 ;       13      ASEXT1
  70 ;       1A      ASTC0L
  71 ;       1B      ASTC0H
  72 ;       1C      ASTC1L
  73 ;       1D      ASTC1H
  74 ;       1E      CMR
  75 ;       1F      CCR
  76 ;       2D      IAR1B
  77 ;
  78 ; Reserved registers
  79 ;       11
  80 ;       19
  81 ;       35
  82 ;       37
  83 ;       3B - 3D
  84
  85 check:
  86         ld      e,U8080         ; Init return val, assume 8080
  87         xor     a
  88         dec     a               ; 00 --> 0FFH   8080/8085: even parity; Z80+: No overflow
  89         jp      po,chk_z80      ; Z80+ if P/V flag reset
  90
  91         ; The 8085 logical AND instructions always set the auxiliary flag ON.
  92         ; The 8080 logical AND instructions set the flag to reflect the
  93         ; logical OR of bit 3 of the values involved in the AND operation.
  94         ; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)
  95
  96         xor     a
  97         and     a               ; 8085 sets, 8080 resets half carry.
  98         daa                     ; A=06 (8085) or A=00 (8080)
  99         ret     z
 100         inc     e
 101         ret
 102
 103 chk_z80:
 104         ld      e,UZ80          ; Assume Z80
 105         daa                     ; Z80: 099H, x180+: 0F9H
 106         cp      99h             ; Result on 180 type cpus is F9 here. Thanks Hitachi
 107         ret     z
 108         inc     e               ; x180
 109
 110         ; At least Hitachi HD64180
 111         ; Test differences in certain internal registers
 112         ; to determine the 180 variant.
 113
 114         ld      b,0
 115         ld      c,icr
 116         in      a,(c)
 117         cp      01FH
 118         jr      z,icr_ok
 119
 120         ;TODO: additional plausibility checks
 121
 122         ret                     ; I/O registers not found
 123
 124         ; Register (base) found.
 125
 126 icr_ok:
 127         inc     e               ; HD64180
 128         out0    (RCR),b         ;
 129         ld      c,omcr          ; Check, if CPU has OMCR register
 130         ld      d,M_IOC         ;
 131         call    chk_reg         ;
 132         ret     nz              ; Register does not exist. It's a HD64180
 133
 134         inc     e               ; Z80180
 135         ld      c,cmr           ; Check, if CPU has CMR register
 136         ld      d,M_LNC         ;
 137         call    chk_reg         ;
 138         ret     nz              ; register does not exist. It's a Z80180
 139
 140         inc     e               ; S180/L180 (class) detected.
 141         ret
 142
 143 ;-------------------------------------------------------------------------------
 144
 145 start:
 146         ld      sp,stack
 147         ld      hl,done
 148         ld      (hl),0
 149         inc     hl
 150         ld      (hl),0
 151         push    hl
 152         call    check
 153         pop     hl
 154         ld      (hl),e
 155         dec     hl
 156         ld      (hl),0ffH
 157         out     (040H),a
 158
 159 ;       ld      a,(wstates)
 160 ;       out0    (DCNTL),a
 161                                 ;Z80    Z180(0W) Z180(MaxW)
 162 loop:                           ;--------------------------
 163         in      a,(050h)        ;11       10     +3*3  19
 164         jp      loop            ;10        9     +3*3  18
 165                                 ;--------------------------
 166                                 ;21       19           37
 167
 168 ;       jr      loop            ;12        8     +2*3  14
 169
 170         rept    8
 171           dw    0
 172         endm
 173 stack:
 174         end
 175
 176 ; vim:set ts=8 noet nowrap