z180/init.180

   1         page    255
   2         .z80
   3
   4         extrn ddtz,bpent
   5         extrn $stack
   6         extrn charini,?const,?conin
   7         extrn ?cono,?conos
   8         extrn romend
   9
  10
  11         global  iobyte
  12         global  isv_sw
  13
  14         include config.inc
  15     if CPU_Z180
  16         include z180reg.inc
  17         include z180.lib
  18     endif
  19
  20
  21
  22
  23 ;----------------------------------------------------------------------
  24
  25         cseg
  26 romstart equ    $
  27
  28         org     romstart+0
  29         jp start
  30
  31 iobyte: db      2
  32
  33 ; restart vectors
  34
  35 rsti    defl    1
  36         rept    7
  37         org     8*rsti + romstart
  38         jp bpent
  39 rsti    defl rsti+1
  40         endm
  41
  42 ;----------------------------------------------------------------------
  43 ; Config space
  44 ;
  45
  46         org     romstart+40h
  47
  48         dw      0
  49         db      0
  50
  51
  52     if ROMSYS
  53 $crom:  defb c$rom              ;
  54     else
  55         db      0               ;
  56     endif
  57
  58 INIWAITS defl   CWAITIO
  59     if  ROMSYS
  60 INIWAITS defl   INIWAITS+CWAITROM
  61     endif
  62
  63 ;----------------------------------------------------------------------
  64
  65         org     romstart+50h
  66 start:
  67         jp      cstart
  68         jp      wstart
  69         jp      ?const
  70         jp      ?conin
  71         jp      ?cono
  72         jp      ?conos
  73         jp      charini
  74
  75 ;----------------------------------------------------------------------
  76
  77 hwini0:
  78     if CPU_Z180
  79         db      3               ;count
  80         db      rcr,CREFSH      ;configure DRAM refresh
  81         db      dcntl,INIWAITS  ;wait states
  82         db      cbar,SYS$CBAR
  83     endif
  84         db     0
  85
  86     if CPU_Z180
  87 dmclrt:                         ;clear ram per dma
  88         db      dmct_e-dmclrt-2 ;
  89         db      sar0l           ;first port
  90         dw      nullbyte        ;src (fixed)
  91 nullbyte:
  92         db      000h            ;src
  93         dw      romend          ;dst (inc), start after "rom" code
  94         db      00h             ;dst
  95         dw      0-romend        ;count (64k)
  96 dmct_e:
  97         db      0
  98     endif
  99
 100
 101 cstart:
 102     if CPU_Z180
 103
 104         push af
 105         in0 a,(itc)             ;Illegal opcode trap?
 106         jp m,??st01
 107         ld a,i                  ;I register == 0 ?
 108         jr z,hw_reset           ;    yes, harware reset
 109
 110 ??st01:
 111         ; TODO: SYS$CBR
 112         ld      a,(syscbr)
 113         out0    (cbr),a
 114         pop af                  ;restore registers
 115         jp bpent                ;
 116
 117 hw_reset:
 118         di                      ;0058
 119         ld      a,CREFSH
 120         out0    (rcr),a         ;       configure DRAM refresh
 121         ld      a,CWAITIO
 122         out0    (dcntl),a       ;       wait states
 123
 124         ld      a,M_NCD         ;No Clock Divide
 125         out0    (ccr),a
 126 ;       ld      a,M_X2CM        ;X2 Clock Multiplier
 127 ;       out0    (cmr),a
 128     else
 129         di
 130         xor     a
 131         ld      (@cbnk),a
 132     endif
 133
 134 ; check warm start mark
 135
 136         ld ix,mark_55AA         ; top of common area
 137         ld a,0aah               ;
 138         cp (ix+000h)            ;
 139         jr nz,kstart            ;
 140         cp (ix+002h)            ;
 141         jr nz,kstart            ;
 142         cpl                     ;
 143         cp (ix+001h)            ;
 144         jr nz,kstart            ;
 145         cp (ix+003h)            ;
 146         jr nz,kstart            ;
 147         ld sp,$stack            ; mark found, check
 148         jp z,wstart             ; check ok,
 149
 150 ; ram not ok, initialize    --  kstart --
 151
 152 kstart:
 153     if CPU_Z180
 154         ld      a,SYS$CBAR
 155         out0    (cbar),a
 156         ld      a,SYS$CBR
 157         out0    (cbr),a
 158     endif
 159
 160         ld      sp,$stack       ;01e1
 161
 162 ; Clear RAM using DMA0
 163
 164     if CPU_Z180
 165      if 0
 166
 167         ld      hl,dmclrt       ;load DMA registers
 168         call    ioiniml
 169         ld      a,0cbh          ;01ef   dst +1, src fixed, burst
 170         out0    (dmode),a       ;01f1
 171
 172         ld      b,512/64
 173         ld      a,062h          ;01f4   enable dma0,
 174 ??cl_1:
 175         out0    (dstat),a       ;01f9   clear (up to) 64k
 176         djnz    ??cl_1          ;       end of RAM?
 177
 178      endif
 179     endif
 180
 181         ld      hl,055AAh       ;set warm start mark
 182         ld      (mark_55AA),hl
 183         ld      (mark_55AA+2),hl
 184
 185 ;       --  wstart  --
 186
 187 wstart:
 188         call    sysram_init     ;027f
 189         call    ivtab_init
 190     if CPU_Z180
 191         call    prt0_init
 192     endif
 193
 194         call    charini
 195         call    bufferinit
 196
 197     if CPU_Z80
 198         ld      a,0
 199         call    selbnk
 200     endif
 201
 202         im 2                    ;?030e
 203         ei                      ;0282
 204
 205         call ?const             ;0284
 206         call ?const             ;0287
 207         or a                    ;028a
 208         call nz,?conin          ;028d
 209
 210     if CPU_Z180
 211         ld e,0                  ;Sys$Bank
 212     else
 213 ; TODO:
 214     endif
 215         jp ddtz                 ;0290
 216
 217
 218     if CPU_Z180
 219 ; TODO: SYS$CBR
 220 syscbr: db      1
 221     endif
 222
 223 ;
 224 ;----------------------------------------------------------------------
 225 ;
 226
 227 ;TODO: Make a ringbuffer module.
 228
 229         global  buf.init
 230
 231 buf.init:
 232         ld      (ix+o.in_idx),0
 233         ld      (ix+o.out_idx),0
 234         ld      (ix+o.mask),a
 235         ret
 236
 237 ;----------------------------------------------------------------------
 238 if 0
 239         extrn   msginit,msg_tx_fifo,msg_rx_fifo
 240         extrn   msg.sout
 241
 242 bufferinit:
 243
 244         ld      de,msg_tx_fifo
 245         in0     a,cbr
 246         call    log2phys
 247         ld      (40h+0),hl
 248         ld      (40h+2),a
 249
 250 ;       ld      (bufdat+1),hl
 251 ;       ld      (bufdat+3),a
 252 ;       ld      a,1
 253 ;       ld      (bufdat+0),a
 254 ;       ld      hl,inimsg
 255 ;       call    msg.sout
 256
 257         ld      de,msg_rx_fifo
 258         in0     a,cbr
 259         call    log2phys
 260         ld      (bufdat+1),hl
 261         ld      (bufdat+3),a
 262         ld      a,2
 263         ld      (bufdat+0),a
 264         ld      hl,inimsg
 265         call    msg.sout
 266
 267         ret
 268
 269 inimsg:
 270         db      inimsg_e - $ - 1
 271         db      0AEh
 272         db      inimsg_e - $ - 1
 273         db      0
 274 bufdat:
 275         db      0
 276         dw      0
 277         db      0
 278 inimsg_e:
 279
 280 endif
 281
 282 ;----------------------------------------------------------------------
 283
 284         extrn   msginit,msg.sout
 285         extrn   mtx.fifo,mrx.fifo
 286         extrn   co.fifo,ci.fifo
 287
 288
 289 bufferinit:
 290     if CPU_Z180
 291         call    msginit
 292
 293         ld      hl,buffers
 294         ld      b,buftablen
 295 bfi_1:
 296         ld      a,(hl)
 297         inc     hl
 298         ld      (bufdat+0),a
 299         ld      e,(hl)
 300         inc     hl
 301         ld      d,(hl)
 302         inc     hl
 303         push    hl
 304
 305         or      a
 306         jr      nz,bfi_2
 307         call    hw_log2phys
 308         ld      (40h+0),hl
 309         ld      (40h+2),a
 310         out0    (AVRINT5),a
 311         jr      bfi_3
 312 bfi_2:
 313         call    hw_log2phys
 314         ld      (bufdat+1),hl
 315         ld      (bufdat+3),a
 316         ld      hl,inimsg
 317         call    msg.sout
 318 bfi_3:
 319         pop     hl
 320         djnz    bfi_1
 321         ret
 322
 323     else
 324
 325         call    msginit
 326
 327         ld      hl,buffers
 328         ld      b,buftablen
 329 bfi_1:
 330         ld      a,(hl)
 331         inc     hl
 332         ld      (bufdat+0),a
 333         ld      e,(hl)
 334         inc     hl
 335         ld      d,(hl)
 336         inc     hl
 337         ex      de,hl
 338
 339         or      a
 340         jr      nz,bfi_2
 341
 342         ld      a,(@cbnk)
 343         call    bnk2phys
 344
 345         ld      (40h+0),hl
 346         ld      (40h+2),a
 347         out     (AVRINT5),a
 348         jr      bfi_3
 349 bfi_2:
 350
 351         ld      a,(@cbnk)
 352         call    bnk2phys
 353
 354         ld      (bufdat+1),hl
 355         ld      (bufdat+3),a
 356         ld      hl,inimsg
 357         call    msg.sout
 358 bfi_3:
 359         ex      de,hl
 360         djnz    bfi_1
 361         ret
 362     endif
 363
 364 buffers:
 365         db      0
 366         dw      mtx.fifo
 367         db      1
 368         dw      mrx.fifo
 369         db      2
 370         dw      co.fifo
 371         db      3
 372         dw      ci.fifo
 373 buftablen equ   ($ - buffers)/3
 374
 375 inimsg:
 376         db      inimsg_e - $ -1
 377         db      0AEh
 378         db      inimsg_e - $ -1
 379         db      0
 380 bufdat:
 381         db      0
 382         dw      0
 383         db      0
 384 inimsg_e:
 385
 386
 387 ;
 388 ;----------------------------------------------------------------------
 389 ;
 390
 391 sysram_init:
 392         ld hl,sysramw
 393         ld de,topcodsys
 394         ld bc,sysrame-sysramw
 395         ldir
 396
 397         ret
 398
 399 ;----------------------------------------------------------------------
 400
 401 ivtab_init:
 402         ld      hl,ivtab        ;
 403         ld      a,h             ;
 404         ld      i,a             ;
 405     if CPU_Z180
 406         out0    (il),l          ;
 407     endif
 408
 409 ; Let all vectors point to spurious int routines.
 410
 411         ld      d,high sp.int0
 412         ld      a,low  sp.int0
 413         ld      b,9
 414 ivt_i1:
 415         ld      (hl),a
 416         inc     l
 417         ld      (hl),d
 418         inc     l
 419         add     a,sp.int.len
 420         djnz    ivt_i1
 421         ret
 422
 423 ;----------------------------------------------------------------------
 424
 425     if CPU_Z180
 426 prt0_init:
 427         ld      a,i
 428         ld      h,a
 429         in0     a,(il)
 430         and     0E0h
 431         or      IV$PRT0
 432         ld      l,a
 433         ld      (hl),low  iprt0
 434         inc     hl
 435         ld      (hl),high iprt0
 436         ld      hl,prt0itab
 437         call    ioiniml
 438         ret
 439
 440 prt0itab:
 441         db      prt0it_e-prt0itab-2
 442         db      tmdr0l
 443         dw      PRT_TC10MS
 444         dw      PRT_TC10MS
 445         db      M_TIE0+M_TDE0   ;enable timer 0 interrupt and down count.
 446 prt0it_e:
 447         db      0
 448     endif
 449
 450
 451 ;
 452 ;----------------------------------------------------------------------
 453 ;
 454
 455     if CPU_Z180
 456 io.ini:
 457      if 0
 458         push    bc
 459         ld      b,0             ;high byte port adress
 460 ioi_nxt:
 461         ld      a,(hl)          ;count
 462         inc     hl
 463         or      a
 464         jr      z,ioi_e
 465
 466         ld      c,(hl)          ;port address
 467         inc     hl
 468 ioi_r:
 469         outi
 470         inc     b               ;outi decrements b
 471         dec     a
 472         jr      nz,ioi_r
 473         jr      ioi_nxt
 474 ioi_e:
 475         pop     bc
 476         ret
 477
 478      else ;(if 1/0)
 479
 480         push    bc
 481         jr      ioi_nxt
 482 ioi_l:
 483         ld      c,(hl)          ;port address
 484         inc     hl
 485         inc     c
 486 ioi_r:
 487         dec     c               ;otim increments c
 488         otim
 489         jr      z,ioi_r
 490 ioi_nxt:
 491         ld      b,(hl)          ;count
 492         inc     hl
 493         inc     b               ;stop if count == 0
 494         djnz    ioi_l
 495         pop     bc
 496         ret
 497
 498      endif ;(1/0)
 499
 500     else
 501
 502 io.ini:
 503         push    bc
 504         jr      ioi_nxt
 505 ioi_l:
 506         ld      c,(hl)          ;port address
 507         inc     hl
 508         otir
 509 ioi_nxt:
 510         ld      b,(hl)          ;count
 511         inc     hl
 512         inc     b
 513         djnz    ioi_l
 514     endif
 515         pop     bc
 516         ret
 517
 518 ;----------------------------------------------------------------------
 519
 520     if CPU_Z180
 521
 522         global ioiniml
 523
 524 ioiniml:
 525         push    bc
 526         xor     a
 527 ioml_lp:
 528         ld      b,(hl)
 529         inc     hl
 530         cp      b
 531         jr      z,ioml_e
 532
 533         ld      c,(hl)
 534         inc     hl
 535         otimr
 536         jr      ioml_lp
 537 ioml_e:
 538         pop     bc
 539         ret     z
 540     endif
 541
 542 io.ini.l:
 543 ;
 544
 545
 546
 547 ;----------------------------------------------------------------------
 548 ;
 549     if CPU_Z180
 550
 551 ; a: Bank number
 552 ;
 553 ; out a: bbr value
 554
 555 bnk2log:
 556         push    bc
 557         ld      b,a
 558         ld      c,CA
 559         mlt     bc
 560         add     a,10h
 561         pop     bc
 562         ret
 563
 564 ; de: Log. Address
 565 ;  a: Bank number
 566 ;
 567 ;out ahl: Phys. (linear) Address
 568
 569
 570 bnk2phys:
 571         call    bnk2log
 572
 573         ; fall thru
 574 ;--------------------------------------------------------------
 575 ;
 576 ; de: Log. Address
 577 ;  a: Bank base (bbr)
 578 ;
 579 ; OP: ahl = (a<<12) + (d<<8) + e
 580 ;
 581 ;out ahl: Phys. (linear) Address
 582
 583
 584 log2phys:
 585         push    bc              ;
 586         ld      c,a             ;
 587         ld      b,16            ;
 588         mlt     bc              ;  bc = a<<4
 589         ld      l,d             ;4
 590         ld      h,0             ;6
 591         add     hl,bc           ;7  bc + d == a<<4 + d
 592         ld      a,h             ;4
 593         ld      h,l             ;4
 594         ld      l,e             ;4
 595         pop     bc              ;
 596         ret                     ;
 597
 598     if 0
 599
 600 log2phys:
 601         push    bc              ;
 602         ld      b,a             ;
 603         ld      c,16            ;
 604         mlt     bc              ; bc = a<<4
 605         ld      a,c             ;4
 606         add     a,h             ;4
 607         ld      h,a             ;4
 608         ld      a,b             ;4
 609         adc     a,0             ;6
 610         pop     bc              ;
 611         ret                     ;
 612
 613     endif
 614 ;--------------------------------------------------------------
 615 ;
 616 ; de: Log. Address
 617 ;
 618 ;
 619 ; OP: ahl = (bankbase<<12) + (d<<8) + e
 620 ;
 621 ;out ahl: Phys. (linear) Address
 622
 623
 624 hw_log2phys:
 625         push    bc              ;
 626         in0     c,(cbar)
 627         ld      a,d
 628         or      00fh
 629         cp      c
 630         jr      c,hlp_1
 631         in0     c,(cbr)
 632         jr      hlp_e
 633 hlp_1:
 634         ld      b,16
 635         mlt     bc
 636         ld      a,d
 637         cp      c
 638         ld      c,0
 639         jr      c,hlp_e
 640         in0     c,(bbr)
 641 hlp_e:
 642         ld      b,16            ;
 643         mlt     bc              ;bc = a<<4
 644         ld      l,d             ;
 645         ld      h,0             ;
 646         add     hl,bc           ;bc + d == a<<4 + d
 647         ld      a,h             ;
 648         ld      h,l             ;
 649         ld      l,e             ;
 650         pop     bc              ;
 651         ret                     ;
 652
 653     else
 654
 655 ;
 656 ;----------------------------------------------------------------------
 657 ;
 658
 659 bnk2phys:
 660         sla     h
 661         jr      nc,b2p_1                ;A15=1 --> common
 662         ld      a,3
 663 b2p_1:
 664         srl     a
 665         rr      h
 666         ret
 667
 668     endif
 669
 670 ;--------------------------------------------------------------
 671 ;
 672 ;return:
 673 ; hl = hl + a
 674 ; Flags undefined
 675 ;
 676
 677 add_hl_a:
 678         add a,l
 679         ld l,a
 680         ret nc
 681         inc h
 682         ret
 683
 684 ; ---------------------------------------------------------
 685
 686 sysramw:
 687
 688         .phase isvsw_loc
 689 topcodsys:
 690
 691 ; Trampoline for interrupt routines in banked ram.
 692 ; Switch stack pointer to "system" stack in top ram
 693 ; Save cbar
 694
 695 isv_sw:                         ;
 696         ex (sp),hl              ;       save hl, return adr in hl
 697         push de                 ;
 698         push af                 ;
 699         ex de,hl                ;
 700         ld hl,0                 ;
 701         add hl,sp               ;
 702         ld a,h                  ;
 703         cp 0f8h                 ;
 704         jr nc,isw_1             ;
 705         ld sp,$stack            ;
 706 isw_1:
 707         push hl                 ;
 708         in0 h,(cbar)            ;
 709         push hl                 ;
 710         ld a,SYS$CBAR           ;
 711         out0 (cbar),a           ;
 712         ex de,hl                ;
 713         ld e,(hl)               ;
 714         inc hl                  ;
 715         ld d,(hl)               ;
 716         ex de,hl                ;
 717         push bc                 ;
 718         call jphl               ;
 719
 720         pop bc                  ;
 721         pop hl                  ;
 722         out0 (cbar),h           ;
 723         pop hl                  ;
 724         ld sp,hl                ;
 725         pop af                  ;
 726         pop de                  ;
 727         pop hl                  ;
 728         ei                      ;
 729         ret                     ;
 730 jphl:
 731         jp (hl)                 ;
 732
 733 ; ---------------------------------------------------------
 734
 735     if CPU_Z180
 736
 737 iprt0:
 738         push    af
 739         push    hl
 740         in0     a,(tcr)
 741         in0     a,(tmdr0l)
 742         in0     a,(tmdr0h)
 743         ld      a,(tim_ms)
 744         inc     a
 745         cp      100
 746         jr      nz,iprt_1
 747         xor     a
 748         ld      hl,(tim_s)
 749         inc     hl
 750         ld      (tim_s),hl
 751 iprt_1:
 752         ld      (tim_ms),a
 753         pop     hl
 754         pop     af
 755         ei
 756         ret
 757
 758     endif
 759
 760 ; ---------------------------------------------------------
 761
 762 sp.int0:
 763         ld      a,0d0h
 764         jr      sp.i.1
 765 sp.int.len equ  $-sp.int0
 766         ld      a,0d1h
 767         jr      sp.i.1
 768         ld      a,0d2h
 769         jr      sp.i.1
 770         ld      a,0d3h
 771         jr      sp.i.1
 772         ld      a,0d4h
 773         jr      sp.i.1
 774         ld      a,0d5h
 775         jr      sp.i.1
 776         ld      a,0d6h
 777         jr      sp.i.1
 778         ld      a,0d7h
 779         jr      sp.i.1
 780         ld      a,0d8h
 781 sp.i.1:
 782 ;       out     (80h),a
 783         halt
 784
 785 ; ---------------------------------------------------------
 786
 787     if CPU_Z80
 788
 789 ; Get IFF2
 790 ; This routine may not be loaded in page zero
 791 ;
 792 ; return Carry clear, if INTs are enabled.
 793 ;
 794         global getiff
 795 getiff:
 796         xor     a               ;clear accu and carry
 797         push    af              ;stack bottom := 00xxh
 798         pop     af
 799         ld      a,i             ;P flag := IFF2
 800         ret     pe              ;exit carry clear, if enabled
 801         dec     sp
 802         dec     sp              ;has stack bottom been overwritten?
 803         pop     af
 804         and     a               ;if not 00xxh, INTs were
 805         ret     nz              ;actually enabled
 806         scf                     ;Otherwise, they really are disabled
 807         ret
 808
 809 ;----------------------------------------------------------------------
 810
 811         global  selbnk
 812
 813 ; a: bank (0..2)
 814
 815 selbnk:
 816         push    bc
 817         ld      c,a
 818         call    getiff
 819         push    af
 820
 821         ld      a,c
 822         di
 823         ld      (@cbnk),a
 824         ld      a,5
 825         out     (SIOAC),a
 826         ld      a,(mm_sio0)
 827         rla
 828         srl     c
 829         rra
 830         out     (SIOAC),a
 831         ld      (mm_sio0),a
 832
 833         ld      a,5
 834         out     (SIOBC),a
 835         ld      a,(mm_sio1)
 836         rla
 837         srl     c
 838         rra
 839         out     (SIOBC),a
 840         ld      (mm_sio1),a
 841         pop     af
 842         pop     bc
 843         ret     c                       ;INTs were disabled
 844         ei
 845         ret
 846
 847 ;----------------------------------------------------------------------
 848
 849 ; c: bank (0..2)
 850
 851     if 0
 852
 853 selbnk:
 854         ld      a,(@cbnk)
 855         xor     c
 856         and     3
 857         ret     z               ;no change
 858
 859         call    getiff
 860         push    af
 861         ld      a,c
 862         di
 863         ld      (@cbnk),a
 864         ld      a,5
 865         out     (SIOAC),a
 866         ld      a,(mm_sio0)
 867         rla
 868         srl     c
 869         rra
 870         out     (SIOAC),a
 871         ld      (mm_sio0),a
 872
 873         ld      a,5
 874         out     (SIOBC),a
 875         ld      a,(mm_sio1)
 876         rla
 877         srl     c
 878         rra
 879         out     (SIOBC),a
 880         ld      (mm_sio1),a
 881         pop     af
 882         ret     nc                      ;INTs were disabled
 883         ei
 884         ret
 885
 886     endif
 887
 888 ;----------------------------------------------------------------------
 889
 890     if 0
 891         ex      af,af'
 892         push    af
 893         ex      af,af'
 894
 895         rra
 896         jr      nc,stbk1
 897         ex      af,af'
 898         ld      a,5
 899         out     (SIOAC),a
 900         ld      a,(mm_sio0)
 901         rla
 902         srl     c
 903         rra
 904         out     (SIOAC),a
 905         ld      (mm_sio1),a
 906         ex      af,af'
 907
 908 stbk1:
 909         rra
 910         jr      nc,stbk2
 911         ex      af,af'
 912         ld      a,5
 913         out     (SIOBC),a
 914         ld      a,(mm_sio1)
 915         rla
 916         srl     c
 917         rra
 918         out     (SIOBC),a
 919         ld      (mm_sio1),a
 920         ex      af,af'
 921
 922 stbk2:
 923     endif
 924
 925         global  @cbnk
 926         global  mm_sio0, mm_sio1
 927
 928 @cbnk:  db      0               ; current bank (0..2)
 929 mm_sio0:
 930         ds      1
 931 mm_sio1:
 932         ds      1
 933
 934
 935     endif
 936
 937 ;----------------------------------------------------------------------
 938
 939 curph   defl    $
 940         .dephase
 941 sysrame:
 942         .phase curph
 943 tim_ms: db      0
 944 tim_s:  dw      0
 945         .dephase
 946
 947 ;-----------------------------------------------------
 948
 949
 950         cseg
 951
 952         ;.phase 0ffc0h
 953 ;ivtab  equ     0ffc0h          ; 0ffc0h        ;int vector table
 954         ;.dephase
 955
 956         ;.phase 0fffah
 957 mark_55AA equ 0 - 2 - 4         ;2 byte for trap stack
 958         ;ds     4
 959         ;.dephase
 960
 961
 962         end
 963