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1 page 255\r
2 .z80\r
3\r
4 extrn ddtz,bpent\r
5 extrn $stack\r
30d1329e 6 extrn charini,?const,?conin\r
8df5b655 7 extrn ?cono,?conos\r
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8 extrn romend\r
9\r
10\r
64cc2207 11 global iobyte\r
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12 global isv_sw\r
13\r
14 include config.inc\r
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15 if CPU_Z180\r
16 include z180reg.inc\r
17 include z180.lib\r
18 endif\r
815c1735 19\r
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20\r
21\r
22\r
23;----------------------------------------------------------------------\r
24\r
25 cseg\r
8df5b655 26romstart equ $\r
a16ba2b0 27\r
8df5b655 28 org romstart+0\r
815c1735 29 jp start\r
a16ba2b0 30\r
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31iobyte: db 2\r
32\r
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33; restart vectors\r
34\r
35rsti defl 1\r
36 rept 7\r
8df5b655 37 org 8*rsti + romstart\r
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38 jp bpent\r
39rsti defl rsti+1\r
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40 endm\r
41\r
42;----------------------------------------------------------------------\r
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43; Config space\r
44;\r
45\r
8df5b655 46 org romstart+40h\r
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47\r
48 dw 0\r
49 db 0\r
50\r
a16ba2b0 51\r
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52 if ROMSYS\r
53$crom: defb c$rom ;\r
54 else\r
55 db 0 ;\r
56 endif\r
a16ba2b0 57\r
8df5b655 58INIWAITS defl CWAITIO\r
fecee241 59 if ROMSYS\r
8df5b655 60INIWAITS defl INIWAITS+CWAITROM\r
fecee241 61 endif\r
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62\r
63;----------------------------------------------------------------------\r
64\r
65 org romstart+50h\r
66start:\r
67 jp cstart\r
68 jp wstart\r
69 jp ?const\r
70 jp ?conin\r
71 jp ?cono\r
72 jp ?conos\r
73 jp charini\r
74\r
75;----------------------------------------------------------------------\r
76\r
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77hwini0:\r
78 if CPU_Z180\r
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79 db 3 ;count\r
80 db rcr,CREFSH ;configure DRAM refresh\r
81 db dcntl,INIWAITS ;wait states\r
82 db cbar,SYS$CBAR\r
fecee241 83 endif\r
2fe44122 84 db 0\r
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85\r
86 if CPU_Z180\r
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87dmclrt: ;clear ram per dma\r
88 db dmct_e-dmclrt-2 ;\r
89 db sar0l ;first port\r
815c1735 90 dw nullbyte ;src (fixed)\r
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91nullbyte:\r
92 db 000h ;src\r
93 dw romend ;dst (inc), start after "rom" code\r
94 db 00h ;dst\r
95 dw 0-romend ;count (64k)\r
96dmct_e:\r
2fe44122 97 db 0\r
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98 endif\r
99\r
a16ba2b0 100\r
8df5b655 101cstart:\r
fecee241 102 if CPU_Z180\r
a16ba2b0 103\r
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104 push af\r
105 in0 a,(itc) ;Illegal opcode trap?\r
106 jp m,??st01\r
107 ld a,i ;I register == 0 ?\r
fecee241 108 jr z,hw_reset ; yes, harware reset\r
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109\r
110??st01:\r
fecee241 111 ; TODO: SYS$CBR\r
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112 ld a,(syscbr)\r
113 out0 (cbr),a\r
114 pop af ;restore registers\r
30d1329e 115 jp bpent ;\r
a16ba2b0 116\r
fecee241 117hw_reset:\r
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118 di ;0058\r
119 ld a,CREFSH\r
120 out0 (rcr),a ; configure DRAM refresh\r
121 ld a,CWAITIO\r
122 out0 (dcntl),a ; wait states\r
123\r
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124 ld a,M_NCD ;No Clock Divide\r
125 out0 (ccr),a\r
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126; ld a,M_X2CM ;X2 Clock Multiplier\r
127; out0 (cmr),a\r
fecee241 128 else\r
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129 di\r
130 xor a\r
131 ld (@cbnk),a\r
fecee241 132 endif\r
815c1735 133\r
fecee241 134; check warm start mark\r
a16ba2b0 135\r
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136 ld ix,mark_55AA ; top of common area\r
137 ld a,0aah ;\r
138 cp (ix+000h) ;\r
139 jr nz,kstart ;\r
140 cp (ix+002h) ;\r
141 jr nz,kstart ;\r
142 cpl ;\r
143 cp (ix+001h) ;\r
144 jr nz,kstart ;\r
145 cp (ix+003h) ;\r
146 jr nz,kstart ;\r
147 ld sp,$stack ; mark found, check\r
148 jp z,wstart ; check ok,\r
fecee241 149\r
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150; ram not ok, initialize -- kstart --\r
151\r
152kstart:\r
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153 if CPU_Z180\r
154 ld a,SYS$CBAR\r
155 out0 (cbar),a\r
156 ld a,SYS$CBR\r
8df5b655 157 out0 (cbr),a\r
fecee241 158 endif\r
a16ba2b0 159\r
a16ba2b0 160 ld sp,$stack ;01e1\r
815c1735 161\r
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162; Clear RAM using DMA0\r
163\r
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164 if CPU_Z180\r
165 if 0\r
8df5b655 166 \r
a16ba2b0 167 ld hl,dmclrt ;load DMA registers\r
2fe44122 168 call ioiniml\r
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169 ld a,0cbh ;01ef dst +1, src fixed, burst\r
170 out0 (dmode),a ;01f1\r
171\r
172 ld b,512/64\r
815c1735 173 ld a,062h ;01f4 enable dma0,\r
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174??cl_1:\r
175 out0 (dstat),a ;01f9 clear (up to) 64k\r
176 djnz ??cl_1 ; end of RAM?\r
8df5b655 177 \r
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178 endif\r
179 endif\r
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180\r
181 ld hl,055AAh ;set warm start mark\r
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182 ld (mark_55AA),hl\r
183 ld (mark_55AA+2),hl\r
184\r
185; -- wstart --\r
a16ba2b0 186\r
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187wstart:\r
188 call sysram_init ;027f\r
189 call ivtab_init\r
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190 if CPU_Z180\r
191 call prt0_init\r
192 endif\r
a16ba2b0 193\r
30d1329e 194 call charini\r
bad2d92d 195 call bufferinit\r
a16ba2b0 196\r
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197 if CPU_Z80\r
198 ld a,0\r
199 call selbnk\r
200 endif\r
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201\r
202 im 2 ;?030e\r
203 ei ;0282\r
204\r
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205 call ?const ;0284\r
206 call ?const ;0287\r
a16ba2b0 207 or a ;028a\r
30d1329e 208 call nz,?conin ;028d\r
815c1735 209\r
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210 if CPU_Z180\r
211 ld e,0 ;Sys$Bank\r
212 else\r
8df5b655 213; TODO:\r
fecee241 214 endif\r
a16ba2b0 215 jp ddtz ;0290\r
815c1735 216\r
30d1329e 217\r
fecee241 218 if CPU_Z180\r
8df5b655 219; TODO: SYS$CBR\r
30d1329e 220syscbr: db 1\r
fecee241 221 endif\r
30d1329e 222\r
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223;\r
224;----------------------------------------------------------------------\r
225;\r
226\r
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227;TODO: Make a ringbuffer module.\r
228\r
229 global buf.init\r
815c1735 230\r
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231buf.init:\r
232 ld (ix+o.in_idx),0\r
233 ld (ix+o.out_idx),0\r
234 ld (ix+o.mask),a\r
235 ret\r
236\r
237;----------------------------------------------------------------------\r
6a4e9540 238if 0\r
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239 extrn msginit,msg_tx_fifo,msg_rx_fifo\r
240 extrn msg.sout\r
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241\r
242bufferinit:\r
349c01b1 243\r
bad2d92d 244 ld de,msg_tx_fifo\r
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245 in0 a,cbr\r
246 call log2phys\r
247 ld (40h+0),hl\r
248 ld (40h+2),a\r
bad2d92d 249\r
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250; ld (bufdat+1),hl\r
251; ld (bufdat+3),a\r
252; ld a,1\r
253; ld (bufdat+0),a\r
254; ld hl,inimsg\r
255; call msg.sout\r
349c01b1 256\r
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257 ld de,msg_rx_fifo\r
258 in0 a,cbr\r
259 call log2phys\r
260 ld (bufdat+1),hl\r
261 ld (bufdat+3),a\r
6a4e9540 262 ld a,2\r
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263 ld (bufdat+0),a\r
264 ld hl,inimsg\r
265 call msg.sout\r
349c01b1 266\r
bad2d92d 267 ret\r
a16ba2b0 268\r
349c01b1 269inimsg:\r
bad2d92d 270 db inimsg_e - $ - 1\r
3531528e 271 db 0AEh\r
bad2d92d 272 db inimsg_e - $ - 1\r
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273 db 0\r
274bufdat:\r
275 db 0\r
276 dw 0\r
277 db 0\r
278inimsg_e:\r
bad2d92d 279\r
6a4e9540 280endif\r
fecee241 281\r
349c01b1 282;----------------------------------------------------------------------\r
4caee1ec 283\r
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284 extrn msginit,msg.sout\r
285 extrn mtx.fifo,mrx.fifo\r
286 extrn co.fifo,ci.fifo\r
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287\r
288\r
a16ba2b0 289bufferinit:\r
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290 if CPU_Z180\r
291 call msginit\r
815c1735 292\r
a16ba2b0 293 ld hl,buffers\r
6a4e9540 294 ld b,buftablen\r
a16ba2b0 295bfi_1:\r
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296 ld a,(hl)\r
297 inc hl\r
298 ld (bufdat+0),a\r
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299 ld e,(hl)\r
300 inc hl\r
301 ld d,(hl)\r
302 inc hl\r
303 push hl\r
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304\r
305 or a\r
306 jr nz,bfi_2\r
8df5b655 307 call hw_log2phys\r
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308 ld (40h+0),hl\r
309 ld (40h+2),a\r
310 out0 (AVRINT5),a\r
311 jr bfi_3 \r
312bfi_2:\r
8df5b655 313 call hw_log2phys\r
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314 ld (bufdat+1),hl\r
315 ld (bufdat+3),a\r
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316 ld hl,inimsg\r
317 call msg.sout\r
6a4e9540 318bfi_3:\r
a16ba2b0 319 pop hl\r
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320 djnz bfi_1\r
321 ret\r
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322\r
323 else\r
324\r
325 call msginit\r
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326\r
327 ld hl,buffers\r
328 ld b,buftablen\r
329bfi_1:\r
330 ld a,(hl)\r
331 inc hl\r
332 ld (bufdat+0),a\r
333 ld e,(hl)\r
334 inc hl\r
335 ld d,(hl)\r
336 inc hl\r
337 ex de,hl\r
338\r
339 or a\r
340 jr nz,bfi_2\r
341\r
342 ld a,(@cbnk)\r
343 call bnk2phys\r
344\r
345 ld (40h+0),hl\r
346 ld (40h+2),a\r
347 out (AVRINT5),a\r
348 jr bfi_3\r
349bfi_2:\r
350\r
351 ld a,(@cbnk)\r
352 call bnk2phys\r
353\r
354 ld (bufdat+1),hl\r
355 ld (bufdat+3),a\r
356 ld hl,inimsg\r
357 call msg.sout\r
358bfi_3:\r
359 ex de,hl\r
360 djnz bfi_1\r
361 ret\r
fecee241 362 endif\r
a16ba2b0 363\r
a16ba2b0 364buffers:\r
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365 db 0\r
366 dw mtx.fifo\r
367 db 1\r
368 dw mrx.fifo\r
369 db 2\r
370 dw co.fifo\r
371 db 3\r
372 dw ci.fifo\r
373buftablen equ ($ - buffers)/3\r
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374\r
375inimsg:\r
6a4e9540 376 db inimsg_e - $ -1\r
3531528e 377 db 0AEh\r
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378 db inimsg_e - $ -1\r
379 db 0\r
380bufdat:\r
381 db 0\r
382 dw 0\r
383 db 0\r
e598b357 384inimsg_e:\r
a16ba2b0 385\r
4caee1ec 386\r
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387;\r
388;----------------------------------------------------------------------\r
389;\r
390\r
391sysram_init:\r
392 ld hl,sysramw\r
393 ld de,topcodsys\r
394 ld bc,sysrame-sysramw\r
395 ldir\r
396\r
397 ret\r
398\r
399;----------------------------------------------------------------------\r
400\r
401ivtab_init:\r
402 ld hl,ivtab ;\r
403 ld a,h ;\r
404 ld i,a ;\r
fecee241 405 if CPU_Z180\r
a16ba2b0 406 out0 (il),l ;\r
fecee241 407 endif\r
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408\r
409; Let all vectors point to spurious int routines.\r
410\r
411 ld d,high sp.int0\r
412 ld a,low sp.int0\r
413 ld b,9\r
815c1735 414ivt_i1:\r
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415 ld (hl),a\r
416 inc l\r
417 ld (hl),d\r
418 inc l\r
419 add a,sp.int.len\r
420 djnz ivt_i1\r
421 ret\r
422\r
4caee1ec 423;----------------------------------------------------------------------\r
a16ba2b0 424\r
fecee241 425 if CPU_Z180\r
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426prt0_init:\r
427 ld a,i\r
428 ld h,a\r
429 in0 a,(il)\r
430 and 0E0h\r
431 or IV$PRT0\r
432 ld l,a\r
433 ld (hl),low iprt0\r
434 inc hl\r
435 ld (hl),high iprt0\r
436 ld hl,prt0itab\r
2fe44122 437 call ioiniml\r
a16ba2b0 438 ret\r
815c1735 439\r
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440prt0itab:\r
441 db prt0it_e-prt0itab-2\r
442 db tmdr0l\r
443 dw PRT_TC10MS\r
444 dw PRT_TC10MS\r
445 db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.\r
446prt0it_e:\r
2fe44122 447 db 0\r
fecee241 448 endif\r
a16ba2b0 449\r
4caee1ec 450\r
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451;\r
452;----------------------------------------------------------------------\r
453;\r
454\r
2fe44122 455 if CPU_Z180\r
a16ba2b0 456io.ini:\r
2fe44122 457 if 0\r
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458 push bc\r
459 ld b,0 ;high byte port adress\r
2fe44122 460ioi_nxt:\r
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461 ld a,(hl) ;count\r
462 inc hl\r
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463 or a\r
464 jr z,ioi_e\r
2fe44122 465\r
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466 ld c,(hl) ;port address\r
467 inc hl\r
2fe44122 468ioi_r:\r
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469 outi\r
470 inc b ;outi decrements b\r
471 dec a\r
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472 jr nz,ioi_r\r
473 jr ioi_nxt\r
fecee241 474ioi_e: \r
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475 pop bc\r
476 ret\r
477 \r
478 else ;(if 1/0)\r
479 \r
480 push bc\r
481 jr ioi_nxt\r
482ioi_l:\r
483 ld c,(hl) ;port address\r
484 inc hl\r
485 inc c\r
486ioi_r:\r
487 dec c ;otim increments c\r
488 otim\r
489 jr z,ioi_r\r
490ioi_nxt:\r
491 ld b,(hl) ;count\r
492 inc hl\r
493 inc b ;stop if count == 0\r
494 djnz ioi_l\r
495 pop bc\r
496 ret\r
497 \r
498 endif ;(1/0)\r
499\r
fecee241 500 else\r
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501\r
502io.ini:\r
503 push bc\r
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504 jr ioi_nxt\r
505ioi_l:\r
506 ld c,(hl) ;port address\r
507 inc hl\r
508 otir\r
509ioi_nxt:\r
510 ld b,(hl) ;count\r
511 inc hl\r
512 inc b\r
513 djnz ioi_l\r
fecee241 514 endif\r
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515 pop bc\r
516 ret\r
517\r
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518;----------------------------------------------------------------------\r
519\r
fecee241 520 if CPU_Z180\r
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521\r
522 global ioiniml\r
523\r
524ioiniml:\r
a16ba2b0 525 push bc\r
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526 xor a\r
527ioml_lp:\r
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528 ld b,(hl)\r
529 inc hl\r
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530 cp b\r
531 jr z,ioml_e\r
532 \r
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533 ld c,(hl)\r
534 inc hl\r
815c1735 535 otimr\r
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536 jr ioml_lp\r
537ioml_e:\r
815c1735 538 pop bc\r
2fe44122 539 ret z\r
fecee241 540 endif\r
815c1735 541\r
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542io.ini.l:\r
543;\r
544\r
a16ba2b0 545\r
a16ba2b0 546\r
4caee1ec 547;----------------------------------------------------------------------\r
a16ba2b0 548;\r
fecee241 549 if CPU_Z180\r
a16ba2b0 550\r
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551; a: Bank number\r
552;\r
553; out a: bbr value\r
a16ba2b0 554\r
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555bnk2log:\r
556 push bc\r
557 ld b,a\r
558 ld c,CA\r
559 mlt bc\r
560 add a,10h\r
561 pop bc\r
562 ret\r
a16ba2b0 563\r
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564; de: Log. Address\r
565; a: Bank number\r
566;\r
567;out ahl: Phys. (linear) Address\r
568\r
569\r
570bnk2phys:\r
fecee241 571 call bnk2log\r
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572\r
573 ; fall thru\r
574;--------------------------------------------------------------\r
575;\r
576; de: Log. Address\r
fecee241 577; a: Bank base (bbr)\r
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578;\r
579; OP: ahl = (a<<12) + (d<<8) + e\r
580;\r
4caee1ec 581;out ahl: Phys. (linear) Address\r
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582\r
583\r
584log2phys:\r
585 push bc ;\r
586 ld c,a ;\r
587 ld b,16 ;\r
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588 mlt bc ; bc = a<<4\r
589 ld l,d ;4\r
590 ld h,0 ;6\r
591 add hl,bc ;7 bc + d == a<<4 + d\r
592 ld a,h ;4\r
593 ld h,l ;4\r
594 ld l,e ;4\r
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595 pop bc ;\r
596 ret ;\r
597\r
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598 if 0\r
599 \r
600log2phys:\r
601 push bc ;\r
602 ld b,a ;\r
603 ld c,16 ;\r
604 mlt bc ; bc = a<<4\r
605 ld a,c ;4\r
606 add a,h ;4\r
607 ld h,a ;4\r
608 ld a,b ;4\r
609 adc a,0 ;6\r
610 pop bc ;\r
611 ret ;\r
612\r
613 endif\r
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614;--------------------------------------------------------------\r
615;\r
616; de: Log. Address\r
617; \r
618;\r
619; OP: ahl = (bankbase<<12) + (d<<8) + e\r
620;\r
621;out ahl: Phys. (linear) Address\r
622\r
623\r
624hw_log2phys:\r
625 push bc ;\r
626 in0 c,(cbar)\r
627 ld a,d\r
628 or 00fh\r
629 cp c\r
630 jr c,hlp_1\r
631 in0 c,(cbr)\r
632 jr hlp_e\r
633hlp_1:\r
634 ld b,16\r
635 mlt bc\r
636 ld a,d\r
637 cp c\r
638 ld c,0\r
639 jr c,hlp_e\r
640 in0 c,(bbr)\r
641hlp_e: \r
642 ld b,16 ;\r
643 mlt bc ;bc = a<<4\r
644 ld l,d ;\r
645 ld h,0 ;\r
646 add hl,bc ;bc + d == a<<4 + d\r
647 ld a,h ;\r
648 ld h,l ;\r
649 ld l,e ;\r
650 pop bc ;\r
651 ret ;\r
652\r
fecee241 653 else\r
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654\r
655;\r
656;----------------------------------------------------------------------\r
657;\r
658\r
659bnk2phys:\r
660 sla h\r
661 jr nc,b2p_1 ;A15=1 --> common\r
662 ld a,3\r
663b2p_1:\r
664 srl a\r
665 rr h\r
666 ret\r
667\r
fecee241 668 endif\r
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669\r
670;--------------------------------------------------------------\r
671;\r
672;return:\r
673; hl = hl + a\r
674; Flags undefined\r
675;\r
676\r
677add_hl_a:\r
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678 add a,l\r
679 ld l,a\r
680 ret nc\r
681 inc h\r
682 ret\r
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683\r
684; ---------------------------------------------------------\r
685\r
686sysramw:\r
687\r
688 .phase isvsw_loc\r
689topcodsys:\r
690\r
691; Trampoline for interrupt routines in banked ram.\r
692; Switch stack pointer to "system" stack in top ram\r
693; Save cbar\r
815c1735 694\r
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695isv_sw: ;\r
696 ex (sp),hl ; save hl, return adr in hl\r
697 push de ;\r
698 push af ;\r
699 ex de,hl ;\r
700 ld hl,0 ;\r
701 add hl,sp ;\r
702 ld a,h ;\r
703 cp 0f8h ;\r
704 jr nc,isw_1 ;\r
705 ld sp,$stack ;\r
706isw_1:\r
707 push hl ;\r
708 in0 h,(cbar) ;\r
709 push hl ;\r
710 ld a,SYS$CBAR ;\r
711 out0 (cbar),a ;\r
712 ex de,hl ;\r
713 ld e,(hl) ;\r
714 inc hl ;\r
715 ld d,(hl) ;\r
716 ex de,hl ;\r
717 push bc ;\r
718 call jphl ;\r
719\r
720 pop bc ;\r
721 pop hl ;\r
722 out0 (cbar),h ;\r
723 pop hl ;\r
724 ld sp,hl ;\r
725 pop af ;\r
726 pop de ;\r
727 pop hl ;\r
728 ei ;\r
729 ret ;\r
730jphl:\r
731 jp (hl) ;\r
732\r
733; ---------------------------------------------------------\r
734\r
fecee241 735 if CPU_Z180\r
4caee1ec 736\r
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737iprt0:\r
738 push af\r
739 push hl\r
740 in0 a,(tcr)\r
741 in0 a,(tmdr0l)\r
742 in0 a,(tmdr0h)\r
743 ld a,(tim_ms)\r
744 inc a\r
745 cp 100\r
746 jr nz,iprt_1\r
747 xor a\r
748 ld hl,(tim_s)\r
749 inc hl\r
750 ld (tim_s),hl\r
751iprt_1:\r
752 ld (tim_ms),a\r
753 pop hl\r
754 pop af\r
755 ei\r
756 ret\r
757\r
fecee241 758 endif\r
8df5b655 759\r
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760; ---------------------------------------------------------\r
761\r
762sp.int0:\r
763 ld a,0d0h\r
764 jr sp.i.1\r
765sp.int.len equ $-sp.int0\r
766 ld a,0d1h\r
767 jr sp.i.1\r
768 ld a,0d2h\r
769 jr sp.i.1\r
770 ld a,0d3h\r
771 jr sp.i.1\r
772 ld a,0d4h\r
773 jr sp.i.1\r
774 ld a,0d5h\r
775 jr sp.i.1\r
776 ld a,0d6h\r
777 jr sp.i.1\r
778 ld a,0d7h\r
779 jr sp.i.1\r
780 ld a,0d8h\r
781sp.i.1:\r
782; out (80h),a\r
783 halt\r
784\r
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785; ---------------------------------------------------------\r
786\r
fecee241 787 if CPU_Z80\r
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788\r
789; Get IFF2\r
790; This routine may not be loaded in page zero\r
791;\r
792; return Carry clear, if INTs are enabled.\r
793;\r
794 global getiff\r
795getiff:\r
796 xor a ;clear accu and carry\r
797 push af ;stack bottom := 00xxh\r
798 pop af\r
799 ld a,i ;P flag := IFF2\r
800 ret pe ;exit carry clear, if enabled\r
801 dec sp\r
802 dec sp ;has stack bottom been overwritten?\r
803 pop af\r
804 and a ;if not 00xxh, INTs were\r
805 ret nz ;actually enabled\r
806 scf ;Otherwise, they really are disabled\r
807 ret\r
808\r
809;----------------------------------------------------------------------\r
810\r
811 global selbnk\r
812\r
813; a: bank (0..2)\r
814\r
815selbnk:\r
816 push bc\r
817 ld c,a\r
818 call getiff\r
819 push af\r
820\r
821 ld a,c\r
822 di\r
823 ld (@cbnk),a\r
824 ld a,5\r
825 out (SIOAC),a\r
826 ld a,(mm_sio0)\r
827 rla\r
828 srl c\r
829 rra\r
830 out (SIOAC),a\r
831 ld (mm_sio0),a\r
832\r
833 ld a,5\r
834 out (SIOBC),a\r
835 ld a,(mm_sio1)\r
836 rla\r
837 srl c\r
838 rra\r
839 out (SIOBC),a\r
840 ld (mm_sio1),a\r
841 pop af\r
842 pop bc\r
843 ret c ;INTs were disabled\r
844 ei\r
845 ret\r
846\r
847;----------------------------------------------------------------------\r
848\r
849; c: bank (0..2)\r
850\r
fecee241 851 if 0\r
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852\r
853selbnk:\r
854 ld a,(@cbnk)\r
855 xor c\r
856 and 3\r
857 ret z ;no change\r
858\r
859 call getiff\r
860 push af\r
861 ld a,c\r
862 di\r
863 ld (@cbnk),a\r
864 ld a,5\r
865 out (SIOAC),a\r
866 ld a,(mm_sio0)\r
867 rla\r
868 srl c\r
869 rra\r
870 out (SIOAC),a\r
871 ld (mm_sio0),a\r
872\r
873 ld a,5\r
874 out (SIOBC),a\r
875 ld a,(mm_sio1)\r
876 rla\r
877 srl c\r
878 rra\r
879 out (SIOBC),a\r
880 ld (mm_sio1),a\r
881 pop af\r
882 ret nc ;INTs were disabled\r
883 ei\r
884 ret\r
885\r
fecee241 886 endif\r
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887\r
888;----------------------------------------------------------------------\r
889\r
fecee241 890 if 0\r
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891 ex af,af'\r
892 push af\r
893 ex af,af'\r
894\r
895 rra\r
896 jr nc,stbk1\r
897 ex af,af'\r
898 ld a,5\r
899 out (SIOAC),a\r
900 ld a,(mm_sio0)\r
901 rla\r
902 srl c\r
903 rra\r
904 out (SIOAC),a\r
905 ld (mm_sio1),a\r
906 ex af,af'\r
907\r
908stbk1:\r
909 rra\r
910 jr nc,stbk2\r
911 ex af,af'\r
912 ld a,5\r
913 out (SIOBC),a\r
914 ld a,(mm_sio1)\r
915 rla\r
916 srl c\r
917 rra\r
918 out (SIOBC),a\r
919 ld (mm_sio1),a\r
920 ex af,af'\r
921\r
922stbk2:\r
fecee241 923 endif\r
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924\r
925 global @cbnk\r
926 global mm_sio0, mm_sio1\r
927\r
928@cbnk: db 0 ; current bank (0..2)\r
929mm_sio0:\r
930 ds 1\r
931mm_sio1:\r
932 ds 1\r
933\r
934\r
fecee241 935 endif\r
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936\r
937;----------------------------------------------------------------------\r
938\r
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939curph defl $\r
940 .dephase\r
941sysrame:\r
942 .phase curph\r
943tim_ms: db 0\r
944tim_s: dw 0\r
945 .dephase\r
815c1735 946\r
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947;-----------------------------------------------------\r
948\r
8df5b655 949\r
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950 cseg\r
951\r
952 ;.phase 0ffc0h\r
953;ivtab equ 0ffc0h ; 0ffc0h ;int vector table\r
954 ;.dephase\r
955\r
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956 ;.phase 0fffah\r
957mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack\r
958 ;ds 4\r
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959 ;.dephase\r
960\r
961\r
962 end\r
963\r