-SRC := r3init.180 ddtz.180
+SRC := init.180 ddtz.180
SRC += fifoio.180 msgbuf.180 ser1-i.180 console.180
SRC += romend.180
endef
#Use: MAKESYM Filename[.ext][/PXXXX][/DXXXX][/CXXXX]
-#egrep '^[[:xdigit:]]{4}[[:space:]]+[[:xdigit:]]{4}[[:space:]]+D.*r3init\.rel' hdrom.map
+#egrep '^[[:xdigit:]]{4}[[:space:]]+[[:xdigit:]]{4}[[:space:]]+D.*init\.rel' hdrom.map
define cpm-mksym =
COMMAND="$(CPMEMU) makesym -$^ -/P -D"; \
OUTPUT=$$(mktemp); echo $${COMMAND}; \
PROG = hdrom
-SRC = r3init.180
+SRC = init.180
SRC += ddtz.180
#SRC += fifoio.180 msgbuf.180 ser1-i.180 console.180
SRC += msgbuf-a.180 conbuf-a.180 ser1-i.180 bioscio.180 chario.180
+;-----------------------------------------------------\r
+; CPU and BANKING types\r
+\r
\r
+CPU_Z180 equ 1 ; 0 = Z80, else Z180\r
+ROMSYS equ 0\r
\r
-FOSC equ 9216 ;Oscillator frequency [KHz]\r
-PHI equ FOSC*2 ;CPU frequency\r
+AVRCLK equ 18432 ;[KHz]\r
+\r
+ if CPU_Z180\r
+\r
+;-----------------------------------------------------\r
+FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]\r
+PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)\r
\r
;-----------------------------------------------------\r
; Programmable Reload Timer (PRT)\r
CREFSH equ 0 ;Refresh rate register (disable refresh)\r
CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States\r
\r
-\r
-ROMSYS equ 0\r
+ else ; Z80\r
+\r
+PHI equ AVRCLK/5 ;CPU frequency [KHz]\r
+BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]\r
+;BDCLK16 equ\r
+\r
+SIOAD EQU 0bch\r
+SIOAC EQU 0bdh\r
+SIOBD EQU 0beh\r
+SIOBC EQU 0bfh\r
+\r
+CTC0 EQU 0f4h\r
+CTC1 EQU 0f5h\r
+CTC2 EQU 0f6h\r
+CTC3 EQU 0f7h\r
+\r
+;\r
+; Init Serial I/O for console input and output (SIO-A)\r
+;\r
+; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r
+;\r
+; Baudrate Divider SIO CTC\r
+; ---------------------------------\r
+; 115200 16 16 1\r
+; 57600 32 16 2\r
+; 38400 48 16 3\r
+; 19200 96 16 6\r
+; 9600 192 16 12\r
+; 4800 384 16 24\r
+; 2400 768 16 48\r
+; 1200 1536 16 96\r
+; 600 3072 16 192\r
+; 300 6144 64 92\r
+\r
+ endif ; CPU_Z180\r
\r
if ROMSYS\r
c$rom equ 0a5h\r
ROM_EN equ 0C0h\r
ROM_DIS equ ROMEN+1\r
+ if CPU_Z180\r
CWAITROM equ 2 shl MWI0\r
endif\r
+ endif\r
\r
\r
DRSTNUM equ 30h ;DDTZ Restart vector (breakpoints)\r
s1.rx_len equ 256 ;Serial 1 (ASCI1) buffers\r
s1.tx_len equ 256 ;\r
\r
-AVRINT5 equ 40h\r
-AVRINT6 equ 50h\r
+AVRINT5 equ 4Fh\r
+AVRINT6 equ 5Fh\r
;PMSG equ 80h\r
\r
;-----------------------------------------------------\r
.z80\r
\r
extrn ?const,?conin,?cono\r
+ extrn getiff\r
+ extrn selbnk,@cbnk\r
\r
global ddtz,bpent\r
global $stack\r
\r
\r
include config.inc\r
+ if CPU_Z180\r
include z180reg.inc\r
include z180.lib\r
+ endif\r
\r
BS equ 08h\r
TAB equ 09h\r
endif\r
endm\r
\r
-; repeat execution of last common code snippet\r
-comrep macro\r
- call ?exclst\r
- endm\r
\r
\r
\r
ld sp,$stack\r
ld a,(wstrtflg) ;check warm start flag\r
or a\r
- jr nz,ddtz_w\r
+;;; jr nz,ddtz_w\r
\r
exx\r
ld hl,sysramc\r
ld bc,topcodend-topcodbeg\r
ldir\r
\r
- ld hl,vartab\r
- ld de,ddtram\r
- ld bc,vartabe-vartab\r
- ldir\r
exx\r
\r
+ if CPU_Z180\r
ld a,e\r
ld (ubbr),a\r
+ endif\r
\r
ddtz_w:\r
ld hl,MSG ;073c\r
ld (hl),a ;\r
cp ' ' ;\r
jr nc,l0869h ;\r
- ld a,'^' ;Controle characters\r
+ ld a,'^' ;Controll characters\r
call $co ;\r
ld a,(hl) ;\r
add a,'@' ;\r
jr l0b58h ;0b5e\r
\r
do_op_mlt:\r
- push bc ;0b60\r
+ push bc\r
+ if CPU_Z180\r
ld b,h\r
ld c,e\r
ld h,e\r
add a,c\r
add a,e\r
ld h,a\r
- pop bc ;0b72\r
- jr l0b58h ;0b73\r
+ else\r
+ ld b,h\r
+ ld c,l\r
+ ld hl,0\r
+ ld a,16\r
+mlt_1:\r
+ add hl,hl\r
+ ex de,hl\r
+ add hl,hl\r
+ ex de,hl\r
+ jr nc,mlt_2\r
+ add hl,bc\r
+mlt_2:\r
+ dec a\r
+ jr nz,mlt_1\r
+ endif\r
+ pop bc\r
+ jr l0b58h\r
\r
do_op_div:\r
call DIV_HL_DE ;0b75\r
\r
bpddtz:\r
if ROMSYS\r
- ld h,ROMEN ;0fcd\r
- jr z,l0fd2h ;0fcf\r
- inc h ;0fd1\r
+ ld h,ROMEN\r
+ jr z,l0fd2h\r
+ inc h\r
l0fd2h:\r
- push hl ;0fd2 save rom enable stat\r
+ push hl ;save rom enable stat\r
+ endif\r
+ push bc\r
+ push de\r
+ push ix\r
+ push iy\r
+ ld a,i\r
+ ld h,a\r
+ ld l,000h\r
+ push hl ;save I register\r
+\r
+ if CPU_Z180\r
+ ld a,0f3h ;DI\r
+ jp po,l0fe6h\r
+ ld a,0fbh ;EI\r
+ else ;NMOS Z80 design flaw\r
+ call getiff ;return Carry set, if INTs are disabled.\r
+ ld a,0f3h ;DI\r
+ jr c,l0fe6h\r
+ ld a,0fbh ;EI\r
endif\r
- push bc ;0fd3\r
- push de ;0fd4\r
- push ix ;0fd5\r
- push iy ;0fd7\r
- ld a,i ;0fd9\r
- ld h,a ;0fdb\r
- ld l,000h ;0fdc\r
- push hl ;0fde\r
- ld a,0f3h ;0fdf DI\r
- jp po,l0fe6h ;0fe1\r
- ld a,0fbh ;0fe4 EI\r
l0fe6h:\r
- ld (reg.iff),a ;0fe6\r
- ld hl,ivtab ;0fe9\r
- ld a,h ;0fec\r
- ld i,a ;0fed\r
- call ddtei ;0fef\r
- ex af,af' ;0ff2\r
- push af ;0ff3\r
- exx ;0ff4\r
- push bc ;0ff5\r
- push de ;0ff6\r
- push hl ;0ff7\r
- call bp.unset ;0ff8\r
- in0 a,(itc) ;0ffb\r
- jp p,l1017h ;0ffe\r
- res TRAP,a ;1001\r
- out0 (itc),a ;1003\r
- bit UFO,a ;1006\r
- jr z,l1011h ;1008\r
- ld hl,(REG.PC) ;100a\r
- dec hl ;100d\r
- ld (REG.PC),hl ;100e\r
+ ld (reg.iff),a\r
+ ld hl,ivtab\r
+ ld a,h\r
+ ld i,a\r
+ call ddtei\r
+ ex af,af'\r
+ push af\r
+ exx\r
+ push bc\r
+ push de\r
+ push hl\r
+ call bp.unset\r
+ if CPU_Z180\r
+ in0 a,(itc)\r
+ jp p,l1017h\r
+ res TRAP,a\r
+ out0 (itc),a\r
+ bit UFO,a\r
+ jr z,l1011h\r
+ ld hl,(REG.PC)\r
+ dec hl\r
+ ld (REG.PC),hl\r
l1011h:\r
- ld hl,MSG_trap ;1011\r
- call PSTR ;1014\r
+ ld hl,MSG_trap\r
+ call PSTR\r
l1017h:\r
- ld a,(XBFE8) ;1017\r
- dec a ;101a\r
- jr z,l1051h ;101b\r
- call inchar ;101d\r
- jr c,l102eh ;1020\r
- call sub_1059h ;1022\r
- and a ;1025\r
- jp z,l1183h ;1026\r
- and 083h ;1029\r
- jp z,l284ah ;102b\r
+ endif\r
+\r
+ ld a,(XBFE8)\r
+ dec a\r
+ jr z,l1051h\r
+ call inchar\r
+ jr c,l102eh\r
+ call sub_1059h\r
+ and a\r
+ jp z,l1183h\r
+ and 083h\r
+ jp z,l284ah\r
l102eh:\r
- call sub_0e68h ;102e\r
+ call sub_0e68h\r
call prnt_cpustat ;1031\r
- jp DDTZML ;1034\r
+ jp DDTZML\r
\r
+ if CPU_Z180\r
MSG_trap:\r
DB CR,LF,'Undefined opcode trap'\r
DB CR,LF,0\r
+ endif\r
\r
l1051h:\r
ld (XBFE8),a ;1051\r
ld l,(ix+002h) ;114e\r
ld h,(ix+003h) ;1151\r
\r
- if 0\r
-\r
- comst ;1154\r
- ld a,(hl) ;1158\r
- comend\r
- ld (ix+001h),a ;1159\r
- ld a,(ddtrst) ;115c\r
- comst ;115f\r
- ld (hl),a ;1163\r
- comend\r
- and 038h ;1164\r
- ld h,000h ;1166\r
- ld l,a ;1168\r
- ld a,0c3h ;1169\r
- comrep ;116b\r
- inc hl ;116e\r
- ld de,bpent ;116f\r
- ld a,e ;1172\r
- comrep ;1173\r
- inc hl ;1176\r
- ld a,d ;1177\r
- comrep ;1178\r
-\r
- else\r
\r
ld a,(ddtrst) ;115c\r
comst ;115f\r
ld (hl),d ;1177\r
comend\r
\r
- endif\r
\r
l117bh:\r
ld de,BP_SIZE ;117b\r
ret ;1329\r
\r
b_0x132A_start:\r
+ if ROMSYS\r
+ DC 'ROMSEL'\r
+ endif\r
+ if CPU_Z180\r
DC 'CBAR'\r
DC 'BBR'\r
+ else\r
+ DC 'BNK'\r
+ endif\r
DC 'BC'''\r
DC 'DE'''\r
DC 'HL'''\r
DC 'I'\r
DC 'F'''\r
DC 'F'\r
- if ROMSYS\r
- DC 'ROMSEL'\r
- endif\r
DB 0\r
b_0x136C_start:\r
+ if ROMSYS\r
+ defb 000h ;13cf\r
+ defw uromen ;13d0\r
+ endif\r
+ if CPU_Z180\r
defb 000h ;136c\r
defw ucbar ;136d\r
defb 000h ;136f\r
defw ubbr ;1370\r
+ else\r
+ defb 000h ;136f\r
+ defw ubnk ;1370\r
+ endif\r
defb 003h ;1372\r
defw reg.c2 ;1373\r
defb 003h ;1375\r
defw reg.f2 ;13ca\r
defb 000h ;13cc\r
defw reg.f ;13cd\r
- if ROMSYS\r
- defb 000h ;13cf\r
- defw uromen ;13d0\r
- endif\r
CMD.S:\r
ld hl,(lst.S) ;13d2\r
call get_lastarg_def ;13d5\r
ld (lst.IP),hl ;1427\r
ld b,h ;142a\r
ld c,l ;142b\r
+ if CPU_Z180\r
ld a,b ;142c\r
or a ;142d\r
jr nz,l1442h ;142e\r
ld a,(hl) ;143f\r
jr l1444h ;1440\r
l1442h:\r
+ endif\r
in a,(c) ;1442\r
l1444h:\r
push af ;1444\r
ld (lst.OP),hl ;146c\r
ld b,h ;146f\r
ld c,l ;1470\r
+ if CPU_Z180\r
ld a,b ;1471\r
or a ;1472\r
jr nz,l1489h ;1473\r
cp cbr ;1484\r
jp z,ERROR ;1486\r
l1489h:\r
+ endif\r
pop af ;1489\r
out (c),a ;148a\r
ret ;148c\r
+ if CPU_Z180\r
l148dh:\r
pop af ;148d\r
ld (hl),a ;148e\r
ret ;148f\r
+ endif\r
\r
CMD.V:\r
call get_arg3 ;1490 get from, size, to\r
pop bc ;28f8\r
pop af ;28f9\r
ex (sp),hl ;28fa\r
-?exclst:\r
+ if CPU_Z180\r
push hl ;28fb\r
ld hl,(ubbr) ;2900\r
\r
+ else\r
+ push af ;28fb\r
+ ld a,(ubnk) ;2900\r
+ endif\r
if ROMSYS\r
push af ;28fc\r
ld a,(uromen) ;28fd\r
; The following 2 params are changeable by user.\r
; Should these moved to top ram?\r
;\r
-ddtrst: inidat ;\r
- rst DRSTNUM ;rst used by ddtz\r
- inidate ;\r
-ddtei: inidat ;\r
- ei ;ints enabled/disabled while ddtz is running\r
+ddtrst: rst DRSTNUM ;rst used by ddtz\r
+ddtei: ei ;ints enabled/disabled while ddtz is running\r
ret ;\r
- inidate ;\r
offs.pc:\r
- inidat \r
dw TPA \r
- inidate\r
offs.@:\r
- inidat\r
dw 0 \r
- inidate\r
CMD_ERR:\r
- inidat\r
dw 0 \r
- inidate\r
CMD_RPT:\r
- inidat\r
dw DDTZML \r
- inidate\r
ci.buf:\r
- inidat\r
db 80 \r
rept 83\r
db 0\r
endm\r
- inidate\r
CON.COL:\r
- inidat\r
db 0 \r
- inidate\r
XA747:\r
- inidat\r
db 0 \r
- inidate\r
bp_tab:\r
- inidat\r
rept BP_CNT \r
db 0,0\r
dw 0,0,0\r
endm\r
BP_SIZE equ 8\r
- inidate\r
sexp1:\r
- inidat\r
dw sexpbuf \r
- inidate\r
sexp2:\r
- inidat\r
dw sexpbuf \r
- inidate\r
sexpbuf:\r
- inidat\r
rept 128 \r
db 0\r
endm\r
- inidate\r
sexpbufe:\r
\r
msg.Y:\r
- inidat\r
dc 'Y0' \r
- inidate\r
reg.Y:\r
- inidat\r
rept 10 \r
dw 0\r
endm\r
- inidate\r
lst.S:\r
- inidat\r
dw 0 \r
- inidate\r
lst.IP:\r
- inidat\r
dw 0 \r
- inidate\r
lst.OP:\r
- inidat\r
dw 0 \r
- inidate\r
lst.OD:\r
- inidat\r
db 0\r
- inidate\r
lst.Qj:\r
- inidat\r
db 0\r
- inidate\r
lst.D:\r
- inidat\r
dw 0 \r
- inidate\r
HILOD:\r
- inidat\r
dw 0 \r
- inidate\r
MAXLOD:\r
- inidat\r
dw 0 \r
- inidate\r
XB068:\r
- inidat\r
dw 0 \r
- inidate\r
lst.A:\r
- inidat\r
dw 0 \r
- inidate\r
XB06C:\r
- inidat\r
dw 0 \r
- inidate\r
pfx.IXY:\r
- inidat\r
db 000h \r
- inidate\r
is.pfx.IXY:\r
- inidat\r
db 000h \r
- inidate\r
lst.L:\r
- inidat\r
dw 0 \r
- inidate\r
XBE01:\r
- inidat\r
dw 0 \r
- inidate\r
XBE03:\r
- inidat\r
db 000h \r
- inidate\r
XBEDD:\r
- inidat\r
ret ;ret cc\r
and a \r
pop hl \r
inc hl \r
jp (hl) \r
- inidate\r
XBFE8:\r
- inidat\r
db 0 \r
- inidate\r
TCFLG:\r
- inidat\r
db 0 \r
- inidate\r
XBFEA:\r
- inidat\r
db 0 \r
- inidate\r
TCCSTR:\r
- inidat\r
dw 0 \r
- inidate\r
TCNFLG:\r
- inidat\r
db 0 \r
- inidate\r
TRJFLG:\r
- inidat\r
db 0 \r
- inidate\r
wstrtflg:\r
- inidat\r
db 1\r
- inidate\r
\r
cseg\r
vartabe:\r
udcntl: db CWAITIO ; 0fe62h (mem-, io- wait)\r
uromen: db ROM_DIS ; 0fe63h\r
endif\r
+ if CPU_Z180\r
ubbr: db 0 ; 0fe64h\r
ucbar: db USR$CBAR ; 0fe65h\r
+ else\r
+ db 0 ; 0fe64h\r
+ubnk: db 0 ; 0fe65h\r
+ endif\r
reg.f: db 0 ; 0fe66h\r
reg.a: db 0 ; 0fe67h\r
reg.l: db 0 ; 0fe68h\r
if ROMSYS\r
out (000h),a ;064c fe6c\r
out0 (dcntl),l ;064e\r
- pop hl ;0651\r
+ pop hl\r
endif\r
+ if CPU_Z180\r
out0 (cbar),h ;0652\r
out0 (bbr),l ;0655\r
+ else\r
+ ld a,h\r
+ call selbnk\r
+ endif\r
pop af ;0658\r
pop hl ;0659\r
ld sp,(reg.sp) ;065a\r
ld (reg.sp),sp ;066a\r
ld sp,reg.l ;066e\r
push af ;0671\r
+ if CPU_Z180\r
in0 h,(cbar) ;0672\r
in0 l,(bbr) ;0675\r
- push hl ;0678\r
ld a,SYS$CBAR ;0679\r
out0 (cbar),a ;067b\r
+;;; TODO: bbr?\r
+ else\r
+ ld a,(@cbnk)\r
+ ld h,a\r
+ xor a\r
+ ld l,a\r
+ call selbnk\r
+ endif\r
+ push hl ;0678\r
\r
if ROMSYS\r
in0 l,(dcntl) ;067e\r
pop af ;069a\r
endif\r
\r
+ if CPU_Z180\r
out0 (cbar),h ;0694\r
out0 (bbr),l ;0697\r
pop hl ;069b\r
+ else\r
+ call selbnk\r
+ pop af\r
+ endif\r
?exeit:\r
ds ?lcmax+2\r
push af ;069f\r
+ if CPU_Z180\r
ld a,SYS$CBAR ;06a0\r
out0 (cbar),a ;06a2\r
\r
+;;; TODO: bbr?\r
+ else\r
+ xor a\r
+ call selbnk\r
+ endif\r
if ROMSYS\r
ld a,ROM_EN ;06a5\r
out (000h),a ;06a7\r
projects / z180-stamp.git / commitdiff