User Timer0 as Z180 Clock

diff --git a/avr/z80-if.c b/avr/z80-if.c
index 392597e5945e9d5916feaa30259a4e64a1d719b8..20efa9ebcd1ae798137255f2573149ab12c8c920 100644 (file)
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -84,7 +84,9 @@ struct bits {
 #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
 
 
-
+#define P_ZCLK         PORTB
+#define ZCLK           7
+#define DDR_ZCLK       DDRB
 #define P_MREQ         PORTD
 #define MREQ           4
 #define DDR_MREQ       DDRD
@@ -128,6 +130,7 @@ struct bits {
 //#define ADB_PORT     PORTE
 
 
+#define Z80_O_ZCLK     SBIT(P_ZCLK, 7)
 #define        Z80_O_MREQ      SBIT(P_MREQ, 4)
 #define Z80_O_RD       SBIT(P_RD, 3)
 #define Z80_O_WR       SBIT(P_WR, 2)
@@ -171,7 +174,7 @@ static void z80_setup_addrbus_tristate(void)
        DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
 }
 
-       
+
 static void z80_setup_addrbus_active(void)
 {
        /* /MREQ, /RD, /WR: Output and high */
@@ -206,9 +209,24 @@ static void z80_reset_pulse(void)
        Z80_O_RST = 1;
 }
 
+static
+void z80_setup_clock(void)
+{
+       /* ZCLK: Output and low */
+       DDR_ZCLK |= _BV(ZCLK);
+       Z80_O_ZCLK = 0;
+
+       /* Timer0: CTC: Toggle OC0A on compare match */
+       PRR0 &= ~_BV(PRTIM0);
+       TCCR0A = _BV(COM0A0) | _BV(WGM01);
+       OCR0A =  0;
+       TCCR0B = (0x01 << CS00);
+}
 
 void z80_setup_bus(void)
 {
+       z80_setup_clock();
+
        /* /ZRESET: Output and low */
        Z80_O_RST = 0;
        DDR_RST |= _BV(RST);
@@ -387,7 +405,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 
 /*--------------------------------------------------------------------------*/
 
-static 
+static
 //inline __attribute__ ((always_inline))
 void z80_setaddress(uint32_t addr)
 {
@@ -447,7 +465,7 @@ void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
 void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
 {
        uint8_t data;
-       
+
        z80_setup_dbus_out();
        Z80_O_MREQ = 0;
        while(length--) {
@@ -468,7 +486,7 @@ void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
   017B'                         rx.out_idx:    ds      1               ;
   017C'                         rx.buf:                ds      rx.buf_len      ;
   018B'                         rx.buf_end     equ     $-1             ; last byte (start+len-1)
-                                
+
   018C'                         tx.bs_mask:    ds      1               ; (buf_len - 1)
   018D'                         tx.in_idx:     ds      1               ;
   018E'                         tx.out_idx:    ds      1               ;
@@ -497,7 +515,7 @@ static struct {
                idx_in,
                mask;
        } fifo_dsc[NUM_FIFOS];
-       
+
 
 void z80_memfifo_init(const fifo_t f, uint32_t adr)
 {
@@ -537,7 +555,7 @@ int z80_memfifo_is_empty(const fifo_t f)
 int z80_memfifo_is_full(const fifo_t f)
 {
        int rc = 1;
-       
+
        if (fifo_dsc[f].base != 0) {
                z80_bus_cmd(Request);
                rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
@@ -550,7 +568,7 @@ int z80_memfifo_is_full(const fifo_t f)
 uint8_t z80_memfifo_getc(const fifo_t f)
 {
        uint8_t rc, idx;
-       
+
        while (z80_memfifo_is_empty(f))
                ;
 
@@ -560,7 +578,7 @@ uint8_t z80_memfifo_getc(const fifo_t f)
        fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
        z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
        z80_bus_cmd(Release);
-       
+
        return rc;
 }
 
@@ -568,7 +586,7 @@ uint8_t z80_memfifo_getc(const fifo_t f)
 void z80_memfifo_putc(fifo_t f, uint8_t val)
 {
        int idx;
-       
+
        while (z80_memfifo_is_full(f))
                ;
 
@@ -653,7 +671,7 @@ DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
 int z80_msg_fifo_getc(void)
 {
        int c = -1;
-       
+
 #if 0
        if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
                c = msg_fifo.buf[msg_fifo.count];