Enable X2 Clock Multiplier, disable Clock Divider

diff --git a/z180/config.inc b/z180/config.inc
index b03761c444ec71574cb6967ece9cb5011d764373..b5df1cc28eca8af6f8bd9af711794bb43ee3fe60 100644 (file)
--- a/z180/config.inc
+++ b/z180/config.inc
@@ -1,7 +1,7 @@
 \r
 \r
-FOSC           equ     18432           ;Oscillator frequency [KHz]\r
-PHI            equ     FOSC/2          ;CPU frequency \r
+FOSC           equ     9216            ;Oscillator frequency [KHz]\r
+PHI            equ     FOSC*2          ;CPU frequency\r
 \r
 ;-----------------------------------------------------\r
 ; Programmable Reload Timer (PRT)\r
@@ -54,7 +54,7 @@ s1.tx_len     equ     256             ;
 PMSG           equ     80h\r
 \r
 ;-----------------------------------------------------\r
-; Definition of (locical) top 2 memory pages \r
+; Definition of (locical) top 2 memory pages\r
 \r
 sysram_start   equ     0FE00h\r
 stacksize      equ     80\r
@@ -72,7 +72,7 @@ iv2tab                equ     ivtab + 2*9
 o.mask         equ     -3\r
 o.in_idx       equ     -2\r
 o.out_idx      equ     -1\r
-       \r
+\r
        .lall\r
 \r
 mkbuf  macro   name,size\r
@@ -80,7 +80,7 @@ mkbuf macro   name,size
     .printx Error: buffer ^size must be power of 2 and in range 0..256!\r
     name&.mask equ ;wrong size error\r
   else\r
-    ds 3       \r
+    ds 3\r
     name:: ds size\r
     name&.mask equ low (size-1)\r
     if size ne 0\r
@@ -92,9 +92,9 @@ endm
 \r
 ;-----------------------------------------------------\r
 \r
-inidat macro   \r
+inidat macro\r
        cseg\r
-??ps.a defl    $       \r
+??ps.a defl    $\r
        endm\r
 \r
 inidate        macro\r

diff --git a/z180/r3init.180 b/z180/r3init.180
index 7ba9a0c02de7112580adf403b35fc0689a2a07e6..8156ed75f9ed74b71644a0150ae7481574e59a7d 100644 (file)
--- a/z180/r3init.180
+++ b/z180/r3init.180
@@ -13,7 +13,7 @@
        include config.inc\r
        include z180reg.inc\r
        include z180.lib\r
-       \r
+\r
 ;CR    equ     0dh\r
 \r
 \r
@@ -22,7 +22,7 @@
 \r
        cseg\r
 \r
-       jp start                \r
+       jp start\r
 \r
 ; restart vectors\r
 \r
@@ -44,7 +44,7 @@ $crom:         defb c$rom             ;
 dmclrt:                                ;clear ram per dma\r
        db      dmct_e-dmclrt-2 ;\r
        db      sar0l           ;first port\r
-       dw      nullbyte        ;src (fixed) \r
+       dw      nullbyte        ;src (fixed)\r
 nullbyte:\r
        db      000h            ;src\r
        dw      romend          ;dst (inc), start after "rom" code\r
@@ -73,9 +73,9 @@ start:
        jp bpent                ;0044     yes, handle\r
 \r
 ??st01:\r
-       ld a,i                  ;0047   I register == 0 ? \r
+       ld a,i                  ;0047   I register == 0 ?\r
        jr z,??st02             ;004b     yes, harware reset\r
-       pop af                  ;004d   \r
+       pop af                  ;004d\r
        jp bpent                ;004e     no, allready set up\r
 \r
 ??st02:\r
@@ -85,6 +85,11 @@ start:
        ld      a,CWAITIO\r
        out0    (dcntl),a       ;       wait states\r
 \r
+       ld      a,M_NCD         ;No Clock Divide\r
+       out0    (ccr),a\r
+       ld      a,M_X2CM        ;X2 Clock Multiplier\r
+       out0    (cmr),a\r
+\r
 ; search warm start mark\r
 \r
        ld ix,mark_55AA         ;00b8   ; top of common area\r
@@ -93,7 +98,7 @@ start:
        ld a,071h               ;00bc\r
        ex af,af'               ;00be   ;for cbr = 0x70 downto 0x40\r
 swsm_l:\r
-       ex af,af'               ;00bf   \r
+       ex af,af'               ;00bf\r
        dec a                   ;00c0\r
        cp 03fh                 ;00c1\r
        jr z,kstart             ;00c3   ;  break (mark not found)\r
@@ -125,9 +130,9 @@ kstart:
 ??f_0:\r
        out0    (cbr),a         ;00f9\r
 \r
-       ld      (ix+0),a        ;0103   \r
+       ld      (ix+0),a        ;0103\r
        cpl\r
-       ld      (ix+1),a        ;0103   \r
+       ld      (ix+1),a        ;0103\r
        cpl\r
        add     a,8             ;010a   next 'bank'\r
        cp      078h            ;010c   stop at 078000\r
@@ -153,7 +158,7 @@ kstart:
        add     a,8\r
        cp      078h            ;       stop at 078000\r
        jr      nz,??cp_0\r
-       \r
+\r
 ;\r
 ;  ram test found 1 or more error free blocks (32k)\r
 ;\r
@@ -178,7 +183,7 @@ ramok:
 alloc:\r
        out0    (cbr),c         ;01de\r
        ld      sp,$stack       ;01e1\r
-       \r
+\r
 ; Clear RAM using DMA0\r
 \r
        ld      hl,dmclrt       ;load DMA registers\r
@@ -187,13 +192,13 @@ alloc:
        out0    (dmode),a       ;01f1\r
 \r
        ld      b,512/64\r
-       ld      a,062h          ;01f4   enable dma0, \r
+       ld      a,062h          ;01f4   enable dma0,\r
 ??cl_1:\r
        out0    (dstat),a       ;01f9   clear (up to) 64k\r
        djnz    ??cl_1          ;       end of RAM?\r
-       \r
+\r
 ; Init bank manager\r
-       \r
+\r
        ld      hl,banktabsys   ;020f\r
        ld      (hl),c          ;       Common area\r
        inc     hl              ;0213\r
@@ -211,7 +216,7 @@ l0218h:
        ld      (hl),0e0h       ;       mark as sys ("rom"/monitor)\r
        inc     hl\r
        djnz    ??a_0\r
-       \r
+\r
        rr      d               ;       shift out bit for block 0\r
        rr      e               ;\r
        ld      c,15            ;022c   15*32k remaining blocks\r
@@ -220,14 +225,14 @@ l022eh:
        rr      d               ;\r
        rr      e\r
        adc     a,0             ;       ==> 0xff : block ok\r
-       ld      b,32/4          ;       32k == 8 * 4k   \r
+       ld      b,32/4          ;       32k == 8 * 4k\r
 l0236h:\r
        ld      (hl),a          ;\r
        inc     hl              ;\r
        djnz    l0236h          ;\r
        dec     c               ;\r
        jr      nz,l022eh       ;next 32k block\r
-       \r
+\r
        ld      hl,memalv+0ch   ;memalv+0ch\r
        ld      a,(banktabsys)  ;\r
        call    add_hl_a\r
@@ -239,7 +244,7 @@ l024ah:
        ld      (hl),0efh       ;alloc common\r
        call    gencrc_alv\r
 \r
-       ld      hl,0000h        ;bank # \r
+       ld      hl,0000h        ;bank #\r
        ld      bc,0f0fh        ;  size (?) (4k blocks)\r
        xor     a               ;\r
        call    sub_0420h       ;alloc mem for bank 0\r
@@ -284,11 +289,11 @@ wstart:
        call $cists             ;0287\r
        or a                    ;028a\r
        call nz,$ci             ;028d\r
-       \r
-       ld a,(banktab)          ;       \r
-       ld e,a                  ;       \r
+\r
+       ld a,(banktab)          ;\r
+       ld e,a                  ;\r
        jp ddtz                 ;0290\r
-       \r
+\r
 \r
 ;\r
 ;----------------------------------------------------------------------\r
@@ -297,7 +302,7 @@ wstart:
 ;TODO: Make a ringbuffer module.\r
 \r
        global  buf.init\r
-       \r
+\r
 buf.init:\r
        ld      (ix+o.in_idx),0\r
        ld      (ix+o.out_idx),0\r
@@ -314,7 +319,7 @@ buf.init:
 \r
 bufferinit:\r
        call     msginit\r
-       \r
+\r
        ld      hl,buffers\r
        ld      bc,0300h\r
 bfi_1:\r
@@ -339,13 +344,13 @@ bfi_1:
        rept    20\r
        db      0\r
        endm\r
-       \r
+\r
 buffers:\r
        dw      msg_fifo\r
        dw      tx.buf\r
        dw      rx.buf\r
-       \r
-inimsg:        \r
+\r
+inimsg:\r
        db      inimsg_e - $ -2\r
        db      PMSG\r
        db      81h\r
@@ -384,7 +389,7 @@ ivtab_init:
        ld      d,high sp.int0\r
        ld      a,low  sp.int0\r
        ld      b,9\r
-ivt_i1:        \r
+ivt_i1:\r
        ld      (hl),a\r
        inc     l\r
        ld      (hl),d\r
@@ -408,7 +413,7 @@ prt0_init:
        ld      hl,prt0itab\r
        call    io.ini.m\r
        ret\r
-       \r
+\r
 prt0itab:\r
        db      prt0it_e-prt0itab-2\r
        db      tmdr0l\r
@@ -443,10 +448,10 @@ io.ini.m:
        inc     hl\r
        ld      c,(hl)\r
        inc     hl\r
-       otimr   \r
-       pop     bc      \r
+       otimr\r
+       pop     bc\r
        ret\r
-       \r
+\r
 io.ini.l:\r
 ;\r
 \r
@@ -536,7 +541,7 @@ checkcrc_alv:
 ;\r
 ;    ret:\r
 ;      a:      0  == ok\r
-;              1  == \r
+;              1  ==\r
 ;              2  == no bank # in requested range\r
 ;              ff == crc error\r
 ;\r
@@ -544,7 +549,7 @@ checkcrc_alv:
 sub_0420h:\r
        call checkcrc_alv       ;0420\r
        jr nz,l049ch            ;0424   crc error, tables corrupt\r
-       \r
+\r
        call sub_049dh          ;0427   bank # in req. range available?\r
        jr c,l0499h             ;042a\r
        push ix                 ;042c\r
@@ -569,7 +574,7 @@ l0441h:
        djnz l043dh             ;0442\r
        jr l0464h               ;0444\r
 l0446h:\r
-       push hl                 ;0446   \r
+       push hl                 ;0446\r
        pop ix                  ;0447   free blocks start here\r
        ld e,000h               ;0449\r
        jr l0451h               ;044b\r
@@ -583,12 +588,12 @@ l0451h:
        djnz l044dh             ;0453\r
        jr l0464h               ;0455\r
 \r
-; end of free blocks run. \r
+; end of free blocks run.\r
 \r
 l0457h:\r
        ld a,d                  ;0457\r
        cp e                    ;0458   nr of blocks >= requested ?\r
-       jr nc,l0441h            ;0459   \r
+       jr nc,l0441h            ;0459\r
 \r
        ld d,e                  ;045b\r
        push ix                 ;045c\r
@@ -660,7 +665,7 @@ l04a1h:
        inc e                   ;04a1   test next #\r
        ld a,d                  ;04a2\r
        cp e                    ;04a3\r
-       jr c,l04b1h             ;04a4   \r
+       jr c,l04b1h             ;04a4\r
        ld a,e                  ;04a6\r
        ld hl,memalv            ;04a7\r
        ld bc,alv_len           ;04aa\r
@@ -721,7 +726,7 @@ log2phys:
        mlt     bc              ;bc = a<<4\r
        ld      l,d             ;\r
        ld      h,0             ;\r
-       add     hl,bc           ;bc + d == a<<4 + d \r
+       add     hl,bc           ;bc + d == a<<4 + d\r
        ld      a,h             ;\r
        ld      h,l             ;\r
        ld      l,e             ;\r
@@ -737,11 +742,11 @@ log2phys:
 ;\r
 \r
 add_hl_a:\r
-       add a,l \r
-       ld l,a  \r
-       ret nc  \r
-       inc h   \r
-       ret     \r
+       add a,l\r
+       ld l,a\r
+       ret nc\r
+       inc h\r
+       ret\r
 \r
 ; ---------------------------------------------------------\r
 \r
@@ -753,7 +758,7 @@ topcodsys:
 ; Trampoline for interrupt routines in banked ram.\r
 ; Switch stack pointer to "system" stack in top ram\r
 ; Save cbar\r
-       \r
+\r
 isv_sw:                                ;\r
        ex (sp),hl              ;       save hl, return adr in hl\r
        push de                 ;\r
@@ -848,7 +853,7 @@ sysrame:
 tim_ms:        db      0\r
 tim_s: dw      0\r
        .dephase\r
-       \r
+\r
 ;-----------------------------------------------------\r
 \r
        dseg\r
@@ -864,7 +869,7 @@ memalv:
 alv_len        equ     $-memalv\r
 crc_len        equ     $-banktabsys\r
 \r
-crc_memalv:    \r
+crc_memalv:\r
        ds      2       ;\r
 \r
        cseg\r

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 616138c045937f40778b55593abb915447eb4ccc..5bbd088d68277901ccb0230569bb4096692b310c 100644 (file)
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -51,10 +51,10 @@ stat1       equ     IOBASE+05h      ;ASCI Status Channel 1
        b2m TDRE,1              ;Transmit Data Register Empty\r
        b2m TIE,0               ;Transmit Interrupt Enable\r
 \r
-tdr0   equ     IOBASE+06h      ;ASCI Transmit Data \r
-tdr1   equ     IOBASE+07h      ;ASCI Transmit Data \r
-rdr0   equ     IOBASE+08h      ;ASCI Receive Data \r
-rdr1   equ     IOBASE+09h      ;ASCI Receive Data \r
+tdr0   equ     IOBASE+06h      ;ASCI Transmit Data\r
+tdr1   equ     IOBASE+07h      ;ASCI Transmit Data\r
+rdr0   equ     IOBASE+08h      ;ASCI Receive Data\r
+rdr1   equ     IOBASE+09h      ;ASCI Receive Data\r
 \r
 cntr   equ     IOBASE+0Ah      ;CSI/O Control Register\r
 trdr   equ     IOBASE+0Bh      ;CSI/O Transmit/Receive Data Register\r
@@ -94,6 +94,7 @@ cmr   equ     IOBASE+1Eh      ;Clock Mutiplier Register
        b2m LNC,6               ;Low Noise Crystal\r
 \r
 ccr    equ     IOBASE+1Fh      ;CPU Control Register\r
+       b2m NCD 7               ;No Clock Divide\r
 \r
 sar0l  equ     IOBASE+20h      ;DMA Src Adr Register Channel 0\r
 sar0h  equ     IOBASE+21h      ;\r