Simplify Console I/O. Switch back to IOBYTE.

diff --git a/z180/Makefile b/z180/Makefile
index 11f9093836d7b72199b0a80f62485d69788f60c5..c6727b9ba9187420eb51428d866863da4e56b207 100644 (file)
--- a/z180/Makefile
+++ b/z180/Makefile
@@ -1,7 +1,9 @@
 
 
 SRC :=  init.180 ddtz.180
-SRC += fifoio.180 msgbuf.180 asci1-i.180 console.180
+SRC += console.180
+SRC += msgbuf-a.180 conbuf-a.180
+SRC += asci1-p.180
 SRC += romend.180
 
 INC := config.inc z180reg.inc z180.lib

diff --git a/z180/Tupfile b/z180/Tupfile
index 23855f8bc086b12c6e7eebd076facd376514f30f..50ede98bcb6289c9eed642a4d17e1aef1aa54db3 100644 (file)
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,10 +4,10 @@ PROG  = hdrom
 
 SRC    = init.180
 SRC    += ddtz.180
-#SRC   += fifoio.180 msgbuf.180 asci-p.180 console.180
-SRC    += msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
-# serial (asci1) console only:
-#SRC   += asci1-i.180 console.180
+SRC    += msgbuf-a.180 conbuf-a.180
+#SRC   += bioscio.180 chario.180
+SRC    += console.180
+SRC    += asci-p.180
 SRC    += romend.180
 
 

diff --git a/z180/conbuf-a.180 b/z180/conbuf-a.180
index 8534f7300441c0af2d99e4cac4bac3447c31d9cf..096bbf932125430a9946b096ddb8e3e34cae3ddc 100644 (file)
--- a/z180/conbuf-a.180
+++ b/z180/conbuf-a.180
@@ -9,7 +9,9 @@
        extrn   buf.init\r
 \r
        include config.inc\r
+       if CPU_Z180\r
        include z180reg.inc\r
+       endif\r
 \r
 \r
 ;--------------------------------------------------------------\r
@@ -96,36 +98,69 @@ buf.full:
        ret\r
 \r
 \r
+       if 1\r
 ff.out:\r
-       push    ix\r
-       ld      ix,co.fifo              ;\r
+       push    ix                      ;15\r
+       ld      ix,co.fifo              ;14\r
 \r
 buf.put:\r
-       push    hl                      ;\r
-       push    bc\r
-       push    ix\r
-       pop     hl\r
-       ld      a,c\r
-       ld      c,(ix+o.in_idx)         ;\r
-       ld      b,0\r
-       add     hl,bc\r
-       ld      b,a\r
-\r
-       ld      a,c                     ;\r
-       inc     a\r
-       and     (ix+o.mask)\r
+       push    hl                      ;11\r
+       push    bc                      ;11\r
+       push    ix                      ;15\r
+       pop     hl                      ;10\r
+       ld      a,c                     ;4\r
+       ld      c,(ix+o.in_idx)         ;19\r
+       ld      b,0                     ;7\r
+       add     hl,bc                   ;11\r
+       ld      (hl),a                  ;7\r
+       ld      b,a                     ;4\r
+\r
+       ld      a,c                     ;4\r
+       inc     a                       ;4\r
+       and     (ix+o.mask)             ;19\r
 bp.wait:\r
-       cp      (ix+o.out_idx)          ;\r
-       jr      z,bp.wait\r
-       ld      (hl),b\r
-       ld      (ix+o.in_idx),a\r
+       cp      (ix+o.out_idx)          ;19\r
+       jr      z,bp.wait               ;12/7\r
+       ld      (ix+o.in_idx),a         ;19\r
        \r
-       out     (AVRINT6),a\r
-       ld      a,b\r
-       pop     bc\r
-       pop     hl\r
-       pop     ix\r
-       ret\r
+       out     (AVRINT6),a             ;11\r
+       ld      a,b                     ;4\r
+       pop     bc                      ;10\r
+       pop     hl                      ;10\r
+       pop     ix                      ;14\r
+       ret                             ;10\r
+\r
+       else\r
+\r
+ff.out:\r
+       push    ix                      ;15\r
+       ld      ix,co.fifo              ;14\r
+\r
+buf.put:\r
+       push    hl                      ;11\r
+       push    ix                      ;15\r
+       pop     hl                      ;10\r
+       ld      a,(ix+o.in_idx)         ;19\r
+       add     a,l                     ;4\r
+       ld      l,a                     ;4\r
+       jr      nc,bp.1                 ;12/7\r
+       inc     l                       ;4\r
+       ld      (hl),c                  ;7\r
+       ld      a,(ix+o.in_idx)         ;19\r
+       inc     a                       ;4\r
+       and     (ix+o.mask)             ;19\r
+bp.wait:\r
+       cp      (ix+o.out_idx)          ;19\r
+       jr      z,bp.wait               ;12/7\r
+       ld      (ix+o.in_idx),a         ;19\r
+\r
+       out     (AVRINT6),a             ;11\r
+       ld      a,c                     ;4\r
+       pop     hl                      ;10\r
+       pop     ix                      ;14\r
+       ret                             ;10             |\r
+\r
+       endif\r
 \r
        end\r
 \r

diff --git a/z180/console.180 b/z180/console.180
index d4f41305e37c5488e16079977fc14142af903bfb..1241d5a05d901a20f71c7406e26d0b14575785bc 100644 (file)
--- a/z180/console.180
+++ b/z180/console.180
@@ -2,47 +2,136 @@
        .z80\r
        \r
 \r
-       global  $coninit\r
-       global  $cists,$ci\r
-       global  $co\r
+; iobyte:\r
+;              0 = console on AVR-System\r
+;              1 = console on SIO/ASCI\r
 \r
 \r
-       extrn   ser.init,ser.ist,ser.in,ser.ost,ser.out\r
+       extrn   iobyte\r
        extrn   ff.init,ff.i.st,ff.in\r
        extrn   ff.o.st,ff.out\r
+    if CPU_Z180\r
+       extrn   as0init,as0ista,as0inp,as0osta,as0out\r
+       extrn   as1init,as1ista,as1inp,as1osta,as1out\r
+    else\r
+       extrn   ser.init,ser.ist,ser.in,ser.ost,ser.out\r
+    endif\r
        \r
+       public  charini\r
+       public  ?const,?conin\r
+       public  ?conos,?cono\r
 \r
        include config.inc\r
+    if CPU_Z180\r
        include z180reg.inc\r
+    endif\r
 \r
        cseg\r
-;\r
-;\r
 \r
-$coninit:\r
+    if CPU_Z180\r
+charini:\r
+       call    ff.init\r
+       call    as0init\r
+       jp      as1init\r
+\r
+?const:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.i.st\r
+       dec     a\r
+       jp      z,as0ista\r
+       dec     a\r
+       jp      z,as1ista\r
+       jr      nullstatus\r
+\r
+?conin:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.in\r
+       dec     a\r
+       jp      z,as0inp\r
+       dec     a\r
+       jp      z,as1inp\r
+       jr      nullinput\r
+\r
+?conos:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.o.st\r
+       dec     a\r
+       jp      z,as0osta\r
+       dec     a\r
+       jp      z,as1osta\r
+       jr      rettrue\r
+\r
+?cono:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.out\r
+       dec     a\r
+       jp      z,as0out\r
+       dec     a\r
+       jp      z,as1out\r
+       jr      nulloutput\r
+\r
+    else\r
+\r
+charini:\r
        call    ff.init\r
+       ld      c,0\r
        call    ser.init\r
+       ld      c,1\r
+       jp      ser.init\r
+\r
+?const:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.i.st\r
+       dec     a\r
+       ld      b,a\r
+       jp      ser.ist\r
+\r
+?conin:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.in\r
+       dec     a\r
+       ld      b,a\r
+       jp      ser.in\r
+\r
+?conos:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.o.st\r
+       dec     a\r
+       ld      b,a\r
+       jp      ser.ost\r
+\r
+?cono:\r
+       ld      a,(iobyte)\r
+       and     03h\r
+       jp      z,ff.out\r
+       dec     a\r
+       ld      b,a\r
+       jp      ser.out\r
+    endif\r
+\r
+\r
+nullinput:\r
+       ld      a,1Ah\r
        ret\r
-       \r
-$cists:\r
-       call    ff.i.st\r
-       ret     nz\r
-       call    ser.ist\r
+\r
+nulloutput:\r
+       ld      a,c\r
        ret\r
-       \r
-$ci:\r
-       call    ff.i.st\r
-       jp      nz,ff.in\r
-       call    ser.ist\r
-       jp      nz,ser.in\r
-       jr      $ci\r
-       \r
-;$costs:\r
-;      jp      f.o.st\r
-       \r
-$co:\r
-       call    ff.out\r
-       jp      ser.out\r
-       \r
+\r
+rettrue:\r
+       or      0FFh\r
+       ret\r
+\r
+nullstatus:\r
+       xor     a\r
+       ret\r
+\r
        end\r
 \r

diff --git a/z180/init-80.180 b/z180/init-80.180
new file mode 100644 (file)
index 0000000..8b71993
--- /dev/null
+++ b/z180/init-80.180
@@ -0,0 +1,591 @@
+       page    255\r
+       .z80\r
+\r
+       extrn ddtz,bpent\r
+       extrn $stack\r
+       extrn charini,?const,?conin\r
+       extrn ?cono,?conos\r
+\r
+       extrn romend\r
+\r
+       global  iobyte\r
+       global  isv_sw\r
+\r
+       include config.inc\r
+\r
+\r
+\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       cseg\r
+romstart equ   $\r
+\r
+       org     romstart+0\r
+       jp      start\r
+\r
+iobyte:        db      0\r
+\r
+; restart vectors\r
+\r
+rsti   defl    1\r
+       rept    7\r
+\r
+       org     8*rsti + romstart\r
+        jp bpent\r
+rsti    defl rsti+1\r
+       endm\r
+\r
+;----------------------------------------------------------------------\r
+       \r
+       org     romstart+40h\r
+\r
+       dw      0\r
+       db      0\r
+\r
+       cseg\r
+\r
+       if ROMSYS\r
+$crom:  defb c$rom             ;\r
+       else\r
+        db     0               ;\r
+       endif\r
+\r
+\r
+hwini0:\r
+       db      0               ;count\r
+;      db      rcr,CREFSH      ;configure DRAM refresh\r
+;      db      dcntl,INIWAITS  ;wait states\r
+;      db      cbar,SYS$CBAR\r
+\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       org     romstart+50h\r
+\r
+start:\r
+       jp      cstart\r
+       jp      wstart\r
+       jp      ?const\r
+       jp      ?conin\r
+       jp      ?cono\r
+       jp      ?conos\r
+       jp      charini\r
+\r
+cstart:\r
+       di\r
+\r
+       xor     a\r
+       ld      (@cbnk),a\r
+\r
+; search warm start mark\r
+\r
+       ld ix,mark_55AA         ; top of common area\r
+       ld a,0aah               ;\r
+       cp (ix+000h)            ;\r
+       jr nz,kstart            ;\r
+       cp (ix+002h)            ;\r
+       jr nz,kstart            ;\r
+       cpl                     ;\r
+       cp (ix+001h)            ;\r
+       jr nz,kstart            ;\r
+       cp (ix+003h)            ;\r
+       jr nz,kstart            ;\r
+       ld sp,$stack            ; mark found, check\r
+;      call checkcrc_alv       ;\r
+       jp z,wstart             ; check ok,\r
+\r
+;\r
+; ram not ok, initialize    --  kstart --\r
+\r
+kstart:\r
+       ld      sp,$stack       ;01e1\r
+\r
+; Clear RAM \r
+\r
+; Init bank manager\r
+\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+       ld      hl,055AAh       ;set warm start mark\r
+       ld      (mark_55AA),hl  ;\r
+       ld      (mark_55AA+2),hl;\r
+\r
+;\r
+;       --  wstart  --\r
+;\r
+wstart:\r
+       call    sysram_init     ;027f\r
+       call    ivtab_init\r
+\r
+       call    charini\r
+       call    bufferinit\r
+\r
+       ld      c,0\r
+       call    selbnk\r
+\r
+\r
+       im 2                    ;?030e\r
+       ei                      ;0282\r
+\r
+       call ?const             ;0284\r
+       call ?const             ;0287\r
+       or a                    ;028a\r
+       call nz,?conin          ;028d\r
+\r
+;;;    ld a,(banktab)          ;\r
+;;;    ld e,a                  ;\r
+       jp ddtz                 ;0290\r
+\r
+\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+;TODO: Make a ringbuffer module.\r
+\r
+       global  buf.init\r
+\r
+buf.init:\r
+       ld      (ix+o.in_idx),0\r
+       ld      (ix+o.out_idx),0\r
+       ld      (ix+o.mask),a\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+\r
+       extrn   msginit,msg.sout\r
+       extrn   mtx.fifo,mrx.fifo\r
+       extrn   co.fifo,ci.fifo\r
+\r
+\r
+bufferinit:\r
+       call     msginit\r
+\r
+       ld      hl,buffers\r
+       ld      b,buftablen\r
+bfi_1:\r
+       ld      a,(hl)\r
+       inc     hl\r
+       ld      (bufdat+0),a\r
+       ld      e,(hl)\r
+       inc     hl\r
+       ld      d,(hl)\r
+       inc     hl\r
+       ex      de,hl\r
+\r
+       or      a\r
+       jr      nz,bfi_2\r
+\r
+       ld      a,(@cbnk)\r
+       call    bnk2phys\r
+\r
+       ld      (40h+0),hl\r
+       ld      (40h+2),a\r
+       out     (AVRINT5),a\r
+       jr      bfi_3\r
+bfi_2:\r
+\r
+       ld      a,(@cbnk)\r
+       call    bnk2phys\r
+\r
+       ld      (bufdat+1),hl\r
+       ld      (bufdat+3),a\r
+       ld      hl,inimsg\r
+       call    msg.sout\r
+bfi_3:\r
+       ex      de,hl\r
+       djnz    bfi_1\r
+       ret\r
+\r
+\r
+buffers:\r
+       db      0\r
+       dw      mtx.fifo\r
+       db      1\r
+       dw      mrx.fifo\r
+       db      2\r
+       dw      co.fifo\r
+       db      3\r
+       dw      ci.fifo\r
+buftablen equ  ($ - buffers)/3\r
+\r
+inimsg:\r
+       db      inimsg_e - $ -1\r
+       db      0AEh\r
+       db      inimsg_e - $ -1\r
+       db      0\r
+bufdat:\r
+       db      0\r
+       dw      0\r
+       db      0\r
+inimsg_e:\r
+\r
+\r
+;\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+bnk2phys:\r
+       sla     h\r
+       jr      nc,b2p_1                ;A15=1 --> common\r
+       ld      a,3\r
+b2p_1:\r
+       srl     a\r
+       rr      h\r
+       ret\r
+\r
+;\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+sysram_init:\r
+       ld hl,sysramw\r
+       ld de,topcodsys\r
+       ld bc,sysrame-sysramw\r
+       ldir\r
+\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+ivtab_init:\r
+       ld      hl,ivtab        ;\r
+       ld      a,h             ;\r
+       ld      i,a             ;\r
+;      out0    (il),l          ;\r
+\r
+; Let all vectors point to spurious int routines.\r
+\r
+       ld      d,high sp.int0\r
+       ld      a,low  sp.int0\r
+       ld      b,9\r
+ivt_i1:\r
+       ld      (hl),a\r
+       inc     l\r
+       ld      (hl),d\r
+       inc     l\r
+       add     a,sp.int.len\r
+       djnz    ivt_i1\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+       global io.ini\r
+       \r
+io.ini:\r
+       push    bc\r
+\r
+       if CPU_Z180\r
+\r
+       ld      b,0             ;high byte port adress\r
+       ld      a,(hl)          ;count\r
+       inc     hl\r
+       or      a\r
+       jr      z,ioi_e\r
+ioi_1:\r
+       ld      c,(hl)          ;port address\r
+       inc     hl\r
+       outi\r
+       inc     b               ;outi decrements b\r
+       dec     a\r
+       jr      nz,ioi_1\r
+\r
+       else\r
+       jr      ioi_nxt\r
+ioi_l:\r
+       ld      c,(hl)          ;port address\r
+       inc     hl\r
+       otir\r
+ioi_nxt:\r
+       ld      b,(hl)          ;count\r
+       inc     hl\r
+       inc     b\r
+       djnz    ioi_l\r
+       endif\r
+ioi_e: \r
+       pop     bc\r
+       ret\r
+\r
+       if CPU_Z180\r
+io.ini.m:\r
+       push    bc\r
+       ld      b,(hl)\r
+       inc     hl\r
+       ld      c,(hl)\r
+       inc     hl\r
+       otimr\r
+       pop     bc\r
+       ret\r
+       endif\r
+\r
+io.ini.l:\r
+;\r
+\r
+\r
+;----------------------------------------------------------------------\r
+;\r
+;return:\r
+; hl = hl + a\r
+; Flags undefined\r
+;\r
+\r
+add_hl_a:\r
+       add a,l\r
+       ld l,a\r
+       ret nc\r
+       inc h\r
+       ret\r
+\r
+; ---------------------------------------------------------\r
+\r
+sysramw:\r
+\r
+       .phase isvsw_loc\r
+topcodsys:\r
+\r
+; Trampoline for interrupt routines in banked ram.\r
+; Switch stack pointer to "system" stack in top ram\r
+\r
+; todo: z80 bank switch\r
+\r
+isv_sw:                                ;\r
+       ex (sp),hl              ; save hl, return adr in hl\r
+       push de                 ;\r
+       push af                 ;\r
+       ex de,hl                ;\r
+       ld hl,0                 ;\r
+       add hl,sp               ;\r
+       ld a,h                  ;\r
+       cp 0f8h                 ;\r
+       jr nc,isw_1             ;\r
+       ld sp,$stack            ;\r
+isw_1:\r
+       push hl                 ;\r
+                               ; save current bank\r
+;      in0 h,(cbar)            ;\r
+       push hl                 ;\r
+                               ; switch to system bank\r
+;      ld a,SYS$CBAR           ;\r
+;      out0 (cbar),a           ; \r
+       ex de,hl                ;\r
+       ld e,(hl)               ;\r
+       inc hl                  ;\r
+       ld d,(hl)               ;\r
+       ex de,hl                ;\r
+       push bc                 ;\r
+       call jphl               ;\r
+\r
+       pop bc                  ;\r
+       pop hl                  ; restore bank\r
+;      out0 (cbar),h           ;\r
+       pop hl                  ;\r
+       ld sp,hl                ;\r
+       pop af                  ;\r
+       pop de                  ;\r
+       pop hl                  ;\r
+       ei                      ;\r
+       ret                     ;\r
+jphl:\r
+       jp (hl)                 ;\r
+\r
+; ---------------------------------------------------------\r
+\r
+sp.int0:\r
+       ld      a,0d0h\r
+       jr      sp.i.1\r
+sp.int.len equ $-sp.int0\r
+       ld      a,0d1h\r
+       jr      sp.i.1\r
+       ld      a,0d2h\r
+       jr      sp.i.1\r
+       ld      a,0d3h\r
+       jr      sp.i.1\r
+       ld      a,0d4h\r
+       jr      sp.i.1\r
+       ld      a,0d5h\r
+       jr      sp.i.1\r
+       ld      a,0d6h\r
+       jr      sp.i.1\r
+       ld      a,0d7h\r
+       jr      sp.i.1\r
+       ld      a,0d8h\r
+sp.i.1:\r
+;      out     (80h),a\r
+       halt\r
+\r
+; ---------------------------------------------------------\r
+\r
+; Get IFF2\r
+; This routine may not be loaded in page zero\r
+;\r
+; return Carry clear, if INTs are enabled.\r
+;\r
+       global getiff\r
+getiff:\r
+       xor     a               ;clear accu and carry\r
+       push    af              ;stack bottom := 00xxh\r
+       pop     af\r
+       ld      a,i             ;P flag := IFF2\r
+       ret     pe              ;exit carry clear, if enabled\r
+       dec     sp\r
+       dec     sp              ;has stack bottom been overwritten?\r
+       pop     af\r
+       and     a               ;if not 00xxh, INTs were\r
+       ret     nz              ;actually enabled\r
+       scf                     ;Otherwise, they really are disabled\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       global  selbnk\r
+\r
+; a: bank (0..2)\r
+\r
+selbnk:\r
+       push    bc\r
+       ld      c,a\r
+       call    getiff\r
+       push    af\r
+\r
+       ld      a,c\r
+       di\r
+       ld      (@cbnk),a\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio0),a\r
+\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       pop     af\r
+       pop     bc\r
+       ret     c                       ;INTs were disabled\r
+       ei\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+; c: bank (0..2)\r
+\r
+       if 0\r
+\r
+selbnk:\r
+       ld      a,(@cbnk)\r
+       xor     c\r
+       and     3\r
+       ret     z               ;no change\r
+\r
+       call    getiff\r
+       push    af\r
+       ld      a,c\r
+       di\r
+       ld      (@cbnk),a\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio0),a\r
+\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       pop     af\r
+       ret     nc                      ;INTs were disabled\r
+       ei\r
+       ret\r
+\r
+       endif\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       if 0\r
+       ex      af,af'\r
+       push    af\r
+       ex      af,af'\r
+\r
+       rra\r
+       jr      nc,stbk1\r
+       ex      af,af'\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio1),a\r
+       ex      af,af'\r
+\r
+stbk1:\r
+       rra\r
+       jr      nc,stbk2\r
+       ex      af,af'\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       ex      af,af'\r
+\r
+stbk2:\r
+       endif\r
+\r
+       global  @cbnk\r
+       global  mm_sio0, mm_sio1\r
+\r
+@cbnk: db      0               ; current bank (0..2)\r
+mm_sio0:\r
+       ds      1\r
+mm_sio1:\r
+       ds      1\r
+\r
+;----------------------------------------------------------------------\r
+\r
+curph  defl    $\r
+       .dephase\r
+sysrame:\r
+       .phase curph\r
+tim_ms:        db      0\r
+tim_s: dw      0\r
+       .dephase\r
+\r
+;-----------------------------------------------------\r
+\r
+       cseg\r
+\r
+       ;.phase 0ffc0h\r
+;ivtab equ     0ffc0h          ; 0ffc0h        ;int vector table\r
+       ;.dephase\r
+\r
+       ;.phase 0fffch\r
+mark_55AA equ 0fffch\r
+       ;ds     4               ; 0fffch\r
+       ;.dephase\r
+\r
+\r
+       end\r
+\r

diff --git a/z180/init.180 b/z180/init.180
index 39b03fcdb6a5cf98dbfe7d89f94904862317498f..73a77bb76767314502278b9ae0fe5a777eabcab0 100644 (file)
--- a/z180/init.180
+++ b/z180/init.180
@@ -8,6 +8,7 @@
        extrn romend\r
 \r
 \r
+       global  iobyte\r
        global  isv_sw\r
 \r
        include config.inc\r
@@ -27,7 +28,8 @@ romstart equ  $
        org     romstart+0\r
        jp start\r
 \r
-iobyte:        db      0\r
+iobyte:        db      2\r
+\r
 ; restart vectors\r
 \r
 rsti   defl    1\r

diff --git a/z180/msgbuf-a.180 b/z180/msgbuf-a.180
index 36e08715db1304e3443110a131d61ffd1aa93d03..1bdd826e27d2bee89f24af427e7d4921e04ac4e1 100644 (file)
--- a/z180/msgbuf-a.180
+++ b/z180/msgbuf-a.180
@@ -9,7 +9,9 @@
        extrn   buf.init\r
 \r
        include config.inc\r
+       if CPU_Z180\r
        include z180reg.inc\r
+       endif\r
 \r
 ;--------------------------------------------------------------\r
 \r
@@ -122,7 +124,7 @@ bp.wait:
        ld      (ix+o.in_idx),a\r
        \r
        ld      a,b\r
-       out0    (AVRINT5),a\r
+       out     (AVRINT5),a\r
        pop     bc\r
        pop     hl\r
        pop     ix\r
@@ -165,7 +167,7 @@ ms.wait:
        ld      (hl),a\r
        ld      (ix+o.in_idx),c\r
        djnz    ms.ol\r
-       out0    (AVRINT5),a\r
+       out     (AVRINT5),a\r
        ex      de,hl\r
        pop     de\r
        pop     bc\r