+/*--------------------------------------------------------------------------*/
+
+//volatile uint8_t io_infifo[256];
+
+static struct {
+ uint8_t idx_out,
+ idx_in;
+ uint16_t count;
+ uint8_t buf[256];
+ } io_infifo;
+
+/*--------------------------------------------------------------------------*/
+
+static void tim1_setup(void)
+{
+ RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
+ RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
+
+ TIM1_CR1 = 0;
+
+ TIM1_SMCR = 0
+ /* | TIM_SMCR_ETP */
+ /* | TIM_SMCR_ETF_CK_INT_N_2 */
+ | TIM_SMCR_TS_ETRF
+ | TIM_SMCR_SMS_OFF
+ ;
+
+ TIM1_DIER = TIM_DIER_TDE;
+
+
+ TIM1_CCMR1 = 0
+ | TIM_CCMR1_OC1M_FORCE_LOW
+ | TIM_CCMR1_CC1S_OUT;
+
+ TIM1_SMCR |= TIM_SMCR_SMS_TM;
+}
+
+/*--------------------------------------------------------------------------*/
+
+static void tim1_ch4_setup(void)
+{
+ /* Reset Timer 1 */
+ RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
+ RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
+
+ TIM1_CCMR2 = 0
+ | TIM_CCMR2_CC4S_IN_TI2
+ | TIM_CCMR2_IC4F_OFF
+ | TIM_CCMR2_IC4PSC_OFF;
+
+ TIM1_CCER = 0
+ /* | TIM_CCER_CC4P */
+ | TIM_CCER_CC4E;
+
+ /* Enable DMA for channel 4 */
+ TIM1_DIER = TIM_DIER_CC4DE;
+}
+
+/*--------------------------------------------------------------------------*/
+
+static void dma1_ch4_setup(void)
+{
+ DMA1_CCR4 =
+ DMA_CCR_PL_VERY_HIGH
+ | DMA_CCR_MSIZE_8BIT
+ | DMA_CCR_PSIZE_8BIT
+ | DMA_CCR_MINC
+ | DMA_CCR_CIRC;
+
+ DMA1_CMAR4 = (uint32_t) io_infifo.buf;
+
+#if (DB_SHIFT == 0) || (DB_SHIFT == 8)
+ DMA1_CPAR4 = DB_PORT + IDR + DB_SHIFT/8;
+#else
+ #error "Databus not byte aligned!"
+#endif
+
+ DMA1_CNDTR4 = io_infifo.count = NELEMS(io_infifo.buf);
+
+ DMA1_CCR4 |= DMA_CCR_EN;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void z80_setup_io_infifo(void)
+{
+ gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
+ GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
+
+ tim1_ch4_setup();
+ dma1_ch4_setup();
+}
+
+
+int z80_io_infifo_getc(void)