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Commit | Line | Data |
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9c15f366 L |
1 | ; Configuration, hardware definition, ... |
2 | ; | |
3 | ; Copyright (C) 2010 Sprite_tm | |
2ccaac16 | 4 | ; Copyright (C) 2010,2012,2013 Leo C. |
9c15f366 L |
5 | ; |
6 | ; This file is part of avrcpm. | |
7 | ; | |
8 | ; avrcpm is free software: you can redistribute it and/or modify it | |
9 | ; under the terms of the GNU General Public License as published by | |
10 | ; the Free Software Foundation, either version 3 of the License, or | |
11 | ; (at your option) any later version. | |
12 | ; | |
13 | ; avrcpm is distributed in the hope that it will be useful, | |
14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ; GNU General Public License for more details. | |
17 | ; | |
18 | ; You should have received a copy of the GNU General Public License | |
19 | ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>. | |
20 | ; | |
21 | ; $Id$ | |
9c15f366 L |
22 | |
23 | ||
db81b524 | 24 | #define VMAJOR 3 /* Version number */ |
825ecc9d | 25 | #define VMINOR 2 |
9c15f366 | 26 | |
5c8bb361 L |
27 | ;----------------------------------------------------------------------- |
28 | ; | |
29 | ; Hardware and feature configuration | |
30 | ; | |
9c15f366 | 31 | |
5c8bb361 L |
32 | ; Supported MCUs are: atmega328P atmega168 atmega88 atmega8 |
33 | ; Z80 emulation currently needs atmega328P, so this is the default. | |
2ccaac16 | 34 | ;#define atmega328p |
80e1fa71 | 35 | |
5c8bb361 L |
36 | ; MCU frequency in Hz. |
37 | ;#define F_CPU 20000000 | |
9c15f366 | 38 | |
5c8bb361 L |
39 | ; Set this to 0, if you have a (one) DRAM chip whith 4 Bit data bus. |
40 | ;#define DRAM_8BIT 1 | |
9c15f366 | 41 | |
5c8bb361 L |
42 | ; Baudrate of serial port (console). |
43 | ;#define BAUD 115200 | |
9c15f366 | 44 | |
825ecc9d | 45 | ; I2C_SUPPORT defaults to 1 on 8-bit-ram systems and must be 0 on 4-bit-ram systems. |
5c8bb361 L |
46 | ; Set this do 0, if you don't have I2C peripherals and want to save some flash |
47 | ; or use the I2C pins for other purposes. | |
825ecc9d | 48 | ;#define I2C_SUPPORT |
5c8bb361 L |
49 | |
50 | ; Emulate Z80 cpu if 1, 8080 otherwise. | |
51 | ; | |
52 | ;#define EM_Z80 1 | |
53 | ||
54 | ; Uncomment and set RAMDISKCOUNT to 1-4 if you want to test the experimental and | |
55 | ; unsupported ramdisk feature . Number depends on actual ram size (256kx4 - 4Mx8) | |
56 | ; and bios dpb/dph definitions. | |
57 | ;#define RAMDISKCNT 0 | |
58 | ||
59 | ; Uncomment and set to 0, if you need to save flash (ie. ATmega88). | |
60 | ;#define FAT16_SUPPORT 1 | |
61 | ||
ce520bff L |
62 | ; Uncomment and set to 0, if you don't want to use CP/M partitions. |
63 | ; (Saves some bytes.) | |
64 | ;#define CPMDSK_SUPPORT 1 | |
65 | ||
5c8bb361 L |
66 | ; Uncomment and set to 0, if you need to save flash. |
67 | ;#define MMCBOOTLOADER 1 | |
9c15f366 | 68 | |
2ccaac16 L |
69 | ; Uncomment to disable ADC support |
70 | ;#define ADC_SUPPORT 0 | |
9c15f366 | 71 | |
5c8bb361 L |
72 | ;----------------------------------------------------------------------- |
73 | ;Debugging aids | |
74 | ||
dd7aea8c L |
75 | .equ BOOTWAIT = 1 |
76 | .equ MEMTEST = 1 | |
98979541 L |
77 | .equ MEMFILL = 1 /* Fill DRAM */ |
78 | .equ SRAM_FILL = 1 /* Fill unused SRAM */ | |
e832c81a | 79 | .equ MMC_DEBUG = 0 /* Increase for more debugging */ |
02d57479 | 80 | .equ MMC_DEBUG_RDW = 0 |
2ccaac16 L |
81 | .equ DSKSEL_DEBUG = 0 |
82 | .equ DISK_DEBUG = 0 /* 1 = BOOT/HOME debug, 2 = +R/W debug */ | |
83 | .equ HOSTRW_DEBUG = 0 | |
e832c81a | 84 | .equ FAT16_DEBUG = 0 |
b2017655 | 85 | .equ FAT16_DBG_FAT = 0 |
dd7aea8c L |
86 | .equ HEAP_DEBUG = 0 |
87 | .equ PORT_DEBUG = 0 | |
88 | .equ INS_DEBUG = 0 | |
e832c81a L |
89 | .equ STACK_DBG = 0 |
90 | .equ PRINT_PC = 0 | |
de15c768 | 91 | .equ TIMER_DEBUG = 0 |
9c15f366 | 92 | |
5c8bb361 L |
93 | ;----------------------------------------------------------------------- |
94 | ; Z80/8080 Virtual Ports | |
95 | ||
e8384f88 L |
96 | #define UARTDR 1 /* UART Data Register */ |
97 | #define UARTCSR 3 /* UART Control/Status Register */ | |
98 | #define UARTRXRDY 0x01 /* RxReady Status Bit Mask */ | |
99 | #define UARTTXRDY 0x02 /* TxReady Status Bit Mask */ | |
100 | ||
2ccaac16 L |
101 | #define READ_FUNC 7 |
102 | #define WRITE_FUNC 6 | |
103 | #define BOOT_FUNC 5 | |
104 | #define HOME_FUNC 4 | |
105 | ||
5c8bb361 L |
106 | #define TIMERPORT 0x40 /* Base z80 port address for clock access */ |
107 | #define TIMER_CTL TIMERPORT | |
108 | #define TIMER_MSECS TIMERPORT+1 | |
109 | #define TIMER_SECS TIMER_MSECS+2 | |
110 | #define CLOCKPORT TIMERPORT+7 /* Real time clock BCD (ss,mm,hh,DD,MM,YYYY) */ | |
111 | ||
112 | #define starttimercmd 1 | |
113 | #define quitTimerCmd 2 | |
114 | #define printTimerCmd 15 | |
115 | #define uptimeCmd 16 | |
116 | ||
117 | #define DEBUGPORT 0x4F | |
118 | ||
98979541 L |
119 | #define startTraceCmd 0x01 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */ |
120 | #define stopTraceCmd 0x00 | |
121 | #define PrintStackCmd 0x02 | |
5c8bb361 L |
122 | |
123 | ; Virtual I2C Interface | |
124 | #define I2CSTAT 0x05 | |
125 | #define I2CCTRL 0x05 | |
126 | #define I2CBLEN 0x06 | |
127 | #define I2CADR 0x07 | |
128 | #define I2CADRL 0x07 | |
129 | #define I2CADRH 0x08 | |
130 | ||
825ecc9d | 131 | ; Simple ADC Interface |
2ccaac16 L |
132 | #define ADC80 0x17 /* Read Value from ADC6 Pin, 8 bit */ |
133 | #define ADC81 0x18 /* Read Value from ADC7 Pin, 8 bit */ | |
134 | #define ADCTEMP 0x19 /* Read Value from Temp Sensor, 8 bit */ | |
135 | #define ADCBGL 0x20 /* Read 1.1V Bandgap, 10 bit */ | |
136 | #define ADCBGH 0x21 /* Read 1.1V Bandgap, 10 bit */ | |
137 | ||
825ecc9d | 138 | |
5c8bb361 L |
139 | ; Port-Expander PCF8574 |
140 | #define PORT 0x80 | |
141 | #define PORT0 0x80 | |
142 | #define PORT1 0x81 | |
143 | #define PORT2 0x82 | |
144 | #define PORT3 0x83 | |
145 | #define PORT4 0x84 | |
146 | #define PORT5 0x85 | |
147 | #define PORT6 0x86 | |
148 | #define PORT7 0x87 | |
149 | ||
150 | ;----------------------------------------------------------------------- | |
151 | ; | |
152 | ||
5c8bb361 L |
153 | #define IPLADDR 0x2000 /* Bootloader load address */ |
154 | ||
155 | #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */ | |
156 | #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ | |
157 | /* Most drams need 1/15.6µs. */ | |
158 | #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ | |
159 | #define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */ | |
160 | ||
161 | #define I2C_CLOCK 100000 /* 100kHz */ | |
162 | #define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */ | |
163 | ||
164 | ||
9c15f366 L |
165 | #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */ |
166 | ||
80e1fa71 | 167 | #define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */ |
9c15f366 L |
168 | #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */ |
169 | #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */ | |
98979541 | 170 | #define SRAMFILL_VAL 0x5A /* Fill unused SRAM */ |
9c15f366 | 171 | |
e8384f88 L |
172 | ; define PARTID 0x52 /* Partition table id */ |
173 | /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */ | |
174 | ; Partition Table Structures | |
175 | ||
176 | #define PART_TYPE 4 | |
177 | #define PART_START 8 | |
178 | #define PART_SIZE 12 | |
179 | ||
180 | /* | |
181 | * Partition table id | |
182 | * (see http://www.win.tue.nl/~aeb/partitions/partition_types-1.html) | |
183 | */ | |
184 | #define PARTID1_FAT16 0x0E | |
185 | #define PARTID2_FAT16 0x06 | |
186 | #define PARTID_CPM 0x52 | |
187 | ||
188 | ||
189 | ;----------------------------------------------------------------------- | |
190 | ; | |
5c8bb361 L |
191 | #ifndef DRAM_8BIT |
192 | #define DRAM_8BIT 1 /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/ | |
193 | #endif /* 0 = only one 4 bit wide DRAM chip */ | |
194 | #ifndef F_CPU | |
195 | #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ | |
196 | #endif | |
197 | #ifndef BAUD | |
198 | #define BAUD 115200 /* console baud rate */ | |
199 | #endif | |
825ecc9d L |
200 | #ifndef I2C_SUPPORT |
201 | #define I2C_SUPPORT DRAM_8BIT /* I2C requires 8 bit DRAM */ | |
202 | #endif | |
203 | #if I2C_SUPPORT && !DRAM_8BIT | |
204 | #error "I2C_SUPPORT requires 8 bit DRAM (DRAM_8BIT=1)!" | |
5c8bb361 | 205 | #endif |
825ecc9d | 206 | #ifndef ADC_SUPPORT |
2ccaac16 | 207 | #define ADC_SUPPORT 1 |
5c8bb361 L |
208 | #endif |
209 | ||
210 | #ifndef EM_Z80 | |
211 | #define EM_Z80 1 /* Emulate Z80 if true, else 8080 */ | |
212 | #endif | |
2ccaac16 | 213 | |
ce520bff L |
214 | #ifndef CPMDSK_SUPPORT |
215 | #define CPMDSK_SUPPORT 1 /* Include Support for CP/M partitions */ | |
216 | #endif | |
217 | ||
5c8bb361 | 218 | #ifndef FAT16_SUPPORT |
ce520bff L |
219 | #define FAT16_SUPPORT 1 /* Include Support for a FAT16 partition */ |
220 | #endif /* which may contain CP/M image files. */ | |
2ccaac16 | 221 | |
5c8bb361 L |
222 | #ifndef RAMDISKCNT |
223 | #define RAMDISKCNT 0 /* Number of RAM disks */ | |
224 | #endif | |
225 | #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */ | |
226 | ||
227 | /* MMC/SD Bootloader support. */ | |
228 | #define BOOTLDRSIZE 2048 /* Bytes needed for Bootloader (1024 Words Bootsection Size) */ | |
229 | #define DEVID_S "ACPM" | |
230 | #ifndef MMCBOOTLOADER | |
231 | #define MMCBOOTLOADER 1 | |
232 | #endif | |
233 | #ifndef TESTVERSION | |
234 | #define TESTVERSION 0 | |
235 | #endif | |
236 | ||
9c15f366 L |
237 | ;----------------------------------------------------------------------- |
238 | ; Port declarations | |
239 | ||
240 | #if DRAM_8BIT /* Implies software uart */ | |
241 | ||
242 | ;Port D | |
243 | .equ RAM_D0 = 0 | |
244 | .equ RAM_D1 = 1 | |
245 | .equ RAM_D2 = 2 | |
246 | .equ RAM_D3 = 3 | |
247 | .equ RAM_D4 = 4 | |
248 | .equ RAM_D5 = 5 | |
249 | .equ RAM_D6 = 6 | |
250 | .equ RAM_D7 = 7 | |
251 | .equ RAM_A0 = 0 | |
252 | .equ RAM_A1 = 1 | |
253 | .equ RAM_A2 = 2 | |
254 | .equ RAM_A3 = 3 | |
255 | .equ RAM_A4 = 4 | |
256 | .equ RAM_A5 = 5 | |
257 | .equ RAM_A6 = 6 | |
258 | .equ RAM_A7 = 7 | |
259 | ||
260 | ;Port B | |
261 | .equ MMC_MOSI = 3 | |
262 | .equ MMC_MISO = 4 | |
263 | .equ MMC_SCK = 5 | |
264 | .equ RAM_A8 = 3 | |
265 | .equ RAM_A9 = 4 | |
266 | .equ RAM_A10 = 5 | |
267 | ||
268 | .equ RXD = 0 | |
269 | .equ TXD = 1 | |
270 | .equ MMC_CS = 2 | |
271 | ||
272 | .equ P_MMC_CS = PORTB | |
273 | .equ P_A8 = PORTB | |
274 | .equ P_RXD = PORTB | |
79986122 | 275 | .equ P_TXD = PORTB |
9c15f366 L |
276 | |
277 | ;Port C | |
278 | .equ RAM_RAS = 0 | |
279 | .equ RAM_CAS = 1 | |
280 | .equ RAM_OE = 2 | |
281 | .equ RAM_W = 3 | |
282 | ||
283 | .equ P_RAS = PORTC | |
284 | .equ P_CAS = PORTC | |
285 | .equ P_OE = PORTC | |
286 | .equ P_W = PORTC | |
287 | ||
288 | ||
289 | #else /* 4 bit RAM, hardware uart */ | |
290 | ||
291 | ; Port D | |
292 | .equ RXD = 0 | |
293 | .equ TXD = 1 | |
294 | .equ RAM_OE = 2 | |
295 | .equ RAM_A8 = 3 | |
296 | .equ MMC_CS = 4 | |
297 | .equ RAM_A5 = 5 | |
298 | .equ RAM_A6 = 6 | |
299 | .equ RAM_A7 = 7 | |
300 | ||
301 | .equ P_RXD = PORTD | |
302 | .equ P_OE = PORTD | |
303 | .equ P_A8 = PORTD | |
304 | .equ P_MMC_CS = PORTD | |
305 | .equ P_AH = PORTD | |
306 | ; RAM_A[7..5] | |
307 | .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5) | |
308 | .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK | |
309 | ||
310 | ||
311 | ;Port B | |
312 | .equ RAM_A4 = 0 | |
313 | .equ RAM_A3 = 1 | |
314 | .equ RAM_A2 = 2 | |
315 | .equ RAM_A1 = 3 | |
316 | .equ MMC_MOSI = 3 | |
317 | .equ RAM_A0 = 4 | |
318 | .equ MMC_MISO = 4 | |
319 | .equ RAM_RAS = 5 | |
320 | .equ MMC_SCK = 5 | |
321 | ||
322 | .equ P_RAS = PORTB | |
323 | .equ P_AL = PORTB | |
324 | ; RAM_A[4..0] | |
325 | .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0) | |
326 | .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK | |
327 | ||
328 | ;Port C | |
329 | .equ RAM_D0 = 0 | |
330 | .equ RAM_D1 = 1 | |
331 | .equ RAM_D2 = 2 | |
332 | .equ RAM_D3 = 3 | |
333 | .equ RAM_W = 4 | |
334 | .equ RAM_CAS = 5 | |
335 | ||
336 | .equ P_DQ = PORTC | |
337 | .equ P_W = PORTC | |
338 | .equ P_CAS = PORTC | |
339 | ||
340 | .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0) | |
341 | .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W) | |
342 | ||
343 | #endif /* DRAM_8BIT */ | |
344 | ||
345 | ||
346 | ;----------------------------------------------------------------------- | |
347 | ;Register definitions | |
348 | ||
349 | .def _tmp0 = r0 | |
350 | .def _tmp1 = r1 | |
351 | ||
352 | .def _RAS0 = r2 | |
353 | .def _CAS0 = r3 | |
354 | .def _OE = r4 | |
355 | .def _WE = r5 | |
356 | .def _255 = r6 | |
357 | .def _0 = r7 | |
825ecc9d L |
358 | |
359 | .def z_c = r8 ; | |
360 | .def z_b = r9 ; | |
bca3519f L |
361 | .def z_bcl = r8 ; |
362 | .def z_bch = r9 ; | |
825ecc9d L |
363 | .def z_e = r10 ; |
364 | .def z_d = r11 ; | |
bca3519f L |
365 | .def z_del = r10 ; |
366 | .def z_deh = r11 ; | |
825ecc9d L |
367 | .def z_l = r12 ; |
368 | .def z_h = r13 ; | |
bca3519f L |
369 | .def z_hll = r12 ; |
370 | .def z_hlh = r13 ; | |
825ecc9d | 371 | .def z_spl = r14 ; |
9c15f366 L |
372 | .def z_sph = r15 ; |
373 | .def temp = r16 ; | |
374 | .def temp2 = r17 ; | |
825ecc9d L |
375 | .def temp3 = r18 ; |
376 | ;.def temp4 = r19 ; | |
377 | .def intstat = r19 ;interpreter status / interrupt status | |
9c15f366 | 378 | .def z_flags = r20 ; |
825ecc9d | 379 | .def z_a = r21 ; |
9c15f366 L |
380 | .def opl = r22 ; |
381 | .def oph = r23 ; | |
382 | .def z_pcl = r24 ; | |
383 | .def z_pch = r25 ; | |
384 | ; xl ;r26 | |
385 | ; xh ;r27 | |
386 | ; yl ;r28 | |
387 | ; yh ;r29 | |
825ecc9d L |
388 | ; zl ;r30 |
389 | ; zh ;r31 | |
9c15f366 L |
390 | |
391 | ||
fa9059af | 392 | .equ i_break = 0 ;break detected flag |
80e1fa71 L |
393 | .equ i_trace = 1 ;cpu interpreter trace flag |
394 | .equ i_halt = 2 ;executing halt instruction | |
9c15f366 L |
395 | |
396 | #if defined __ATmega8__ | |
623dd899 L |
397 | #if DRAM_8BIT |
398 | ||
399 | .equ flags = UBRRL ;UART is unused with 8-Bit RAM | |
400 | #else | |
401 | .equ flags = TWBR ;TWI is unused with 4-Bit RAM | |
402 | #endif | |
403 | .equ P_PUD = SFIOR | |
404 | ||
405 | #else | |
406 | ||
407 | .equ flags = GPIOR0 | |
408 | .equ P_PUD = MCUCR | |
409 | ||
410 | #endif /* __ATmega8__ */ | |
9c15f366 L |
411 | |
412 | ; Flags: | |
413 | .equ hostact = 7 ;host active flag | |
414 | .equ hostwrt = 6 ;host written flag | |
415 | .equ rsflag = 5 ;read sector flag | |
416 | .equ readop = 4 ;1 if read operation | |
80e1fa71 L |
417 | |
418 | .equ prefixfd = 1 ;Opcode prefix DD=0, FD=1 | |
9c15f366 | 419 | |
80e1fa71 | 420 | |
79986122 L |
421 | #if EM_Z80 |
422 | #define CPUSTR "Z80" | |
423 | #else | |
424 | #define CPUSTR "8080" | |
425 | #endif | |
5c8bb361 L |
426 | #if TESTVERSION |
427 | #define TESTSTR "Test" | |
428 | #else | |
429 | #define TESTSTR "" | |
430 | #endif | |
79986122 | 431 | |
9c15f366 L |
432 | #if defined __ATmega8__ |
433 | .equ RXTXDR0 = UDR | |
434 | .equ UCSR0A = UCSRA | |
435 | .equ UDRE0 = UDRE | |
436 | .equ UCSR0B = UCSRB | |
437 | .equ RXCIE0 = RXCIE | |
438 | .equ UDRIE0 = UDRIE | |
439 | .equ RXEN0 = RXEN | |
440 | .equ TXEN0 = TXEN | |
441 | .equ UCSR0C = UCSRC | |
442 | .equ UCSZ00 = UCSZ0 | |
443 | .equ UCSZ01 = UCSZ1 | |
444 | .equ UBRR0H = UBRRH | |
445 | .equ UBRR0L = UBRRL | |
446 | .equ OCR2A = OCR2 | |
447 | .equ OC2Aaddr= OC2addr | |
448 | .equ TCCR2A = TCCR2 | |
449 | .equ TCCR2B = TCCR2 | |
450 | .equ TIMSK1 = TIMSK | |
451 | .equ TIMSK2 = TIMSK | |
452 | .equ OCIE2A = OCIE2 | |
453 | .equ TIFR1 = TIFR | |
454 | .equ ICIE1 = TICIE1 | |
455 | #else | |
456 | .equ RXTXDR0 = UDR0 | |
457 | #endif | |
458 | ||
459 | ; vim:set ts=8 noet nowrap | |
460 |