[z180-stamp.git] / avr / z80-if.c

/*
 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

/**
 *
 * Pin assignments
 *
 * | Z180-Sig   |   AVR-Port    | Dir   |
 * +------------+---------------+-------+
 * |    A0      | PA    0       |  O    |
 * |    A1      | PA    1       |  O    |
 * |    A2      | PA    2       |  O    |
 * |    A3      | PA    3       |  O    |
 * |    A4      | PA    4       |  O    |
 * |    A5      | PA    5       |  O    |
 * |    A6      | PA    6       |  O    |
 * |    A7      | PA    7       |  O    |
 * |    A8      | PC    0       |  O    |
 * |    A9      | PC    1       |  O    |
 * |    A10     | PC    2       |  O    |
 * |    A11     | PC    3       |  O    |
 * |    A12     | PC    4       |  O    |
 * |    A13     | PC    5       |  O    |
 * |    A14     | PC    6       |  O    |
 * |    A15     | PC    7       |  O    |
 * |    A16     | PE    2       |  O    |
 * |    A17     | PE    3       |  O    |
 * |    A18     | PE    4       |  O    |
 * |    D0      | PF    0       |  I/O  |
 * |    D1      | PF    1       |  I/O  |
 * |    D2      | PF    2       |  I/O  |
 * |    D3      | PF    3       |  I/O  |
 * |    D4      | PF    4       |  I/O  |
 * |    D5      | PF    5       |  I/O  |
 * |    D6      | PF    6       |  I/O  |
 * |    D7      | PF    7       |  I/O  |
 * |    RD      | PD    3       |  O    |
 * |    WR      | PD    2       |  O    |
 * |    MREQ    | PD    4       |  O    |
 * |    RST     | PD    5       |  O    |
 * |    BUSREQ  | PD    7       |  O    |
 * |    BUSACK  | PD    6       |  I    |
 * |
 * | Optional
 * +------------------------------------+
 * |    STEP    | PG    0       |  O    |
 * |    RUN     | PG    1       |  O    |
 * |    WAIT    | PG    2       |  I    |

 */


#include "z80-if.h"
#include <util/atomic.h>
#include "debug.h"
#include "config.h"
#include "env.h"


//#define P_ZCLK		PORTB
//#define ZCLK		5
//#define DDR_ZCLK	DDRB
#define P_MREQ		PORTD
#define MREQ		4
#define DDR_MREQ	DDRD
#define P_RD		PORTD
#define RD		3
#define P_WR		PORTD
#define WR		2
#define P_BUSREQ	PORTD
#define BUSREQ		7
#define DDR_BUSREQ	DDRD
#define P_BUSACK	PORTD
#define PIN_BUSACK	PIND
#define BUSACK		6
#define DDR_BUSACK	DDRD
#define P_RST		PORTD
#define PIN_RST		PIND
#define DDR_RST		DDRD
#define RST		5


#define P_DB		PORTF
#define PIN_DB		PINF
#define DDR_DB		DDRF

#define P_ADL		PORTA
#define P_ADH		PORTC
#define P_ADB		PORTE
#define PIN_ADB		PINE
#define DDR_ADL		DDRA
#define DDR_ADH		DDRC
#define DDR_ADB		DDRE

#define ADB_WIDTH	3
#define ADB_SHIFT	2
//#define ADB_PORT	PORTE


//#define Z80_O_ZCLK	SBIT(P_ZCLK, 5)
#define	Z80_O_MREQ	SBIT(P_MREQ, 4)
#define Z80_O_RD	SBIT(P_RD, 3)
#define Z80_O_WR	SBIT(P_WR, 2)
#define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI	SBIT(P_NMI, )
#define Z80_O_RST	SBIT(P_RST, 5)
#define Z80_I_RST	SBIT(PIN_RST, 5)
#define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT	SBIT(P_HALT, )

/* Optional */
#define P_RUN		PORTG
#define RUN			1
#define DDR_RUN		DDRG
#define P_STEP		PORTG
#define STEP		0
#define DDR_STEP	DDRG
#define P_WAIT		PORTG
#define WAIT		2
#define DDR_WAIT	DDRG
/* All three signals are on the same Port (PortG) */
#define PORT_SS		PORTG
#define DDR_SS		DDRG
#define PIN_SS		PING
#define	Z80_O_RUN	SBIT(PORT_SS, RUN)
#define	Z80_O_STEP	SBIT(PORT_SS, STEP)
#define	Z80_I_WAIT	SBIT(PORT_SS, WAIT)


#define BUS_TO 20


#define MASK(n)	((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))

void z80_bus_request_or_exit(void)
{
	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
		cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
}

static zstate_t zstate;
static volatile uint8_t timer;		/* used for bus timeout */
static bool reset_polarity;

/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC5A                  */
/*---------------------------------------------------------*/

ISR(TIMER5_COMPA_vect)
{

	uint8_t i = timer;

	if (i)
		timer = i - 1;
}

/*--------------------------------------------------------------------------*/


static void z80_addrbus_set_in(void)
{
	/* /MREQ, /RD, /WR: Input, no pullup */
	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
	Z80_O_MREQ = 0;
	Z80_O_RD = 0;
	Z80_O_WR = 0;

	P_ADL = 0;
	DDR_ADL = 0;
	P_ADH = 0;
	DDR_ADH = 0;
	PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_addrbus_set_out(void)
{
	/* /MREQ, /RD, /WR: Output and high */
	Z80_O_MREQ = 1;
	Z80_O_RD = 1;
	Z80_O_WR = 1;
	DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);

	DDR_ADL = 0xff;
	DDR_ADH = 0xff;
	DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_dbus_set_in(void)
{
	DDR_DB = 0;
	P_DB = 0;
}


static void z80_dbus_set_out(void)
{
	DDR_DB = 0xff;
}

static void z80_reset_active(void)
{
	if (reset_polarity)
		Z80_O_RST = 1;
	else
		Z80_O_RST = 0;
}

static void z80_reset_inactive(void)
{
	if (reset_polarity)
		Z80_O_RST = 0;
	else
		Z80_O_RST = 1;
}

static void z80_reset_pulse(void)
{
	z80_reset_active();
	_delay_us(10);
	z80_reset_inactive();
}


void z80_setup_bus(void)
{
	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {

		/* /ZRESET: Input, no pullup */
		DDR_RST &= ~_BV(RST);
		Z80_O_RST = 0;

		/* /BUSREQ: Output and high */
		Z80_O_BUSREQ = 1;
		DDR_BUSREQ |= _BV(BUSREQ);

		/* /BUSACK: Input, no pullup */
		DDR_BUSACK &= ~_BV(BUSACK);
		P_BUSACK &= ~_BV(BUSACK);

		z80_addrbus_set_in();
		z80_dbus_set_in();

		if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
			/* /RUN & /STEP: output, /WAIT: input */

			PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
			DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
		}

		reset_polarity = Z80_I_RST;
		z80_reset_active();
		DDR_RST |= _BV(RST);

		zstate = RESET;
	}

	/* Timer 5 */
	PRR1 &= ~_BV(PRTIM5);
	OCR5A = F_CPU / 1024 / 10 - 1;		  /* Timer: 10Hz interval (OC4A) */
	TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
	TIMSK5 = _BV(OCIE5A);				  /* Enable oca interrupt */

}


zstate_t z80_bus_state(void)
{
	return zstate;
}


static void z80_busreq_hpulse(void)
{
	z80_dbus_set_in();
	z80_addrbus_set_in();

#if 0
	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;
		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
	}
#endif

#if 1
	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;

		do {
			if (Z80_I_BUSACK == 1)  {
				Z80_O_BUSREQ = 0;
				break;
			}
		} while (1);
	}
#endif

	if (zstate & ZST_ACQUIRED) {
		timer = BUS_TO;
		while (Z80_I_BUSACK == 1 && timer)
			;
		if (Z80_I_BUSACK == 0)
			z80_addrbus_set_out();
	}
}


/*

 +              |               |               |               |               |
    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
       +        |               |               |               |               |
          +     |       0       |       1       |       2       |       3       |
Event        +  |               |               |               |               |
----------------+---------------+---------------+---------------+---------------+
                |               |               |               |               |
Reset           |       0       |       0       |       0       |       0       |
                |               |               |               |               |
                |               |               |               |               |
Request         |       1       |               |       3       |               |
                |               |               |               |               |
                |               |               |               |               |
Release         |               |       0       |               |       2       |
                |               |               |               |               |
                |               |               |               |               |
Run             |       2       |       3       |               |               |
                |               |               |               |               |
                |               |               |               |               |
Restart         |               |               |       2       |       3       |
                |               |               |               |               |
                |               |               |               |               |
M_Cycle         |               |               |               |       3       |
                |               |               |               |               |
                |               |               |               |               |
*/

zstate_t z80_bus_cmd(bus_cmd_t cmd)
{
	switch (cmd) {

	case Reset:
		z80_dbus_set_in();
		z80_addrbus_set_in();
		z80_reset_active();
		Z80_O_BUSREQ = 1;
		timer = BUS_TO;
		while (Z80_I_BUSACK == 0 && timer)
			;
		zstate = RESET;
		break;

	case Request:
		switch (zstate) {
		case RESET:
			Z80_O_BUSREQ = 0;
			z80_reset_inactive();
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_out();
				zstate = RESET_AQRD;
			} else {
				z80_reset_active();
				Z80_O_BUSREQ = 1;
			}
			break;

		case RUNNING:
			Z80_O_BUSREQ = 0;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_out();
				zstate = RUNNING_AQRD;
			} else {
				Z80_O_BUSREQ = 1;
			}
			break;

		default:
			break;
		}
		break;

	case Release:
		switch (zstate) {
		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			z80_reset_active();
			Z80_O_BUSREQ = 1;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 0 && timer)
				;
			zstate = RESET;
			break;
		case RUNNING_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			Z80_O_BUSREQ = 1;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 0 && timer)
				;
			zstate = RUNNING;
			break;
		default:
			break;
		}
		break;

	case Run:
		switch (zstate) {
		case RESET:
			_delay_ms(20);		/* TODO: */
			z80_reset_inactive();
			zstate = RUNNING;
			break;

		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_in();
			z80_reset_pulse();
			z80_addrbus_set_out();
			zstate = RUNNING_AQRD;
			break;
		default:
			break;
		}
		break;

	case Restart:
		switch (zstate) {
		case RUNNING:
		case RUNNING_AQRD:
			z80_reset_pulse();
			break;
		default:
			break;
		}
		break;

	case M_Cycle:
		switch (zstate) {
		case RUNNING_AQRD:
			z80_busreq_hpulse();	/* TODO: */
			break;
		default:
			break;
		}
	}
	return zstate;
}


/*--------------------------------------------------------------------------*/

static
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
	P_ADL = addr;
	P_ADH = (addr & 0xff00) >> 8;
	PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
}

int32_t z80_memsize_detect(void)
{
	const uint8_t PATTERN_1	= 0x55;
	const uint8_t PATTERN_2	= ~PATTERN_1;
	uint32_t addr;

	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
		return  -EBUSTO;

	uint8_t ram_0 = z80_read(0);
	uint8_t ram_1 = z80_read(1);

	z80_write(0, ram_0 ^ 0xff);
	z80_write(1, ram_1);
	if ((z80_read(0) ^ ram_0) != 0xff) {
		addr = 0;
	} else {
		z80_write(0, PATTERN_1);
		for (addr=1; addr < CONFIG_SYS_RAMSIZE_MAX; addr <<= 1) {
			uint8_t ram_i = z80_read(addr);
			z80_write(addr, PATTERN_2);
			if (z80_read(0) != PATTERN_1 || z80_read(addr) != PATTERN_2)
				break;
			z80_write(addr, ram_i);
		}
	}

	z80_write(0, ram_0);
	z80_bus_cmd(Release);

	return addr;
}

/*--------------------------------------------------------------------------*/

void z80_write(uint32_t addr, uint8_t data)
{
	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_out();
	P_DB = data;
	P_DB = data;
	Z80_O_WR = 0;
	Z80_O_WR = 0;
	Z80_O_WR = 1;
	Z80_O_MREQ = 1;
}

uint8_t z80_read(uint32_t addr)
{
	uint8_t data;

	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	data = PIN_DB;
	Z80_O_RD = 1;
	Z80_O_MREQ = 1;

	return data;
}


void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	P_DB = data;
	while(length--) {
		z80_setaddress(addr++);
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
{
	uint8_t data;

	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	while(length--) {
		z80_setaddress(src++);
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		data = PIN_DB;
		Z80_O_RD = 1;
		*dest++ = data;
	}
	Z80_O_MREQ = 1;
}

/*--------------------------------------------------------------------------*/

/*
  0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
  017A'                         rx.in_idx:	ds	1		;
  017B'                         rx.out_idx:	ds	1		;
  017C'                         rx.buf:		ds	rx.buf_len	;
  018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)

  018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
  018D'                         tx.in_idx:	ds	1		;
  018E'                         tx.out_idx:	ds	1		;
  018F'                         tx.buf:		ds	tx.buf_len 	;
  019E'                         tx.buf_end	equ	$-1		; last byte
*/


typedef struct __attribute__((packed)) {
	uint8_t mask;
	uint8_t in_idx;
	uint8_t out_idx;
	uint8_t buf[];
} zfifo_t;


#define FIFO_BUFSIZE_MASK	-3
#define FIFO_INDEX_IN		-2
#define FIFO_INDEX_OUT		-1


static struct {
	uint32_t base;
	uint8_t idx_out,
		idx_in,
		mask;
	} fifo_dsc[NUM_FIFOS];


void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
	fifo_dsc[f].base = addr;


	if (addr != 0) {
		z80_bus_cmd(Request);
		fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
		z80_bus_cmd(Release);

		if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) {
			DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
					f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
		}
	}
}


int z80_memfifo_is_empty(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {

		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
		uint8_t idx;

		z80_bus_cmd(Request);
		idx = z80_read(adr);
		z80_bus_cmd(Release);
		rc = idx == fifo_dsc[f].idx_out;
	}

	return rc;
}

int z80_memfifo_is_full(const fifo_t f)
{
	int rc = 0;

	if (fifo_dsc[f].base != 0) {
		z80_bus_cmd(Request);
		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
	return rc;
}


uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
	uint8_t rc, idx;

	while (z80_memfifo_is_empty(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_out;
	rc = z80_read(fifo_dsc[f].base+idx);
	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	z80_bus_cmd(Release);

	return rc;
}

int z80_memfifo_getc(const fifo_t f)
{
	int rc = -1;

	if (fifo_dsc[f].base != 0) {
		uint8_t idx = fifo_dsc[f].idx_out;
		z80_bus_cmd(Request);
		if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
			rc = z80_read(fifo_dsc[f].base+idx);
			fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
			z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
		}
		z80_bus_cmd(Release);
	}

	return rc;
}


void z80_memfifo_putc(fifo_t f, uint8_t val)
{
	int idx;

	while (z80_memfifo_is_full(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_in;
	z80_write(fifo_dsc[f].base+idx, val);
	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
	z80_bus_cmd(Release);
}

/*--------------------------------------------------------------------------*/

void z80_load_mem(int_fast8_t verbosity,
				const FLASH unsigned char data[],
				const FLASH unsigned long *sections,
				const FLASH unsigned long address[],
				const FLASH unsigned long length_of_sections[])
{
	uint32_t sec_base = 0;

	if (verbosity > 1)
		printf_P(PSTR("Loading Z180 memory... \n"));

	for (unsigned sec = 0; sec < *sections; sec++) {
		if (verbosity > 0) {
			printf_P(PSTR("   From: 0x%.5lX to: 0x%.5lX    (%5li bytes)\n"),
					address[sec],
					address[sec]+length_of_sections[sec] - 1,
					length_of_sections[sec]);
		}

		z80_write_block_P((const FLASH unsigned char *) &data[sec_base],  /* src */
				address[sec],                  /* dest */
				length_of_sections[sec]);      /* len */
		sec_base += length_of_sections[sec];
	}
}
Commit	Line	Data
35edb766 L	1	/*
	2	* (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
	3	*
a1595a8e	4	* SPDX-License-Identifier: GPL-2.0
35edb766 L	5	*/
35edb766 L	6
0c5890bb L	7	/**
	8	*
	9	* Pin assignments
	10	*
a1595a8e L	11	* \| Z180-Sig \| AVR-Port \| Dir \|
	12	* +------------+---------------+-------+
	13	* \| A0 \| PA 0 \| O \|
	14	* \| A1 \| PA 1 \| O \|
	15	* \| A2 \| PA 2 \| O \|
	16	* \| A3 \| PA 3 \| O \|
	17	* \| A4 \| PA 4 \| O \|
	18	* \| A5 \| PA 5 \| O \|
	19	* \| A6 \| PA 6 \| O \|
	20	* \| A7 \| PA 7 \| O \|
	21	* \| A8 \| PC 0 \| O \|
	22	* \| A9 \| PC 1 \| O \|
	23	* \| A10 \| PC 2 \| O \|
	24	* \| A11 \| PC 3 \| O \|
	25	* \| A12 \| PC 4 \| O \|
	26	* \| A13 \| PC 5 \| O \|
	27	* \| A14 \| PC 6 \| O \|
	28	* \| A15 \| PC 7 \| O \|
	29	* \| A16 \| PE 2 \| O \|
	30	* \| A17 \| PE 3 \| O \|
	31	* \| A18 \| PE 4 \| O \|
	32	* \| D0 \| PF 0 \| I/O \|
	33	* \| D1 \| PF 1 \| I/O \|
	34	* \| D2 \| PF 2 \| I/O \|
	35	* \| D3 \| PF 3 \| I/O \|
	36	* \| D4 \| PF 4 \| I/O \|
	37	* \| D5 \| PF 5 \| I/O \|
	38	* \| D6 \| PF 6 \| I/O \|
	39	* \| D7 \| PF 7 \| I/O \|
	40	* \| RD \| PD 3 \| O \|
	41	* \| WR \| PD 2 \| O \|
	42	* \| MREQ \| PD 4 \| O \|
	43	* \| RST \| PD 5 \| O \|
	44	* \| BUSREQ \| PD 7 \| O \|
	45	* \| BUSACK \| PD 6 \| I \|
	46	* \|
	47	* \| Optional
	48	* +------------------------------------+
	49	* \| STEP \| PG 0 \| O \|
	50	* \| RUN \| PG 1 \| O \|
	51	* \| WAIT \| PG 2 \| I \|
0c5890bb	52
0c5890bb L	53	*/
0c5890bb L	54
ea6971b8	55
a1595a8e	56	#include "z80-if.h"
f338df2a	57	#include <util/atomic.h>
0c5890bb	58	#include "debug.h"
a1595a8e L	59	#include "config.h"
a1595a8e L	60	#include "env.h"
0c5890bb	61
0c5890bb	62
41d36f28 L	63	//#define P_ZCLK PORTB
	64	//#define ZCLK 5
	65	//#define DDR_ZCLK DDRB
0c5890bb L	66	#define P_MREQ PORTD
	67	#define MREQ 4
	68	#define DDR_MREQ DDRD
	69	#define P_RD PORTD
	70	#define RD 3
	71	#define P_WR PORTD
	72	#define WR 2
	73	#define P_BUSREQ PORTD
	74	#define BUSREQ 7
	75	#define DDR_BUSREQ DDRD
	76	#define P_BUSACK PORTD
9b6b4b31	77	#define PIN_BUSACK PIND
0c5890bb L	78	#define BUSACK 6
0c5890bb L	79	#define DDR_BUSACK DDRD
0c5890bb	80	#define P_RST PORTD
61bd408c	81	#define PIN_RST PIND
0c5890bb L	82	#define DDR_RST DDRD
	83	#define RST 5
	84
	85
	86	#define P_DB PORTF
	87	#define PIN_DB PINF
	88	#define DDR_DB DDRF
	89
	90	#define P_ADL PORTA
	91	#define P_ADH PORTC
	92	#define P_ADB PORTE
	93	#define PIN_ADB PINE
9b6b4b31 L	94	#define DDR_ADL DDRA
9b6b4b31 L	95	#define DDR_ADH DDRC
0c5890bb L	96	#define DDR_ADB DDRE
	97
	98	#define ADB_WIDTH 3
	99	#define ADB_SHIFT 2
	100	//#define ADB_PORT PORTE
	101
	102
41d36f28	103	//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
0c5890bb L	104	#define Z80_O_MREQ SBIT(P_MREQ, 4)
	105	#define Z80_O_RD SBIT(P_RD, 3)
	106	#define Z80_O_WR SBIT(P_WR, 2)
	107	#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
	108	//#define Z80_O_NMI SBIT(P_NMI, )
	109	#define Z80_O_RST SBIT(P_RST, 5)
61bd408c	110	#define Z80_I_RST SBIT(PIN_RST, 5)
9b6b4b31	111	#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
0c5890bb L	112	//#define Z80_I_HALT SBIT(P_HALT, )
0c5890bb L	113
a1595a8e L	114	/* Optional */
	115	#define P_RUN PORTG
	116	#define RUN 1
	117	#define DDR_RUN DDRG
	118	#define P_STEP PORTG
	119	#define STEP 0
	120	#define DDR_STEP DDRG
	121	#define P_WAIT PORTG
	122	#define WAIT 2
	123	#define DDR_WAIT DDRG
	124	/* All three signals are on the same Port (PortG) */
	125	#define PORT_SS PORTG
	126	#define DDR_SS DDRG
	127	#define PIN_SS PING
	128	#define Z80_O_RUN SBIT(PORT_SS, RUN)
	129	#define Z80_O_STEP SBIT(PORT_SS, STEP)
	130	#define Z80_I_WAIT SBIT(PORT_SS, WAIT)
	131
9b6b4b31	132
ea6971b8 L	133	#define BUS_TO 20
	134
	135
0c5890bb L	136	#define MASK(n) ((1<<(n))-1)
	137	#define SMASK(w,s) (MASK(w) << (s))
	138
b35fcb2f L	139	void z80_bus_request_or_exit(void)
	140	{
	141	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
	142	cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
	143	}
0c5890bb	144
f338df2a	145	static zstate_t zstate;
ea6971b8	146	static volatile uint8_t timer; /* used for bus timeout */
61bd408c	147	static bool reset_polarity;
ea6971b8 L	148
ea6971b8 L	149	/---------------------------------------------------------/
f66d9570	150	/* 10Hz timer interrupt generated by OC5A */
ea6971b8 L	151	/---------------------------------------------------------/
ea6971b8 L	152
a1595a8e	153	ISR(TIMER5_COMPA_vect)
ea6971b8 L	154	{
	155
	156	uint8_t i = timer;
	157
	158	if (i)
	159	timer = i - 1;
	160	}
eded7ec4	161
0c5890bb L	162	/--------------------------------------------------------------------------/
0c5890bb L	163
6035a17b	164
a1595a8e	165	static void z80_addrbus_set_in(void)
0c5890bb	166	{
9b6b4b31 L	167	/* /MREQ, /RD, /WR: Input, no pullup */
	168	DDR_MREQ &= ~(_BV(MREQ) \| _BV(RD) \| _BV(WR));
	169	Z80_O_MREQ = 0;
	170	Z80_O_RD = 0;
	171	Z80_O_WR = 0;
	172
0c5890bb L	173	P_ADL = 0;
	174	DDR_ADL = 0;
	175	P_ADH = 0;
	176	DDR_ADH = 0;
6353e862	177	PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
0c5890bb L	178	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	179	}
	180
54678798	181
a1595a8e	182	static void z80_addrbus_set_out(void)
0c5890bb	183	{
9b6b4b31 L	184	/* /MREQ, /RD, /WR: Output and high */
	185	Z80_O_MREQ = 1;
	186	Z80_O_RD = 1;
	187	Z80_O_WR = 1;
	188	DDR_MREQ \|= _BV(MREQ) \| _BV(RD) \| _BV(WR);
	189
0c5890bb L	190	DDR_ADL = 0xff;
	191	DDR_ADH = 0xff;
	192	DDR_ADB = DDR_ADB \| (MASK(ADB_WIDTH) << ADB_SHIFT);
	193	}
	194
	195
6035a17b	196	static void z80_dbus_set_in(void)
0c5890bb L	197	{
	198	DDR_DB = 0;
	199	P_DB = 0;
	200	}
	201
62f624d3	202
6035a17b	203	static void z80_dbus_set_out(void)
0c5890bb L	204	{
	205	DDR_DB = 0xff;
	206	}
	207
61bd408c L	208	static void z80_reset_active(void)
	209	{
	210	if (reset_polarity)
	211	Z80_O_RST = 1;
	212	else
	213	Z80_O_RST = 0;
	214	}
	215
	216	static void z80_reset_inactive(void)
	217	{
	218	if (reset_polarity)
	219	Z80_O_RST = 0;
	220	else
	221	Z80_O_RST = 1;
	222	}
62f624d3 L	223
	224	static void z80_reset_pulse(void)
	225	{
61bd408c	226	z80_reset_active();
62f624d3	227	_delay_us(10);
61bd408c	228	z80_reset_inactive();
62f624d3 L	229	}
	230
	231
0c5890bb L	232	void z80_setup_bus(void)
0c5890bb L	233	{
a1595a8e L	234	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
a1595a8e L	235
61bd408c L	236	/* /ZRESET: Input, no pullup */
61bd408c L	237	DDR_RST &= ~_BV(RST);
a1595a8e	238	Z80_O_RST = 0;
0c5890bb	239
a1595a8e L	240	/* /BUSREQ: Output and high */
	241	Z80_O_BUSREQ = 1;
	242	DDR_BUSREQ \|= _BV(BUSREQ);
0c5890bb	243
a1595a8e L	244	/* /BUSACK: Input, no pullup */
	245	DDR_BUSACK &= ~_BV(BUSACK);
	246	P_BUSACK &= ~_BV(BUSACK);
0c5890bb	247
a1595a8e L	248	z80_addrbus_set_in();
a1595a8e L	249	z80_dbus_set_in();
0c5890bb	250
a1595a8e L	251	if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
a1595a8e L	252	/* /RUN & /STEP: output, /WAIT: input */
72f58822	253
a1595a8e L	254	PORT_SS = (PORT_SS & ~_BV(RUN)) \| _BV(STEP);
	255	DDR_SS = (DDR_SS & ~_BV(WAIT)) \| _BV(RUN) \| _BV(STEP);
	256	}
	257
61bd408c L	258	reset_polarity = Z80_I_RST;
	259	z80_reset_active();
	260	DDR_RST \|= _BV(RST);
	261
a1595a8e L	262	zstate = RESET;
a1595a8e L	263	}
ea6971b8	264
a1595a8e L	265	/* Timer 5 */
	266	PRR1 &= ~_BV(PRTIM5);
	267	OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
	268	TCCR5B = (0b01<<WGM52)\|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
	269	TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */
ea6971b8	270
0c5890bb L	271	}
0c5890bb L	272
f338df2a	273
62f624d3	274	zstate_t z80_bus_state(void)
f338df2a L	275	{
	276	return zstate;
	277	}
	278
62f624d3 L	279
62f624d3 L	280	static void z80_busreq_hpulse(void)
0c5890bb	281	{
6035a17b	282	z80_dbus_set_in();
a1595a8e	283	z80_addrbus_set_in();
72f58822	284
a1595a8e	285	#if 0
8a7decea	286	ATOMIC_BLOCK(ATOMIC_FORCEON) {
62f624d3 L	287	Z80_O_BUSREQ = 1;
	288	Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
	289	Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
f338df2a	290	}
a1595a8e L	291	#endif
a1595a8e L	292
4b0604a4	293	#if 1
a1595a8e L	294	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	295	Z80_O_BUSREQ = 1;
	296
	297	do {
	298	if (Z80_I_BUSACK == 1) {
	299	Z80_O_BUSREQ = 0;
	300	break;
	301	}
	302	} while (1);
	303	}
4b0604a4	304	#endif
72f58822	305
62f624d3	306	if (zstate & ZST_ACQUIRED) {
ea6971b8 L	307	timer = BUS_TO;
ea6971b8 L	308	while (Z80_I_BUSACK == 1 && timer)
f338df2a	309	;
ea6971b8	310	if (Z80_I_BUSACK == 0)
a1595a8e	311	z80_addrbus_set_out();
f338df2a	312	}
f338df2a L	313	}
f338df2a L	314
f338df2a L	315
f338df2a L	316	/*
f338df2a	317
ea6971b8	318	+ \| \| \| \| \|
62f624d3	319	+ State \| RESET \| RESET_AQRD \| RUNNING \| RUNNING_AQRD \|
ea6971b8 L	320	+ \| \| \| \| \|
	321	+ \| 0 \| 1 \| 2 \| 3 \|
	322	Event + \| \| \| \| \|
62f624d3	323	----------------+---------------+---------------+---------------+---------------+
ea6971b8 L	324	\| \| \| \| \|
	325	Reset \| 0 \| 0 \| 0 \| 0 \|
	326	\| \| \| \| \|
	327	\| \| \| \| \|
	328	Request \| 1 \| \| 3 \| \|
	329	\| \| \| \| \|
	330	\| \| \| \| \|
	331	Release \| \| 0 \| \| 2 \|
	332	\| \| \| \| \|
	333	\| \| \| \| \|
	334	Run \| 2 \| 3 \| \| \|
	335	\| \| \| \| \|
	336	\| \| \| \| \|
	337	Restart \| \| \| 2 \| 3 \|
	338	\| \| \| \| \|
	339	\| \| \| \| \|
	340	M_Cycle \| \| \| \| 3 \|
	341	\| \| \| \| \|
	342	\| \| \| \| \|
62f624d3	343	*/
f338df2a	344
62f624d3	345	zstate_t z80_bus_cmd(bus_cmd_t cmd)
f338df2a	346	{
62f624d3	347	switch (cmd) {
f338df2a	348
62f624d3	349	case Reset:
6035a17b	350	z80_dbus_set_in();
a1595a8e	351	z80_addrbus_set_in();
61bd408c	352	z80_reset_active();
62f624d3	353	Z80_O_BUSREQ = 1;
f66d9570 L	354	timer = BUS_TO;
	355	while (Z80_I_BUSACK == 0 && timer)
	356	;
62f624d3	357	zstate = RESET;
f338df2a L	358	break;
f338df2a L	359
62f624d3 L	360	case Request:
	361	switch (zstate) {
	362	case RESET:
	363	Z80_O_BUSREQ = 0;
61bd408c	364	z80_reset_inactive();
ea6971b8 L	365	timer = BUS_TO;
ea6971b8 L	366	while (Z80_I_BUSACK == 1 && timer)
62f624d3	367	;
ea6971b8	368	if (Z80_I_BUSACK == 0) {
a1595a8e	369	z80_addrbus_set_out();
ea6971b8 L	370	zstate = RESET_AQRD;
ea6971b8 L	371	} else {
61bd408c	372	z80_reset_active();
ea6971b8 L	373	Z80_O_BUSREQ = 1;
ea6971b8 L	374	}
62f624d3 L	375	break;
	376
	377	case RUNNING:
	378	Z80_O_BUSREQ = 0;
ea6971b8 L	379	timer = BUS_TO;
ea6971b8 L	380	while (Z80_I_BUSACK == 1 && timer)
62f624d3	381	;
ea6971b8	382	if (Z80_I_BUSACK == 0) {
a1595a8e	383	z80_addrbus_set_out();
ea6971b8 L	384	zstate = RUNNING_AQRD;
	385	} else {
	386	Z80_O_BUSREQ = 1;
	387	}
62f624d3 L	388	break;
	389
	390	default:
	391	break;
	392	}
f338df2a	393	break;
f338df2a	394
62f624d3 L	395	case Release:
	396	switch (zstate) {
	397	case RESET_AQRD:
6035a17b	398	z80_dbus_set_in();
a1595a8e	399	z80_addrbus_set_in();
61bd408c	400	z80_reset_active();
62f624d3	401	Z80_O_BUSREQ = 1;
f66d9570 L	402	timer = BUS_TO;
	403	while (Z80_I_BUSACK == 0 && timer)
	404	;
62f624d3 L	405	zstate = RESET;
	406	break;
	407	case RUNNING_AQRD:
6035a17b	408	z80_dbus_set_in();
a1595a8e	409	z80_addrbus_set_in();
62f624d3	410	Z80_O_BUSREQ = 1;
f66d9570 L	411	timer = BUS_TO;
	412	while (Z80_I_BUSACK == 0 && timer)
	413	;
62f624d3 L	414	zstate = RUNNING;
	415	break;
	416	default:
	417	break;
	418	}
	419	break;
f338df2a	420
62f624d3 L	421	case Run:
	422	switch (zstate) {
	423	case RESET:
f66d9570	424	_delay_ms(20); /* TODO: */
61bd408c	425	z80_reset_inactive();
62f624d3 L	426	zstate = RUNNING;
	427	break;
	428
	429	case RESET_AQRD:
6035a17b	430	z80_dbus_set_in();
a1595a8e	431	z80_addrbus_set_in();
62f624d3	432	z80_reset_pulse();
a1595a8e	433	z80_addrbus_set_out();
62f624d3 L	434	zstate = RUNNING_AQRD;
	435	break;
	436	default:
	437	break;
	438	}
	439	break;
f338df2a	440
62f624d3 L	441	case Restart:
	442	switch (zstate) {
	443	case RUNNING:
	444	case RUNNING_AQRD:
	445	z80_reset_pulse();
	446	break;
	447	default:
	448	break;
	449	}
	450	break;
f338df2a	451
62f624d3 L	452	case M_Cycle:
	453	switch (zstate) {
	454	case RUNNING_AQRD:
ea6971b8	455	z80_busreq_hpulse(); /* TODO: */
62f624d3 L	456	break;
	457	default:
	458	break;
	459	}
f338df2a	460	}
62f624d3	461	return zstate;
9b6b4b31 L	462	}
9b6b4b31 L	463
62f624d3	464
9b6b4b31 L	465	/--------------------------------------------------------------------------/
9b6b4b31 L	466
54678798	467	static
9b6b4b31 L	468	//inline __attribute__ ((always_inline))
	469	void z80_setaddress(uint32_t addr)
	470	{
a1595a8e L	471	P_ADL = addr;
	472	P_ADH = (addr & 0xff00) >> 8;
	473	PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
0c5890bb L	474	}
0c5890bb L	475
1e5609bf L	476	int32_t z80_memsize_detect(void)
	477	{
	478	const uint8_t PATTERN_1 = 0x55;
	479	const uint8_t PATTERN_2 = ~PATTERN_1;
	480	uint32_t addr;
	481
	482	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
	483	return -EBUSTO;
	484
	485	uint8_t ram_0 = z80_read(0);
	486	uint8_t ram_1 = z80_read(1);
	487
	488	z80_write(0, ram_0 ^ 0xff);
	489	z80_write(1, ram_1);
	490	if ((z80_read(0) ^ ram_0) != 0xff) {
	491	addr = 0;
	492	} else {
	493	z80_write(0, PATTERN_1);
	494	for (addr=1; addr < CONFIG_SYS_RAMSIZE_MAX; addr <<= 1) {
	495	uint8_t ram_i = z80_read(addr);
	496	z80_write(addr, PATTERN_2);
	497	if (z80_read(0) != PATTERN_1 \|\| z80_read(addr) != PATTERN_2)
	498	break;
	499	z80_write(addr, ram_i);
	500	}
	501	}
	502
	503	z80_write(0, ram_0);
	504	z80_bus_cmd(Release);
	505
	506	return addr;
	507	}
	508
226d3221 L	509	/--------------------------------------------------------------------------/
226d3221 L	510
0c5890bb L	511	void z80_write(uint32_t addr, uint8_t data)
	512	{
	513	z80_setaddress(addr);
	514	Z80_O_MREQ = 0;
6035a17b	515	z80_dbus_set_out();
9b6b4b31 L	516	P_DB = data;
	517	P_DB = data;
	518	Z80_O_WR = 0;
0c5890bb L	519	Z80_O_WR = 0;
	520	Z80_O_WR = 1;
	521	Z80_O_MREQ = 1;
	522	}
	523
	524	uint8_t z80_read(uint32_t addr)
	525	{
	526	uint8_t data;
	527
	528	z80_setaddress(addr);
	529	Z80_O_MREQ = 0;
6035a17b	530	z80_dbus_set_in();
0c5890bb L	531	Z80_O_RD = 0;
0c5890bb L	532	Z80_O_RD = 0;
9b6b4b31	533	Z80_O_RD = 0;
0c5890bb L	534	data = PIN_DB;
	535	Z80_O_RD = 1;
	536	Z80_O_MREQ = 1;
	537
	538	return data;
	539	}
	540
	541
	542	void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
	543	{
6035a17b	544	z80_dbus_set_out();
0c5890bb	545	Z80_O_MREQ = 0;
ea6971b8	546	P_DB = data;
0c5890bb L	547	while(length--) {
0c5890bb L	548	z80_setaddress(addr++);
ea6971b8 L	549	Z80_O_WR = 0;
	550	Z80_O_WR = 0;
	551	Z80_O_WR = 1;
	552	}
	553	Z80_O_MREQ = 1;
	554	}
	555
	556	void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
	557	{
	558	uint8_t data;
	559
	560	z80_dbus_set_out();
	561	Z80_O_MREQ = 0;
	562	while(length--) {
	563	z80_setaddress(dest++);
	564	data = *src++;
0c5890bb	565	P_DB = data;
9b6b4b31 L	566	P_DB = data;
9b6b4b31 L	567	Z80_O_WR = 0;
0c5890bb L	568	Z80_O_WR = 0;
	569	Z80_O_WR = 1;
	570	}
	571	Z80_O_MREQ = 1;
	572	}
	573
ea6971b8	574	void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
0c5890bb L	575	{
0c5890bb L	576	uint8_t data;
54678798	577
6035a17b	578	z80_dbus_set_out();
0c5890bb L	579	Z80_O_MREQ = 0;
	580	while(length--) {
	581	z80_setaddress(dest++);
	582	data = *src++;
	583	P_DB = data;
9b6b4b31 L	584	P_DB = data;
9b6b4b31 L	585	Z80_O_WR = 0;
0c5890bb L	586	Z80_O_WR = 0;
	587	Z80_O_WR = 1;
	588	}
	589	Z80_O_MREQ = 1;
	590	}
	591
ea6971b8 L	592	void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
	593	{
	594	uint8_t data;
	595
	596	Z80_O_MREQ = 0;
	597	z80_dbus_set_in();
	598	while(length--) {
	599	z80_setaddress(src++);
	600	Z80_O_RD = 0;
	601	Z80_O_RD = 0;
	602	Z80_O_RD = 0;
	603	data = PIN_DB;
	604	Z80_O_RD = 1;
	605	*dest++ = data;
	606	}
	607	Z80_O_MREQ = 1;
	608	}
	609
226d3221	610	/--------------------------------------------------------------------------/
ea6971b8	611
0c5890bb L	612	/*
	613	0179' rx.bs_mask: ds 1 ; (buf_len - 1)
	614	017A' rx.in_idx: ds 1 ;
	615	017B' rx.out_idx: ds 1 ;
	616	017C' rx.buf: ds rx.buf_len ;
	617	018B' rx.buf_end equ $-1 ; last byte (start+len-1)
54678798	618
0c5890bb L	619	018C' tx.bs_mask: ds 1 ; (buf_len - 1)
	620	018D' tx.in_idx: ds 1 ;
	621	018E' tx.out_idx: ds 1 ;
	622	018F' tx.buf: ds tx.buf_len ;
	623	019E' tx.buf_end equ $-1 ; last byte
	624	*/
	625
	626
	627	typedef struct __attribute__((packed)) {
	628	uint8_t mask;
	629	uint8_t in_idx;
	630	uint8_t out_idx;
	631	uint8_t buf[];
	632	} zfifo_t;
	633
	634
	635
	636	#define FIFO_BUFSIZE_MASK -3
	637	#define FIFO_INDEX_IN -2
	638	#define FIFO_INDEX_OUT -1
	639
	640
	641	static struct {
	642	uint32_t base;
	643	uint8_t idx_out,
	644	idx_in,
	645	mask;
	646	} fifo_dsc[NUM_FIFOS];
54678798	647
0c5890bb	648
8a7decea	649	void z80_memfifo_init(const fifo_t f, uint32_t addr)
0c5890bb	650	{
8a7decea	651	fifo_dsc[f].base = addr;
0c5890bb	652
0c5890bb	653
bbd45c46	654	if (addr != 0) {
8a7decea L	655	z80_bus_cmd(Request);
	656	fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
	657	fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
	658	fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
	659	z80_bus_cmd(Release);
910e7206 L	660
	661	if (fifo_dsc[f].idx_in != 0 \|\| fifo_dsc[f].idx_out != 0) {
	662	DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
	663	f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
	664	}
8a7decea	665	}
0c5890bb L	666	}
	667
	668
	669	int z80_memfifo_is_empty(const fifo_t f)
	670	{
	671	int rc = 1;
	672
89adce76	673	if (fifo_dsc[f].base != 0) {
0c5890bb L	674
	675	uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
	676	uint8_t idx;
	677
62f624d3	678	z80_bus_cmd(Request);
0c5890bb	679	idx = z80_read(adr);
62f624d3	680	z80_bus_cmd(Release);
0c5890bb L	681	rc = idx == fifo_dsc[f].idx_out;
	682	}
	683
	684	return rc;
	685	}
	686
	687	int z80_memfifo_is_full(const fifo_t f)
	688	{
ce47d431	689	int rc = 0;
54678798	690
0c5890bb	691	if (fifo_dsc[f].base != 0) {
62f624d3	692	z80_bus_cmd(Request);
0c5890bb L	693	rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
0c5890bb L	694	== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
62f624d3	695	z80_bus_cmd(Release);
0c5890bb L	696	}
	697	return rc;
	698	}
	699
89adce76 L	700
89adce76 L	701	uint8_t z80_memfifo_getc_wait(const fifo_t f)
0c5890bb L	702	{
0c5890bb L	703	uint8_t rc, idx;
54678798	704
0c5890bb L	705	while (z80_memfifo_is_empty(f))
	706	;
	707
62f624d3	708	z80_bus_cmd(Request);
0c5890bb L	709	idx = fifo_dsc[f].idx_out;
	710	rc = z80_read(fifo_dsc[f].base+idx);
	711	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	712	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
62f624d3	713	z80_bus_cmd(Release);
54678798	714
0c5890bb L	715	return rc;
	716	}
	717
89adce76 L	718	int z80_memfifo_getc(const fifo_t f)
	719	{
	720	int rc = -1;
	721
	722	if (fifo_dsc[f].base != 0) {
	723	uint8_t idx = fifo_dsc[f].idx_out;
	724	z80_bus_cmd(Request);
	725	if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
	726	rc = z80_read(fifo_dsc[f].base+idx);
	727	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	728	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	729	}
	730	z80_bus_cmd(Release);
	731	}
	732
	733	return rc;
	734	}
	735
0c5890bb L	736
	737	void z80_memfifo_putc(fifo_t f, uint8_t val)
	738	{
	739	int idx;
54678798	740
0c5890bb L	741	while (z80_memfifo_is_full(f))
	742	;
	743
62f624d3	744	z80_bus_cmd(Request);
0c5890bb L	745	idx = fifo_dsc[f].idx_in;
	746	z80_write(fifo_dsc[f].base+idx, val);
	747	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	748	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
62f624d3	749	z80_bus_cmd(Release);
0c5890bb	750	}
226d3221 L	751
	752	/--------------------------------------------------------------------------/
	753
	754	void z80_load_mem(int_fast8_t verbosity,
	755	const FLASH unsigned char data[],
	756	const FLASH unsigned long *sections,
	757	const FLASH unsigned long address[],
	758	const FLASH unsigned long length_of_sections[])
	759	{
	760	uint32_t sec_base = 0;
	761
	762	if (verbosity > 1)
	763	printf_P(PSTR("Loading Z180 memory... \n"));
	764
	765	for (unsigned sec = 0; sec < *sections; sec++) {
	766	if (verbosity > 0) {
	767	printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
	768	address[sec],
	769	address[sec]+length_of_sections[sec] - 1,
	770	length_of_sections[sec]);
	771	}
	772
	773	z80_write_block_P((const FLASH unsigned char ) &data[sec_base], / src */
	774	address[sec], /* dest */
	775	length_of_sections[sec]); /* len */
	776	sec_base += length_of_sections[sec];
	777	}
	778	}