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Commit | Line | Data |
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35edb766 L |
1 | /* |
2 | * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de> | |
3 | * | |
a1595a8e | 4 | * SPDX-License-Identifier: GPL-2.0 |
35edb766 L |
5 | */ |
6 | ||
0c5890bb L |
7 | /** |
8 | * | |
9 | * Pin assignments | |
10 | * | |
a1595a8e L |
11 | * | Z180-Sig | AVR-Port | Dir | |
12 | * +------------+---------------+-------+ | |
13 | * | A0 | PA 0 | O | | |
14 | * | A1 | PA 1 | O | | |
15 | * | A2 | PA 2 | O | | |
16 | * | A3 | PA 3 | O | | |
17 | * | A4 | PA 4 | O | | |
18 | * | A5 | PA 5 | O | | |
19 | * | A6 | PA 6 | O | | |
20 | * | A7 | PA 7 | O | | |
21 | * | A8 | PC 0 | O | | |
22 | * | A9 | PC 1 | O | | |
23 | * | A10 | PC 2 | O | | |
24 | * | A11 | PC 3 | O | | |
25 | * | A12 | PC 4 | O | | |
26 | * | A13 | PC 5 | O | | |
27 | * | A14 | PC 6 | O | | |
28 | * | A15 | PC 7 | O | | |
29 | * | A16 | PE 2 | O | | |
30 | * | A17 | PE 3 | O | | |
31 | * | A18 | PE 4 | O | | |
32 | * | D0 | PF 0 | I/O | | |
33 | * | D1 | PF 1 | I/O | | |
34 | * | D2 | PF 2 | I/O | | |
35 | * | D3 | PF 3 | I/O | | |
36 | * | D4 | PF 4 | I/O | | |
37 | * | D5 | PF 5 | I/O | | |
38 | * | D6 | PF 6 | I/O | | |
39 | * | D7 | PF 7 | I/O | | |
40 | * | RD | PD 3 | O | | |
41 | * | WR | PD 2 | O | | |
42 | * | MREQ | PD 4 | O | | |
43 | * | RST | PD 5 | O | | |
44 | * | BUSREQ | PD 7 | O | | |
45 | * | BUSACK | PD 6 | I | | |
46 | * | | |
47 | * | Optional | |
48 | * +------------------------------------+ | |
49 | * | STEP | PG 0 | O | | |
50 | * | RUN | PG 1 | O | | |
51 | * | WAIT | PG 2 | I | | |
0c5890bb | 52 | |
0c5890bb L |
53 | */ |
54 | ||
ea6971b8 | 55 | |
a1595a8e | 56 | #include "z80-if.h" |
f338df2a | 57 | #include <util/atomic.h> |
0c5890bb | 58 | #include "debug.h" |
a1595a8e L |
59 | #include "config.h" |
60 | #include "env.h" | |
0c5890bb | 61 | |
0c5890bb | 62 | |
41d36f28 L |
63 | //#define P_ZCLK PORTB |
64 | //#define ZCLK 5 | |
65 | //#define DDR_ZCLK DDRB | |
0c5890bb L |
66 | #define P_MREQ PORTD |
67 | #define MREQ 4 | |
68 | #define DDR_MREQ DDRD | |
69 | #define P_RD PORTD | |
70 | #define RD 3 | |
71 | #define P_WR PORTD | |
72 | #define WR 2 | |
73 | #define P_BUSREQ PORTD | |
74 | #define BUSREQ 7 | |
75 | #define DDR_BUSREQ DDRD | |
76 | #define P_BUSACK PORTD | |
9b6b4b31 | 77 | #define PIN_BUSACK PIND |
0c5890bb L |
78 | #define BUSACK 6 |
79 | #define DDR_BUSACK DDRD | |
0c5890bb | 80 | #define P_RST PORTD |
61bd408c | 81 | #define PIN_RST PIND |
0c5890bb L |
82 | #define DDR_RST DDRD |
83 | #define RST 5 | |
84 | ||
85 | ||
86 | #define P_DB PORTF | |
87 | #define PIN_DB PINF | |
88 | #define DDR_DB DDRF | |
89 | ||
90 | #define P_ADL PORTA | |
91 | #define P_ADH PORTC | |
92 | #define P_ADB PORTE | |
93 | #define PIN_ADB PINE | |
9b6b4b31 L |
94 | #define DDR_ADL DDRA |
95 | #define DDR_ADH DDRC | |
0c5890bb L |
96 | #define DDR_ADB DDRE |
97 | ||
98 | #define ADB_WIDTH 3 | |
99 | #define ADB_SHIFT 2 | |
100 | //#define ADB_PORT PORTE | |
101 | ||
102 | ||
41d36f28 | 103 | //#define Z80_O_ZCLK SBIT(P_ZCLK, 5) |
0c5890bb L |
104 | #define Z80_O_MREQ SBIT(P_MREQ, 4) |
105 | #define Z80_O_RD SBIT(P_RD, 3) | |
106 | #define Z80_O_WR SBIT(P_WR, 2) | |
107 | #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) | |
108 | //#define Z80_O_NMI SBIT(P_NMI, ) | |
109 | #define Z80_O_RST SBIT(P_RST, 5) | |
61bd408c | 110 | #define Z80_I_RST SBIT(PIN_RST, 5) |
9b6b4b31 | 111 | #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6) |
0c5890bb L |
112 | //#define Z80_I_HALT SBIT(P_HALT, ) |
113 | ||
a1595a8e L |
114 | /* Optional */ |
115 | #define P_RUN PORTG | |
116 | #define RUN 1 | |
117 | #define DDR_RUN DDRG | |
118 | #define P_STEP PORTG | |
119 | #define STEP 0 | |
120 | #define DDR_STEP DDRG | |
121 | #define P_WAIT PORTG | |
122 | #define WAIT 2 | |
123 | #define DDR_WAIT DDRG | |
124 | /* All three signals are on the same Port (PortG) */ | |
125 | #define PORT_SS PORTG | |
126 | #define DDR_SS DDRG | |
127 | #define PIN_SS PING | |
128 | #define Z80_O_RUN SBIT(PORT_SS, RUN) | |
129 | #define Z80_O_STEP SBIT(PORT_SS, STEP) | |
130 | #define Z80_I_WAIT SBIT(PORT_SS, WAIT) | |
131 | ||
9b6b4b31 | 132 | |
ea6971b8 L |
133 | #define BUS_TO 20 |
134 | ||
135 | ||
0c5890bb L |
136 | #define MASK(n) ((1<<(n))-1) |
137 | #define SMASK(w,s) (MASK(w) << (s)) | |
138 | ||
b35fcb2f L |
139 | void z80_bus_request_or_exit(void) |
140 | { | |
141 | if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) | |
142 | cmd_error(CMD_RET_FAILURE, EBUSTO, NULL); | |
143 | } | |
0c5890bb | 144 | |
f338df2a | 145 | static zstate_t zstate; |
ea6971b8 | 146 | static volatile uint8_t timer; /* used for bus timeout */ |
61bd408c | 147 | static bool reset_polarity; |
ea6971b8 L |
148 | |
149 | /*---------------------------------------------------------*/ | |
150 | /* 10Hz timer interrupt generated by OC4A */ | |
151 | /*---------------------------------------------------------*/ | |
152 | ||
a1595a8e | 153 | ISR(TIMER5_COMPA_vect) |
ea6971b8 L |
154 | { |
155 | ||
156 | uint8_t i = timer; | |
157 | ||
158 | if (i) | |
159 | timer = i - 1; | |
160 | } | |
eded7ec4 | 161 | |
0c5890bb L |
162 | /*--------------------------------------------------------------------------*/ |
163 | ||
6035a17b | 164 | |
a1595a8e | 165 | static void z80_addrbus_set_in(void) |
0c5890bb | 166 | { |
9b6b4b31 L |
167 | /* /MREQ, /RD, /WR: Input, no pullup */ |
168 | DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); | |
169 | Z80_O_MREQ = 0; | |
170 | Z80_O_RD = 0; | |
171 | Z80_O_WR = 0; | |
172 | ||
0c5890bb L |
173 | P_ADL = 0; |
174 | DDR_ADL = 0; | |
175 | P_ADH = 0; | |
176 | DDR_ADH = 0; | |
6353e862 | 177 | PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT); |
0c5890bb L |
178 | DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); |
179 | } | |
180 | ||
54678798 | 181 | |
a1595a8e | 182 | static void z80_addrbus_set_out(void) |
0c5890bb | 183 | { |
9b6b4b31 L |
184 | /* /MREQ, /RD, /WR: Output and high */ |
185 | Z80_O_MREQ = 1; | |
186 | Z80_O_RD = 1; | |
187 | Z80_O_WR = 1; | |
188 | DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); | |
189 | ||
0c5890bb L |
190 | DDR_ADL = 0xff; |
191 | DDR_ADH = 0xff; | |
192 | DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT); | |
193 | } | |
194 | ||
195 | ||
6035a17b | 196 | static void z80_dbus_set_in(void) |
0c5890bb L |
197 | { |
198 | DDR_DB = 0; | |
199 | P_DB = 0; | |
200 | } | |
201 | ||
62f624d3 | 202 | |
6035a17b | 203 | static void z80_dbus_set_out(void) |
0c5890bb L |
204 | { |
205 | DDR_DB = 0xff; | |
206 | } | |
207 | ||
61bd408c L |
208 | static void z80_reset_active(void) |
209 | { | |
210 | if (reset_polarity) | |
211 | Z80_O_RST = 1; | |
212 | else | |
213 | Z80_O_RST = 0; | |
214 | } | |
215 | ||
216 | static void z80_reset_inactive(void) | |
217 | { | |
218 | if (reset_polarity) | |
219 | Z80_O_RST = 0; | |
220 | else | |
221 | Z80_O_RST = 1; | |
222 | } | |
62f624d3 L |
223 | |
224 | static void z80_reset_pulse(void) | |
225 | { | |
61bd408c | 226 | z80_reset_active(); |
62f624d3 | 227 | _delay_us(10); |
61bd408c | 228 | z80_reset_inactive(); |
62f624d3 L |
229 | } |
230 | ||
231 | ||
0c5890bb L |
232 | void z80_setup_bus(void) |
233 | { | |
a1595a8e L |
234 | ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { |
235 | ||
61bd408c L |
236 | /* /ZRESET: Input, no pullup */ |
237 | DDR_RST &= ~_BV(RST); | |
a1595a8e | 238 | Z80_O_RST = 0; |
0c5890bb | 239 | |
a1595a8e L |
240 | /* /BUSREQ: Output and high */ |
241 | Z80_O_BUSREQ = 1; | |
242 | DDR_BUSREQ |= _BV(BUSREQ); | |
0c5890bb | 243 | |
a1595a8e L |
244 | /* /BUSACK: Input, no pullup */ |
245 | DDR_BUSACK &= ~_BV(BUSACK); | |
246 | P_BUSACK &= ~_BV(BUSACK); | |
0c5890bb | 247 | |
a1595a8e L |
248 | z80_addrbus_set_in(); |
249 | z80_dbus_set_in(); | |
0c5890bb | 250 | |
a1595a8e L |
251 | if (getenv_yesno(PSTR(ENV_SINGLESTEP))) { |
252 | /* /RUN & /STEP: output, /WAIT: input */ | |
72f58822 | 253 | |
a1595a8e L |
254 | PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP); |
255 | DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP); | |
256 | } | |
257 | ||
61bd408c L |
258 | reset_polarity = Z80_I_RST; |
259 | z80_reset_active(); | |
260 | DDR_RST |= _BV(RST); | |
261 | ||
a1595a8e L |
262 | zstate = RESET; |
263 | } | |
ea6971b8 | 264 | |
a1595a8e L |
265 | /* Timer 5 */ |
266 | PRR1 &= ~_BV(PRTIM5); | |
267 | OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */ | |
268 | TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */ | |
269 | TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */ | |
ea6971b8 | 270 | |
0c5890bb L |
271 | } |
272 | ||
f338df2a | 273 | |
62f624d3 | 274 | zstate_t z80_bus_state(void) |
f338df2a L |
275 | { |
276 | return zstate; | |
277 | } | |
278 | ||
62f624d3 L |
279 | |
280 | static void z80_busreq_hpulse(void) | |
0c5890bb | 281 | { |
6035a17b | 282 | z80_dbus_set_in(); |
a1595a8e | 283 | z80_addrbus_set_in(); |
72f58822 | 284 | |
a1595a8e | 285 | #if 0 |
8a7decea | 286 | ATOMIC_BLOCK(ATOMIC_FORCEON) { |
62f624d3 L |
287 | Z80_O_BUSREQ = 1; |
288 | Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ | |
289 | Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ | |
f338df2a | 290 | } |
a1595a8e L |
291 | #endif |
292 | ||
4b0604a4 | 293 | #if 1 |
a1595a8e L |
294 | ATOMIC_BLOCK(ATOMIC_FORCEON) { |
295 | Z80_O_BUSREQ = 1; | |
296 | ||
297 | do { | |
298 | if (Z80_I_BUSACK == 1) { | |
299 | Z80_O_BUSREQ = 0; | |
300 | break; | |
301 | } | |
302 | } while (1); | |
303 | } | |
4b0604a4 | 304 | #endif |
72f58822 | 305 | |
62f624d3 | 306 | if (zstate & ZST_ACQUIRED) { |
ea6971b8 L |
307 | timer = BUS_TO; |
308 | while (Z80_I_BUSACK == 1 && timer) | |
f338df2a | 309 | ; |
ea6971b8 | 310 | if (Z80_I_BUSACK == 0) |
a1595a8e | 311 | z80_addrbus_set_out(); |
f338df2a | 312 | } |
f338df2a L |
313 | } |
314 | ||
f338df2a L |
315 | |
316 | /* | |
f338df2a | 317 | |
ea6971b8 | 318 | + | | | | | |
62f624d3 | 319 | + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | |
ea6971b8 L |
320 | + | | | | | |
321 | + | 0 | 1 | 2 | 3 | | |
322 | Event + | | | | | | |
62f624d3 | 323 | ----------------+---------------+---------------+---------------+---------------+ |
ea6971b8 L |
324 | | | | | | |
325 | Reset | 0 | 0 | 0 | 0 | | |
326 | | | | | | | |
327 | | | | | | | |
328 | Request | 1 | | 3 | | | |
329 | | | | | | | |
330 | | | | | | | |
331 | Release | | 0 | | 2 | | |
332 | | | | | | | |
333 | | | | | | | |
334 | Run | 2 | 3 | | | | |
335 | | | | | | | |
336 | | | | | | | |
337 | Restart | | | 2 | 3 | | |
338 | | | | | | | |
339 | | | | | | | |
340 | M_Cycle | | | | 3 | | |
341 | | | | | | | |
342 | | | | | | | |
62f624d3 | 343 | */ |
f338df2a | 344 | |
62f624d3 | 345 | zstate_t z80_bus_cmd(bus_cmd_t cmd) |
f338df2a | 346 | { |
62f624d3 | 347 | switch (cmd) { |
f338df2a | 348 | |
62f624d3 | 349 | case Reset: |
6035a17b | 350 | z80_dbus_set_in(); |
a1595a8e | 351 | z80_addrbus_set_in(); |
61bd408c | 352 | z80_reset_active(); |
62f624d3 L |
353 | Z80_O_BUSREQ = 1; |
354 | zstate = RESET; | |
f338df2a L |
355 | break; |
356 | ||
62f624d3 L |
357 | case Request: |
358 | switch (zstate) { | |
359 | case RESET: | |
360 | Z80_O_BUSREQ = 0; | |
61bd408c | 361 | z80_reset_inactive(); |
ea6971b8 L |
362 | timer = BUS_TO; |
363 | while (Z80_I_BUSACK == 1 && timer) | |
62f624d3 | 364 | ; |
ea6971b8 | 365 | if (Z80_I_BUSACK == 0) { |
a1595a8e | 366 | z80_addrbus_set_out(); |
ea6971b8 L |
367 | zstate = RESET_AQRD; |
368 | } else { | |
61bd408c | 369 | z80_reset_active(); |
ea6971b8 L |
370 | Z80_O_BUSREQ = 1; |
371 | } | |
62f624d3 L |
372 | break; |
373 | ||
374 | case RUNNING: | |
375 | Z80_O_BUSREQ = 0; | |
ea6971b8 L |
376 | timer = BUS_TO; |
377 | while (Z80_I_BUSACK == 1 && timer) | |
62f624d3 | 378 | ; |
ea6971b8 | 379 | if (Z80_I_BUSACK == 0) { |
a1595a8e | 380 | z80_addrbus_set_out(); |
ea6971b8 L |
381 | zstate = RUNNING_AQRD; |
382 | } else { | |
383 | Z80_O_BUSREQ = 1; | |
384 | } | |
62f624d3 L |
385 | break; |
386 | ||
387 | default: | |
388 | break; | |
389 | } | |
f338df2a | 390 | break; |
f338df2a | 391 | |
62f624d3 L |
392 | case Release: |
393 | switch (zstate) { | |
394 | case RESET_AQRD: | |
6035a17b | 395 | z80_dbus_set_in(); |
a1595a8e | 396 | z80_addrbus_set_in(); |
61bd408c | 397 | z80_reset_active(); |
62f624d3 L |
398 | Z80_O_BUSREQ = 1; |
399 | zstate = RESET; | |
400 | break; | |
401 | case RUNNING_AQRD: | |
6035a17b | 402 | z80_dbus_set_in(); |
a1595a8e | 403 | z80_addrbus_set_in(); |
62f624d3 L |
404 | Z80_O_BUSREQ = 1; |
405 | zstate = RUNNING; | |
406 | break; | |
407 | default: | |
408 | break; | |
409 | } | |
410 | break; | |
f338df2a | 411 | |
62f624d3 L |
412 | case Run: |
413 | switch (zstate) { | |
414 | case RESET: | |
61bd408c | 415 | z80_reset_inactive(); |
62f624d3 L |
416 | zstate = RUNNING; |
417 | break; | |
418 | ||
419 | case RESET_AQRD: | |
6035a17b | 420 | z80_dbus_set_in(); |
a1595a8e | 421 | z80_addrbus_set_in(); |
62f624d3 | 422 | z80_reset_pulse(); |
a1595a8e | 423 | z80_addrbus_set_out(); |
62f624d3 L |
424 | zstate = RUNNING_AQRD; |
425 | break; | |
426 | default: | |
427 | break; | |
428 | } | |
429 | break; | |
f338df2a | 430 | |
62f624d3 L |
431 | case Restart: |
432 | switch (zstate) { | |
433 | case RUNNING: | |
434 | case RUNNING_AQRD: | |
435 | z80_reset_pulse(); | |
436 | break; | |
437 | default: | |
438 | break; | |
439 | } | |
440 | break; | |
f338df2a | 441 | |
62f624d3 L |
442 | case M_Cycle: |
443 | switch (zstate) { | |
444 | case RUNNING_AQRD: | |
ea6971b8 | 445 | z80_busreq_hpulse(); /* TODO: */ |
62f624d3 L |
446 | break; |
447 | default: | |
448 | break; | |
449 | } | |
f338df2a | 450 | } |
62f624d3 | 451 | return zstate; |
9b6b4b31 L |
452 | } |
453 | ||
62f624d3 | 454 | |
9b6b4b31 L |
455 | /*--------------------------------------------------------------------------*/ |
456 | ||
54678798 | 457 | static |
9b6b4b31 L |
458 | //inline __attribute__ ((always_inline)) |
459 | void z80_setaddress(uint32_t addr) | |
460 | { | |
a1595a8e L |
461 | P_ADL = addr; |
462 | P_ADH = (addr & 0xff00) >> 8; | |
463 | PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT; | |
0c5890bb L |
464 | } |
465 | ||
466 | void z80_write(uint32_t addr, uint8_t data) | |
467 | { | |
468 | z80_setaddress(addr); | |
469 | Z80_O_MREQ = 0; | |
6035a17b | 470 | z80_dbus_set_out(); |
9b6b4b31 L |
471 | P_DB = data; |
472 | P_DB = data; | |
473 | Z80_O_WR = 0; | |
0c5890bb L |
474 | Z80_O_WR = 0; |
475 | Z80_O_WR = 1; | |
476 | Z80_O_MREQ = 1; | |
477 | } | |
478 | ||
479 | uint8_t z80_read(uint32_t addr) | |
480 | { | |
481 | uint8_t data; | |
482 | ||
483 | z80_setaddress(addr); | |
484 | Z80_O_MREQ = 0; | |
6035a17b | 485 | z80_dbus_set_in(); |
0c5890bb L |
486 | Z80_O_RD = 0; |
487 | Z80_O_RD = 0; | |
9b6b4b31 | 488 | Z80_O_RD = 0; |
0c5890bb L |
489 | data = PIN_DB; |
490 | Z80_O_RD = 1; | |
491 | Z80_O_MREQ = 1; | |
492 | ||
493 | return data; | |
494 | } | |
495 | ||
496 | ||
497 | void z80_memset(uint32_t addr, uint8_t data, uint32_t length) | |
498 | { | |
6035a17b | 499 | z80_dbus_set_out(); |
0c5890bb | 500 | Z80_O_MREQ = 0; |
ea6971b8 | 501 | P_DB = data; |
0c5890bb L |
502 | while(length--) { |
503 | z80_setaddress(addr++); | |
ea6971b8 L |
504 | Z80_O_WR = 0; |
505 | Z80_O_WR = 0; | |
506 | Z80_O_WR = 1; | |
507 | } | |
508 | Z80_O_MREQ = 1; | |
509 | } | |
510 | ||
511 | void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length) | |
512 | { | |
513 | uint8_t data; | |
514 | ||
515 | z80_dbus_set_out(); | |
516 | Z80_O_MREQ = 0; | |
517 | while(length--) { | |
518 | z80_setaddress(dest++); | |
519 | data = *src++; | |
0c5890bb | 520 | P_DB = data; |
9b6b4b31 L |
521 | P_DB = data; |
522 | Z80_O_WR = 0; | |
0c5890bb L |
523 | Z80_O_WR = 0; |
524 | Z80_O_WR = 1; | |
525 | } | |
526 | Z80_O_MREQ = 1; | |
527 | } | |
528 | ||
ea6971b8 | 529 | void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length) |
0c5890bb L |
530 | { |
531 | uint8_t data; | |
54678798 | 532 | |
6035a17b | 533 | z80_dbus_set_out(); |
0c5890bb L |
534 | Z80_O_MREQ = 0; |
535 | while(length--) { | |
536 | z80_setaddress(dest++); | |
537 | data = *src++; | |
538 | P_DB = data; | |
9b6b4b31 L |
539 | P_DB = data; |
540 | Z80_O_WR = 0; | |
0c5890bb L |
541 | Z80_O_WR = 0; |
542 | Z80_O_WR = 1; | |
543 | } | |
544 | Z80_O_MREQ = 1; | |
545 | } | |
546 | ||
ea6971b8 L |
547 | void z80_read_block (uint8_t *dest, uint32_t src, size_t length) |
548 | { | |
549 | uint8_t data; | |
550 | ||
551 | Z80_O_MREQ = 0; | |
552 | z80_dbus_set_in(); | |
553 | while(length--) { | |
554 | z80_setaddress(src++); | |
555 | Z80_O_RD = 0; | |
556 | Z80_O_RD = 0; | |
557 | Z80_O_RD = 0; | |
558 | data = PIN_DB; | |
559 | Z80_O_RD = 1; | |
560 | *dest++ = data; | |
561 | } | |
562 | Z80_O_MREQ = 1; | |
563 | } | |
564 | ||
565 | ||
0c5890bb L |
566 | /* |
567 | 0179' rx.bs_mask: ds 1 ; (buf_len - 1) | |
568 | 017A' rx.in_idx: ds 1 ; | |
569 | 017B' rx.out_idx: ds 1 ; | |
570 | 017C' rx.buf: ds rx.buf_len ; | |
571 | 018B' rx.buf_end equ $-1 ; last byte (start+len-1) | |
54678798 | 572 | |
0c5890bb L |
573 | 018C' tx.bs_mask: ds 1 ; (buf_len - 1) |
574 | 018D' tx.in_idx: ds 1 ; | |
575 | 018E' tx.out_idx: ds 1 ; | |
576 | 018F' tx.buf: ds tx.buf_len ; | |
577 | 019E' tx.buf_end equ $-1 ; last byte | |
578 | */ | |
579 | ||
580 | ||
581 | typedef struct __attribute__((packed)) { | |
582 | uint8_t mask; | |
583 | uint8_t in_idx; | |
584 | uint8_t out_idx; | |
585 | uint8_t buf[]; | |
586 | } zfifo_t; | |
587 | ||
588 | ||
589 | ||
590 | #define FIFO_BUFSIZE_MASK -3 | |
591 | #define FIFO_INDEX_IN -2 | |
592 | #define FIFO_INDEX_OUT -1 | |
593 | ||
594 | ||
595 | static struct { | |
596 | uint32_t base; | |
597 | uint8_t idx_out, | |
598 | idx_in, | |
599 | mask; | |
600 | } fifo_dsc[NUM_FIFOS]; | |
54678798 | 601 | |
0c5890bb | 602 | |
8a7decea | 603 | void z80_memfifo_init(const fifo_t f, uint32_t addr) |
0c5890bb | 604 | { |
8a7decea | 605 | fifo_dsc[f].base = addr; |
0c5890bb | 606 | |
0c5890bb | 607 | |
bbd45c46 | 608 | if (addr != 0) { |
8a7decea L |
609 | z80_bus_cmd(Request); |
610 | fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK); | |
611 | fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN); | |
612 | fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT); | |
613 | z80_bus_cmd(Release); | |
910e7206 L |
614 | |
615 | if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) { | |
616 | DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n", | |
617 | f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask); | |
618 | } | |
8a7decea | 619 | } |
0c5890bb L |
620 | } |
621 | ||
622 | ||
623 | int z80_memfifo_is_empty(const fifo_t f) | |
624 | { | |
625 | int rc = 1; | |
626 | ||
89adce76 | 627 | if (fifo_dsc[f].base != 0) { |
0c5890bb L |
628 | |
629 | uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; | |
630 | uint8_t idx; | |
631 | ||
62f624d3 | 632 | z80_bus_cmd(Request); |
0c5890bb | 633 | idx = z80_read(adr); |
62f624d3 | 634 | z80_bus_cmd(Release); |
0c5890bb L |
635 | rc = idx == fifo_dsc[f].idx_out; |
636 | } | |
637 | ||
638 | return rc; | |
639 | } | |
640 | ||
641 | int z80_memfifo_is_full(const fifo_t f) | |
642 | { | |
ce47d431 | 643 | int rc = 0; |
54678798 | 644 | |
0c5890bb | 645 | if (fifo_dsc[f].base != 0) { |
62f624d3 | 646 | z80_bus_cmd(Request); |
0c5890bb L |
647 | rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) |
648 | == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); | |
62f624d3 | 649 | z80_bus_cmd(Release); |
0c5890bb L |
650 | } |
651 | return rc; | |
652 | } | |
653 | ||
89adce76 L |
654 | |
655 | uint8_t z80_memfifo_getc_wait(const fifo_t f) | |
0c5890bb L |
656 | { |
657 | uint8_t rc, idx; | |
54678798 | 658 | |
0c5890bb L |
659 | while (z80_memfifo_is_empty(f)) |
660 | ; | |
661 | ||
62f624d3 | 662 | z80_bus_cmd(Request); |
0c5890bb L |
663 | idx = fifo_dsc[f].idx_out; |
664 | rc = z80_read(fifo_dsc[f].base+idx); | |
665 | fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; | |
666 | z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); | |
62f624d3 | 667 | z80_bus_cmd(Release); |
54678798 | 668 | |
0c5890bb L |
669 | return rc; |
670 | } | |
671 | ||
89adce76 L |
672 | int z80_memfifo_getc(const fifo_t f) |
673 | { | |
674 | int rc = -1; | |
675 | ||
676 | if (fifo_dsc[f].base != 0) { | |
677 | uint8_t idx = fifo_dsc[f].idx_out; | |
678 | z80_bus_cmd(Request); | |
679 | if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) { | |
680 | rc = z80_read(fifo_dsc[f].base+idx); | |
681 | fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; | |
682 | z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); | |
683 | } | |
684 | z80_bus_cmd(Release); | |
685 | } | |
686 | ||
687 | return rc; | |
688 | } | |
689 | ||
0c5890bb L |
690 | |
691 | void z80_memfifo_putc(fifo_t f, uint8_t val) | |
692 | { | |
693 | int idx; | |
54678798 | 694 | |
0c5890bb L |
695 | while (z80_memfifo_is_full(f)) |
696 | ; | |
697 | ||
62f624d3 | 698 | z80_bus_cmd(Request); |
0c5890bb L |
699 | idx = fifo_dsc[f].idx_in; |
700 | z80_write(fifo_dsc[f].base+idx, val); | |
701 | fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; | |
702 | z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); | |
62f624d3 | 703 | z80_bus_cmd(Release); |
0c5890bb | 704 | } |