Continue Integration

diff --git a/z180/Tupfile b/z180/Tupfile
index 3105c94fde902e6c6ec22c111e9aff03a340b888..1becb049f93921145dc500e4606a17dca45e52b4 100644 (file)
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -38,7 +38,8 @@ grep -q '^ 0 Error(s) Detected' ${OUTPUT}; ERROR=$?;\
 rm -f ${OUTPUT}; exit ${ERROR} \
 |> %B.rel | %B.lst 
 
-!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+#!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) %f |> | %O.map
 
 #ifndef DEBUG
 

diff --git a/z180/bioscio.180 b/z180/bioscio.180
index 5ec55c69b07e44d1eefe8392e2df6e5fe998f6e4..b0fd4daa98fd7b2b513132cf4e0acd73624d0836 100644 (file)
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -65,7 +65,8 @@ c$init$loop:
        dec     c\r
        jp      p,c$init$loop\r
 \r
-       ld      hl,1000000000000000b    ; assign console to HOST\r
+;      ld      hl,1000000000000000b    ; assign console to HOST\r
+       ld      hl,0100000000000000b    ; assign console to ASCI1\r
        ld      (@civec),hl\r
        ld      (@covec),hl\r
        ld      hl,0000000000000000b    ; assign auxiliary to nothing\r

diff --git a/z180/ddtz.180 b/z180/ddtz.180
index 5f8bf20bfb969e87cd1b33262366aa2e9bb827b9..490b8293cc052f63b20ddc3955768b9f0baa9a64 100644 (file)
--- a/z180/ddtz.180
+++ b/z180/ddtz.180
@@ -6130,7 +6130,8 @@ l28dbh:
 ;------------------------------------------\r
 \r
 vartab:\r
-       dseg\r
+;      dseg\r
+       cseg\r
 ddtram:                                \r
 ;todo:\r
 ; The following 2 params are changeable by user.\r

diff --git a/z180/init.180 b/z180/init.180
index 9edeaf216f33b2395baafcda06fca5348b4faeb1..16ca852639b6bc4460bc3335b26cec14250b5fd0 100644 (file)
--- a/z180/init.180
+++ b/z180/init.180
@@ -4,6 +4,7 @@
        extrn ddtz,bpent\r
        extrn $stack\r
        extrn charini,?const,?conin\r
+       extrn ?cono,?conos\r
 \r
        extrn romend\r
 \r
@@ -11,32 +12,35 @@
        global  isv_sw\r
 \r
        include config.inc\r
-       include z180reg.inc\r
-       include z180.lib\r
+       if CPU_Z180\r
+        include        z180reg.inc\r
+        include z180.lib\r
+       endif\r
 \r
-;CR    equ     0dh\r
 \r
 \r
 \r
 ;----------------------------------------------------------------------\r
 \r
        cseg\r
+romstart equ   $\r
 \r
+       org     romstart+0\r
        jp start\r
 \r
+iobyte:        db      0\r
 ; restart vectors\r
 \r
 rsti   defl    1\r
        rept    7\r
-        db 0, 0, 0, 0, 0\r
+       org     8*rsti + romstart\r
         jp bpent\r
 rsti    defl rsti+1\r
        endm\r
-        db 0, 0, 0, 0, 0\r
 \r
 ;----------------------------------------------------------------------\r
        \r
-       ;org    40h\r
+       org     romstart+40h\r
 \r
        dw      0\r
        db      0\r
@@ -48,6 +52,36 @@ $crom:        defb c$rom             ;
         db     0               ;\r
        endif\r
 \r
+INIWAITS defl  CWAITIO\r
+       if      ROMSYS\r
+INIWAITS defl  INIWAITS+CWAITROM\r
+       endif\r
+\r
+hwini0:\r
+       if CPU_Z180\r
+\r
+        db     3               ;count\r
+        db     rcr,CREFSH      ;configure DRAM refresh\r
+        db     dcntl,INIWAITS  ;wait states\r
+        db     cbar,SYS$CBAR\r
+       else\r
+        db     0\r
+       endif\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       org     romstart+50h\r
+start:\r
+       jp      cstart\r
+       jp      wstart\r
+       jp      ?const\r
+       jp      ?conin\r
+       jp      ?cono\r
+       jp      ?conos\r
+       jp      charini\r
+\r
+;----------------------------------------------------------------------\r
+\r
 dmclrt:                                ;clear ram per dma\r
        db      dmct_e-dmclrt-2 ;\r
        db      sar0l           ;first port\r
@@ -59,22 +93,9 @@ nullbyte:
        dw      0-romend        ;count (64k)\r
 dmct_e:\r
 \r
-INIWAITS defl  CWAITIO\r
-       if      ROMSYS\r
-INIWAITS defl  INIWAITS+CWAITROM\r
-       endif\r
-\r
-hwini0:\r
-       db      3               ;count\r
-       db      rcr,CREFSH      ;configure DRAM refresh\r
-       db      dcntl,INIWAITS  ;wait states\r
-       db      cbar,SYS$CBAR\r
+cstart:\r
+       if CPU_Z180\r
 \r
-;----------------------------------------------------------------------\r
-\r
-start:\r
-       ld      (tmpstack),sp\r
-       ld      sp,tmpstack\r
        push af\r
        in0 a,(itc)             ;Illegal opcode trap?\r
        jp m,??st01\r
@@ -82,10 +103,10 @@ start:
        jr z,??st02             ;    yes, harware reset\r
 \r
 ??st01:\r
+; TODO: SYS$CBR\r
        ld      a,(syscbr)\r
        out0    (cbr),a\r
        pop af                  ;restore registers\r
-       ld      sp,(tmpstack)   ;\r
        jp bpent                ;\r
 \r
 ??st02:\r
@@ -99,9 +120,16 @@ start:
        out0    (ccr),a\r
 ;      ld      a,M_X2CM        ;X2 Clock Multiplier\r
 ;      out0    (cmr),a\r
+       else\r
+       di\r
+       xor     a\r
+       ld      (@cbnk),a\r
+       endif\r
 \r
 ; search warm start mark\r
 \r
+       if CPU_Z180\r
+\r
        ld ix,mark_55AA         ;00b8   ; top of common area\r
        ld a,SYS$CBAR           ;\r
        out0 (cbar),a           ;\r
@@ -127,11 +155,28 @@ swsm_l:
        ld sp,$stack            ;00e0   mark found, check\r
        call checkcrc_alv       ;00e3\r
        jp z,wstart             ;00e6   check ok,\r
-\r
+       else\r
+       ld ix,mark_55AA         ; top of common area\r
+       ld a,0aah               ;\r
+       cp (ix+000h)            ;\r
+       jr nz,kstart            ;\r
+       cp (ix+002h)            ;\r
+       jr nz,kstart            ;\r
+       cpl                     ;\r
+       cp (ix+001h)            ;\r
+       jr nz,kstart            ;\r
+       cp (ix+003h)            ;\r
+       jr nz,kstart            ;\r
+       ld sp,$stack            ; mark found, check\r
+       jp z,wstart             ; check ok,\r
+       endif\r
 ;\r
 ; ram not ok, initialize    --  kstart --\r
 \r
 kstart:\r
+       if CPU_Z180\r
+       \r
+       if 0\r
 \r
        ld      a,088h          ;00e9   0000-7fff: common 0\r
        out0    (cbar),a        ;00eb   8000-ffff: common 1\r
@@ -168,6 +213,14 @@ kstart:
        add     a,8\r
        cp      078h            ;       stop at 078000\r
        jr      nz,??cp_0\r
+       \r
+       else\r
+       \r
+       ld      de,0ffffh\r
+       ld      a,070h\r
+       out0    (cbr),a\r
+       \r
+       endif\r
 \r
 ;\r
 ;  ram test found 1 or more error free blocks (32k)\r
@@ -194,10 +247,15 @@ alloc:
        out0    (cbr),c         ;01de\r
        ld      a,c\r
        ld      (syscbr),a\r
+       endif\r
        ld      sp,$stack       ;01e1\r
 \r
 ; Clear RAM using DMA0\r
 \r
+       if CPU_Z180\r
+\r
+       if 0\r
+       \r
        ld      hl,dmclrt       ;load DMA registers\r
        call    io.ini.m\r
        ld      a,0cbh          ;01ef   dst +1, src fixed, burst\r
@@ -208,6 +266,8 @@ alloc:
 ??cl_1:\r
        out0    (dstat),a       ;01f9   clear (up to) 64k\r
        djnz    ??cl_1          ;       end of RAM?\r
+       \r
+       endif\r
 \r
 ; Init bank manager\r
 \r
@@ -271,24 +331,29 @@ l024ah:
        ld      c,l             ;\r
        or      a               ;\r
        call    z,sub_04b5h     ;\r
+       endif\r
 \r
        ld      hl,055AAh       ;set warm start mark\r
        ld      (mark_55AA),hl  ;\r
        ld      (mark_55AA+2),hl;\r
 \r
 ;\r
-; crc ok       --  wstart  --\r
+; (crc ok)      --  wstart  --\r
 ;\r
 wstart:\r
        call    sysram_init     ;027f\r
        call    ivtab_init\r
-\r
-       call    prt0_init\r
+       if CPU_Z180\r
+        call   prt0_init\r
+       endif\r
 \r
        call    charini\r
-\r
        call    bufferinit\r
 \r
+       iff CPU_Z180\r
+        ld     a,0\r
+        call   selbnk\r
+       endif\r
 \r
 \r
        im 2                    ;?030e\r
@@ -299,15 +364,19 @@ wstart:
        or a                    ;028a\r
        call nz,?conin          ;028d\r
 \r
-       ld a,(banktab)          ;\r
-       ld e,a                  ;\r
+       if CPU_Z180\r
+        ld a,(banktab)         ;\r
+        ld e,a                 ;\r
+       else\r
+; TODO:\r
+       endif\r
        jp ddtz                 ;0290\r
 \r
 \r
-       ds      8\r
-tmpstack:\r
-       dw      2\r
+       if CPU_Z180\r
+; TODO: SYS$CBR\r
 syscbr:        db      1\r
+       endif\r
 \r
 ;\r
 ;----------------------------------------------------------------------\r
@@ -376,6 +445,7 @@ endif
 \r
 \r
 bufferinit:\r
+       if CPU_Z180\r
        call     msginit\r
 \r
        ld      hl,buffers\r
@@ -392,15 +462,15 @@ bfi_1:
 \r
        or      a\r
        jr      nz,bfi_2\r
-       in0     a,cbr\r
-       call    log2phys\r
+;      in0     a,(cbr)\r
+       call    hw_log2phys\r
        ld      (40h+0),hl\r
        ld      (40h+2),a\r
        out0    (AVRINT5),a\r
        jr      bfi_3   \r
 bfi_2:\r
-       in0     a,cbr\r
-       call    log2phys\r
+;      in0     a,(cbr)\r
+       call    hw_log2phys\r
        ld      (bufdat+1),hl\r
        ld      (bufdat+3),a\r
        ld      hl,inimsg\r
@@ -409,6 +479,45 @@ bfi_3:
        pop     hl\r
        djnz    bfi_1\r
        ret\r
+       else\r
+       call     msginit\r
+\r
+       ld      hl,buffers\r
+       ld      b,buftablen\r
+bfi_1:\r
+       ld      a,(hl)\r
+       inc     hl\r
+       ld      (bufdat+0),a\r
+       ld      e,(hl)\r
+       inc     hl\r
+       ld      d,(hl)\r
+       inc     hl\r
+       ex      de,hl\r
+\r
+       or      a\r
+       jr      nz,bfi_2\r
+\r
+       ld      a,(@cbnk)\r
+       call    bnk2phys\r
+\r
+       ld      (40h+0),hl\r
+       ld      (40h+2),a\r
+       out     (AVRINT5),a\r
+       jr      bfi_3\r
+bfi_2:\r
+\r
+       ld      a,(@cbnk)\r
+       call    bnk2phys\r
+\r
+       ld      (bufdat+1),hl\r
+       ld      (bufdat+3),a\r
+       ld      hl,inimsg\r
+       call    msg.sout\r
+bfi_3:\r
+       ex      de,hl\r
+       djnz    bfi_1\r
+       ret\r
+       endif\r
 \r
 buffers:\r
        db      0\r
@@ -451,7 +560,9 @@ ivtab_init:
        ld      hl,ivtab        ;\r
        ld      a,h             ;\r
        ld      i,a             ;\r
+       if CPU_Z180\r
        out0    (il),l          ;\r
+       endif\r
 \r
 ; Let all vectors point to spurious int routines.\r
 \r
@@ -469,6 +580,7 @@ ivt_i1:
 \r
 ;----------------------------------------------------------------------\r
 \r
+       if CPU_Z180\r
 prt0_init:\r
        ld      a,i\r
        ld      h,a\r
@@ -490,6 +602,7 @@ prt0itab:
        dw      PRT_TC10MS\r
        db      M_TIE0+M_TDE0   ;enable timer 0 interrupt and down count.\r
 prt0it_e:\r
+       endif\r
 \r
 \r
 ;\r
@@ -498,9 +611,13 @@ prt0it_e:
 \r
 io.ini:\r
        push    bc\r
+       if CPU_Z180\r
+\r
        ld      b,0             ;high byte port adress\r
        ld      a,(hl)          ;count\r
        inc     hl\r
+       or      a\r
+       jr      z,ioi_e\r
 ioi_1:\r
        ld      c,(hl)          ;port address\r
        inc     hl\r
@@ -508,9 +625,24 @@ ioi_1:
        inc     b               ;outi decrements b\r
        dec     a\r
        jr      nz,ioi_1\r
+\r
+       else\r
+       jr      ioi_nxt\r
+ioi_l:\r
+       ld      c,(hl)          ;port address\r
+       inc     hl\r
+       otir\r
+ioi_nxt:\r
+       ld      b,(hl)          ;count\r
+       inc     hl\r
+       inc     b\r
+       djnz    ioi_l\r
+       endif\r
+ioi_e: \r
        pop     bc\r
        ret\r
 \r
+       if CPU_Z180\r
 io.ini.m:\r
        push    bc\r
        ld      b,(hl)\r
@@ -520,13 +652,17 @@ io.ini.m:
        otimr\r
        pop     bc\r
        ret\r
+       endif\r
 \r
 io.ini.l:\r
 ;\r
 \r
+;\r
 ;----------------------------------------------------------------------\r
 ;\r
 \r
+       if CPU_Z180\r
+\r
 ; compute crc\r
 ; hl: start adr\r
 ; bc: len\r
@@ -802,6 +938,61 @@ log2phys:
        pop     bc              ;\r
        ret                     ;\r
 \r
+;--------------------------------------------------------------\r
+;\r
+; de: Log. Address\r
+; \r
+;\r
+; OP: ahl = (bankbase<<12) + (d<<8) + e\r
+;\r
+;out ahl: Phys. (linear) Address\r
+\r
+\r
+hw_log2phys:\r
+       push    bc              ;\r
+       in0     c,(cbar)\r
+       ld      a,d\r
+       or      00fh\r
+       cp      c\r
+       jr      c,hlp_1\r
+       in0     c,(cbr)\r
+       jr      hlp_e\r
+hlp_1:\r
+       ld      b,16\r
+       mlt     bc\r
+       ld      a,d\r
+       cp      c\r
+       ld      c,0\r
+       jr      c,hlp_e\r
+       in0     c,(bbr)\r
+hlp_e: \r
+       ld      b,16            ;\r
+       mlt     bc              ;bc = a<<4\r
+       ld      l,d             ;\r
+       ld      h,0             ;\r
+       add     hl,bc           ;bc + d == a<<4 + d\r
+       ld      a,h             ;\r
+       ld      h,l             ;\r
+       ld      l,e             ;\r
+       pop     bc              ;\r
+       ret                     ;\r
+\r
+       else\r
+\r
+;\r
+;----------------------------------------------------------------------\r
+;\r
+\r
+bnk2phys:\r
+       sla     h\r
+       jr      nc,b2p_1                ;A15=1 --> common\r
+       ld      a,3\r
+b2p_1:\r
+       srl     a\r
+       rr      h\r
+       ret\r
+\r
+       endif\r
 \r
 ;--------------------------------------------------------------\r
 ;\r
@@ -868,6 +1059,7 @@ jphl:
 \r
 ; ---------------------------------------------------------\r
 \r
+       if CPU_Z180\r
 \r
 iprt0:\r
        push    af\r
@@ -890,6 +1082,8 @@ iprt_1:
        ei\r
        ret\r
 \r
+       endif\r
+\r
 ; ---------------------------------------------------------\r
 \r
 sp.int0:\r
@@ -915,6 +1109,160 @@ sp.i.1:
 ;      out     (80h),a\r
        halt\r
 \r
+; ---------------------------------------------------------\r
+\r
+       iff CPU_Z180\r
+\r
+; Get IFF2\r
+; This routine may not be loaded in page zero\r
+;\r
+; return Carry clear, if INTs are enabled.\r
+;\r
+       global getiff\r
+getiff:\r
+       xor     a               ;clear accu and carry\r
+       push    af              ;stack bottom := 00xxh\r
+       pop     af\r
+       ld      a,i             ;P flag := IFF2\r
+       ret     pe              ;exit carry clear, if enabled\r
+       dec     sp\r
+       dec     sp              ;has stack bottom been overwritten?\r
+       pop     af\r
+       and     a               ;if not 00xxh, INTs were\r
+       ret     nz              ;actually enabled\r
+       scf                     ;Otherwise, they really are disabled\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       global  selbnk\r
+\r
+; a: bank (0..2)\r
+\r
+selbnk:\r
+       push    bc\r
+       ld      c,a\r
+       call    getiff\r
+       push    af\r
+\r
+       ld      a,c\r
+       di\r
+       ld      (@cbnk),a\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio0),a\r
+\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       pop     af\r
+       pop     bc\r
+       ret     c                       ;INTs were disabled\r
+       ei\r
+       ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+; c: bank (0..2)\r
+\r
+       if 0\r
+\r
+selbnk:\r
+       ld      a,(@cbnk)\r
+       xor     c\r
+       and     3\r
+       ret     z               ;no change\r
+\r
+       call    getiff\r
+       push    af\r
+       ld      a,c\r
+       di\r
+       ld      (@cbnk),a\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio0),a\r
+\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       pop     af\r
+       ret     nc                      ;INTs were disabled\r
+       ei\r
+       ret\r
+\r
+       endif\r
+\r
+;----------------------------------------------------------------------\r
+\r
+       if 0\r
+       ex      af,af'\r
+       push    af\r
+       ex      af,af'\r
+\r
+       rra\r
+       jr      nc,stbk1\r
+       ex      af,af'\r
+       ld      a,5\r
+       out     (SIOAC),a\r
+       ld      a,(mm_sio0)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOAC),a\r
+       ld      (mm_sio1),a\r
+       ex      af,af'\r
+\r
+stbk1:\r
+       rra\r
+       jr      nc,stbk2\r
+       ex      af,af'\r
+       ld      a,5\r
+       out     (SIOBC),a\r
+       ld      a,(mm_sio1)\r
+       rla\r
+       srl     c\r
+       rra\r
+       out     (SIOBC),a\r
+       ld      (mm_sio1),a\r
+       ex      af,af'\r
+\r
+stbk2:\r
+       endif\r
+\r
+       global  @cbnk\r
+       global  mm_sio0, mm_sio1\r
+\r
+@cbnk: db      0               ; current bank (0..2)\r
+mm_sio0:\r
+       ds      1\r
+mm_sio1:\r
+       ds      1\r
+\r
+\r
+       endif\r
+\r
+;----------------------------------------------------------------------\r
+\r
 curph  defl    $\r
        .dephase\r
 sysrame:\r
@@ -925,6 +1273,8 @@ tim_s:     dw      0
 \r
 ;-----------------------------------------------------\r
 \r
+       if CPU_Z180\r
+\r
        dseg\r
 \r
        ds      1\r
@@ -941,6 +1291,8 @@ crc_len    equ     $-banktabsys
 crc_memalv:\r
        ds      2       ;\r
 \r
+       endif\r
+\r
        cseg\r
 \r
        ;.phase 0ffc0h\r