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Version 2.9.7: added port to to ESP8266 and TEENSY, added PANASONIC protocol, added...
[irmp.git] / irsnd.c
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4225a882 1/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
2 * @file irsnd.c\r
3 *\r
0834784c 4 * Copyright (c) 2010-2015 Frank Meyer - frank(at)fli4l.de\r
4225a882 5 *\r
622f5f59 6 * Supported AVR mikrocontrollers:\r
7644ac04 7 *\r
21a4e0ee 8 * ATtiny87, ATtiny167\r
476267f4 9 * ATtiny45, ATtiny85\r
2ac088b2 10 * ATtiny44 ATtiny84\r
7644ac04 11 * ATmega8, ATmega16, ATmega32\r
12 * ATmega162\r
e664a9f3 13 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P\r
7644ac04 14 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r
15 *\r
df24bb50 16 * $Id: irsnd.c,v 1.97 2015/11/18 08:27:50 fm Exp $\r
5481e9cd 17 *\r
4225a882 18 * This program is free software; you can redistribute it and/or modify\r
19 * it under the terms of the GNU General Public License as published by\r
20 * the Free Software Foundation; either version 2 of the License, or\r
21 * (at your option) any later version.\r
22 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
23 */\r
24\r
4225a882 25#include "irsnd.h"\r
26\r
a03ad359 27#ifndef F_CPU\r
28# error F_CPU unkown\r
29#endif\r
30\r
1f54e86c 31/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
32 * ATtiny pin definition of OC0A / OC0B\r
33 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B\r
34 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
35 */\r
2ac088b2 36#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7\r
08f2dd9d 37# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 38# define IRSND_PORT_LETTER B\r
39# define IRSND_BIT_NUMBER 2\r
08f2dd9d 40# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 41# define IRSND_PORT_LETTER A\r
42# define IRSND_BIT_NUMBER 7\r
08f2dd9d 43# else\r
44# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
45# endif // IRSND_OCx\r
ad4d3d41 46\r
08f2dd9d 47#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1\r
48# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 49# define IRSND_PORT_LETTER B\r
50# define IRSND_BIT_NUMBER 0\r
08f2dd9d 51# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 52# define IRSND_PORT_LETTER B\r
53# define IRSND_BIT_NUMBER 1\r
08f2dd9d 54# else\r
55# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
56# endif // IRSND_OCx\r
ad4d3d41 57\r
21a4e0ee 58#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2\r
90387f65 59# if IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 60# define IRSND_PORT_LETTER A\r
61# define IRSND_BIT_NUMBER 2\r
90387f65 62# else\r
63# error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h\r
64# endif // IRSND_OCx\r
ad4d3d41 65\r
08f2dd9d 66#elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3\r
67# if IRSND_OCx == IRSND_OC2 // OC0A\r
f874da09 68# define IRSND_PORT_LETTER B\r
69# define IRSND_BIT_NUMBER 3\r
08f2dd9d 70# else\r
71# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
72# endif // IRSND_OCx\r
73#elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC2 = PD7\r
74# if IRSND_OCx == IRSND_OC2 // OC2\r
f874da09 75# define IRSND_PORT_LETTER D\r
76# define IRSND_BIT_NUMBER 7\r
08f2dd9d 77# else\r
78# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
79# endif // IRSND_OCx\r
ad4d3d41 80\r
08f2dd9d 81#elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0\r
82# if IRSND_OCx == IRSND_OC2 // OC2\r
f874da09 83# define IRSND_PORT_LETTER B\r
84# define IRSND_BIT_NUMBER 1\r
08f2dd9d 85# elif IRSND_OCx == IRSND_OC0 // OC0\r
f874da09 86# define IRSND_PORT_LETTER B\r
87# define IRSND_BIT_NUMBER 0\r
08f2dd9d 88# else\r
89# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r
90# endif // IRSND_OCx\r
ad4d3d41 91\r
f50e01e7 92#elif defined (__AVR_ATmega164__) \\r
93 || defined (__AVR_ATmega324__) \\r
94 || defined (__AVR_ATmega644__) \\r
95 || defined (__AVR_ATmega644P__) \\r
0f700c8e 96 || defined (__AVR_ATmega1284__) \\r
08f2dd9d 97 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4\r
98# if IRSND_OCx == IRSND_OC2A // OC2A\r
f874da09 99# define IRSND_PORT_LETTER D\r
100# define IRSND_BIT_NUMBER 7\r
08f2dd9d 101# elif IRSND_OCx == IRSND_OC2B // OC2B\r
f874da09 102# define IRSND_PORT_LETTER D\r
103# define IRSND_BIT_NUMBER 6\r
08f2dd9d 104# elif IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 105# define IRSND_PORT_LETTER B\r
106# define IRSND_BIT_NUMBER 3\r
08f2dd9d 107# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 108# define IRSND_PORT_LETTER B\r
109# define IRSND_BIT_NUMBER 4\r
08f2dd9d 110# else\r
111# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
112# endif // IRSND_OCx\r
ad4d3d41 113\r
f50e01e7 114#elif defined (__AVR_ATmega48__) \\r
115 || defined (__AVR_ATmega88__) \\r
7644ac04 116 || defined (__AVR_ATmega88P__) \\r
f50e01e7 117 || defined (__AVR_ATmega168__) \\r
1f54e86c 118 || defined (__AVR_ATmega168P__) \\r
08f2dd9d 119 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5\r
120# if IRSND_OCx == IRSND_OC2A // OC2A\r
f874da09 121# define IRSND_PORT_LETTER B\r
122# define IRSND_BIT_NUMBER 3\r
08f2dd9d 123# elif IRSND_OCx == IRSND_OC2B // OC2B\r
f874da09 124# define IRSND_PORT_LETTER D\r
125# define IRSND_BIT_NUMBER 3\r
08f2dd9d 126# elif IRSND_OCx == IRSND_OC0A // OC0A\r
f874da09 127# define IRSND_PORT_LETTER D\r
128# define IRSND_BIT_NUMBER 6\r
08f2dd9d 129# elif IRSND_OCx == IRSND_OC0B // OC0B\r
f874da09 130# define IRSND_PORT_LETTER D\r
131# define IRSND_BIT_NUMBER 5\r
08f2dd9d 132# else\r
133# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
134# endif // IRSND_OCx\r
ad4d3d41 135\r
f874da09 136#elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2\r
08f2dd9d 137# if IRSND_OCx == IRSND_OC0 \r
f874da09 138# define IRSND_PORT_LETTER B\r
139# define IRSND_BIT_NUMBER 0\r
08f2dd9d 140# elif IRSND_OCx == IRSND_OC1A \r
f874da09 141# define IRSND_PORT_LETTER D\r
142# define IRSND_BIT_NUMBER 5\r
08f2dd9d 143# elif IRSND_OCx == IRSND_OC1B \r
f874da09 144# define IRSND_PORT_LETTER E\r
145# define IRSND_BIT_NUMBER 2\r
ad4d3d41 146# endif // IRSND_OCx\r
147\r
c2b70f0b 148#elif defined (__AVR_XMEGA__) // ATxmega\r
ad4d3d41 149# if IRSND_OCx == IRSND_XMEGA_OC0A \r
150# define IRSND_BIT_NUMBER 0\r
151# elif IRSND_OCx == IRSND_XMEGA_OC0B\r
152# define IRSND_BIT_NUMBER 1\r
153# elif IRSND_OCx == IRSND_XMEGA_OC0C\r
154# define IRSND_BIT_NUMBER 2\r
155# elif IRSND_OCx == IRSND_XMEGA_OC0D\r
156# define IRSND_BIT_NUMBER 3\r
157# elif IRSND_OCx == IRSND_XMEGA_OC1A\r
158# define IRSND_BIT_NUMBER 4\r
159# elif IRSND_OCx == IRSND_XMEGA_OC1B\r
160# define IRSND_BIT_NUMBER 5\r
08f2dd9d 161# else\r
c2b70f0b 162# error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h\r
08f2dd9d 163# endif // IRSND_OCx\r
ad4d3d41 164\r
9c86ff1a 165#elif defined (PIC_C18) //Microchip C18 compiler\r
166 //Nothing here to do here -> See irsndconfig.h\r
08f2dd9d 167#elif defined (ARM_STM32) //STM32\r
168 //Nothing here to do here -> See irsndconfig.h\r
df24bb50 169#elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3\r
95b27043 170# if !digitalPinHasPWM(IRSND_PIN)\r
171# error need pin with PWM output.\r
172# endif\r
f50e01e7 173#else\r
08f2dd9d 174# if !defined (unix) && !defined (WIN32)\r
175# error mikrocontroller not defined, please fill in definitions here.\r
176# endif // unix, WIN32\r
f50e01e7 177#endif // __AVR...\r
178\r
ad4d3d41 179#if defined(__AVR_XMEGA__)\r
180# define _CONCAT(a,b) a##b\r
181# define CONCAT(a,b) _CONCAT(a,b)\r
182# define IRSND_PORT IRSND_PORT_PRE.OUT\r
22a5040e 183# define IRSND_DDR IRSND_PORT_PRE.DIR\r
184# define IRSND_PIN IRSND_PORT_PRE.IN\r
ad4d3d41 185# define IRSND_BIT IRSND_BIT_NUMBER\r
ad4d3d41 186#elif defined(ATMEL_AVR)\r
f874da09 187# define _CONCAT(a,b) a##b\r
188# define CONCAT(a,b) _CONCAT(a,b)\r
189# define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)\r
190# define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)\r
191# define IRSND_BIT IRSND_BIT_NUMBER\r
192#endif\r
193\r
9405f84a 194#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
9c86ff1a 195 typedef uint16_t IRSND_PAUSE_LEN;\r
9405f84a 196#else\r
9c86ff1a 197 typedef uint8_t IRSND_PAUSE_LEN;\r
9405f84a 198#endif\r
199\r
f50e01e7 200/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
201 * IR timings\r
202 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
203 */\r
4225a882 204#define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)\r
205#define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)\r
206#define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)\r
207#define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)\r
208#define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)\r
9c07687e 209#define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
210#define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 211\r
212#define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)\r
213#define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)\r
a7054daf 214#define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
4225a882 215#define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)\r
216#define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)\r
217#define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)\r
9c07687e 218#define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 219\r
220#define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)\r
221#define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)\r
222#define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)\r
223#define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)\r
224#define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)\r
9c07687e 225#define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 226\r
9c07687e 227#define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
228#define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 229\r
ac8504f8 230#define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
231#define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
232\r
4225a882 233#define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)\r
234#define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)\r
235#define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)\r
236#define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)\r
237#define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)\r
9c07687e 238#define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 239\r
770a1a9d 240#define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)\r
241#define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)\r
242#define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)\r
243#define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)\r
244#define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)\r
9c07687e 245#define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
246#define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
770a1a9d 247\r
95b27043 248#define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)\r
249#define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)\r
250#define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)\r
251#define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)\r
252#define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)\r
253#define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
254#define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
255\r
4225a882 256#define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)\r
257#define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)\r
258#define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)\r
259#define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)\r
260#define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)\r
9c07687e 261#define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 262\r
263#define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
264#define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
9c07687e 265#define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 266\r
267#define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)\r
268#define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)\r
4225a882 269#define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)\r
95b27043 270#define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)\r
271#define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)\r
9c07687e 272#define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 273\r
274#define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)\r
275#define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)\r
276#define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)\r
9c07687e 277#define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
278#define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 279\r
beda975f 280#define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)\r
281#define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)\r
282#define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)\r
9c07687e 283#define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
284#define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
beda975f 285\r
4225a882 286#define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)\r
287#define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)\r
288#define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)\r
289#define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)\r
290#define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)\r
9c07687e 291#define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
292\r
293#define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)\r
294#define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)\r
295#define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)\r
296#define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)\r
297#define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)\r
298#define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
299#define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 300\r
95b27043 301#define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)\r
302#define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)\r
303#define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)\r
304#define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)\r
305#define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)\r
306#define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
307#define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
308\r
4225a882 309#define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)\r
310#define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)\r
311#define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)\r
312#define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)\r
313#define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)\r
314#define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)\r
9c07687e 315#define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
316#define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
4225a882 317\r
0715cf5e 318#define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)\r
319#define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)\r
320#define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)\r
321#define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)\r
322#define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)\r
323#define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)\r
324#define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
325#define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
326\r
15dd9c32 327#define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)\r
328#define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)\r
329#define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)\r
330#define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)\r
331#define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)\r
332#define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)\r
9c07687e 333#define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
334#define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
15dd9c32 335\r
5481e9cd 336#define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)\r
337#define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)\r
338#define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)\r
339#define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)\r
340#define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)\r
341#define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)\r
342#define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)\r
343#define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)\r
344#define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)\r
345#define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)\r
346#define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)\r
9c07687e 347#define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5481e9cd 348\r
9c86ff1a 349#define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)\r
350#define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)\r
9c07687e 351#define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
352#define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
89e8cafb 353#define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
a7054daf 354\r
9c07687e 355#define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!\r
a48187fa 356\r
02ccdb69 357#define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
358#define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
9c07687e 359#define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
5b437ff6 360\r
cb93f9e9 361#define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
362#define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)\r
363#define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
364#define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)\r
9c07687e 365#define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
cb93f9e9 366\r
08f2dd9d 367#ifdef PIC_C18 // PIC C18\r
368# define IRSND_FREQ_TYPE uint8_t\r
369# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
370# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
371# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
372# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
373# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
374# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
375# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)\r
376#elif defined (ARM_STM32) // STM32\r
377# define IRSND_FREQ_TYPE uint32_t\r
378# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
379# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
380# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
381# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
382# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
383# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
384# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
df24bb50 385#elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
95b27043 386# define IRSND_FREQ_TYPE float\r
387# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)\r
388# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)\r
389# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)\r
390# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)\r
391# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)\r
392# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
393# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
08f2dd9d 394#else // AVR\r
a03ad359 395# if F_CPU >= 16000000L\r
396# define AVR_PRESCALER 8\r
397# else\r
398# define AVR_PRESCALER 1\r
399# endif\r
08f2dd9d 400# define IRSND_FREQ_TYPE uint8_t\r
a03ad359 401# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)\r
402# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)\r
403# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)\r
404# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)\r
405# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)\r
406# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)\r
407# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)\r
9c86ff1a 408#endif\r
4225a882 409\r
48664931 410#define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)\r
411#define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)\r
412#define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)\r
413#define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)\r
414#define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)\r
415#define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
b5ea7869 416\r
c7c9a4a1 417#define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)\r
418#define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)\r
419#define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)\r
420#define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)\r
421#define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)\r
422#define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
423\r
c7a47e89 424#define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)\r
425#define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)\r
426#define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
427#define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)\r
428#define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)\r
429#define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)\r
430#define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
431\r
9405f84a 432#define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)\r
433#define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)\r
434#define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
435#define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)\r
436#define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)\r
437#define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)\r
f50e01e7 438#define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
439\r
440#define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)\r
441#define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)\r
442#define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
443#define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)\r
444#define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)\r
445#define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)\r
446#define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
9405f84a 447\r
fa09ce10 448#define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)\r
449#define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)\r
450#define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)\r
451#define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)\r
452#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
453#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
454\r
c9b6916a 455#define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)\r
456#define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)\r
457#define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)\r
458#define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)\r
459#define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)\r
460#define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)\r
461#define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
462\r
003c1008 463#define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)\r
464#define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)\r
465#define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
466#define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)\r
467#define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)\r
468#define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)\r
469#define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
470\r
43c535be 471#define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)\r
472#define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)\r
473#define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)\r
474#define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)\r
475#define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)\r
476#define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)\r
477#define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
478\r
9c86ff1a 479static volatile uint8_t irsnd_busy = 0;\r
480static volatile uint8_t irsnd_protocol = 0;\r
43c535be 481static volatile uint8_t irsnd_buffer[9] = {0};\r
9c86ff1a 482static volatile uint8_t irsnd_repeat = 0;\r
4225a882 483static volatile uint8_t irsnd_is_on = FALSE;\r
484\r
f50e01e7 485#if IRSND_USE_CALLBACK == 1\r
486static void (*irsnd_callback_ptr) (uint8_t);\r
487#endif // IRSND_USE_CALLBACK == 1\r
488\r
4225a882 489/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
490 * Switch PWM on\r
4225a882 491 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
492 */\r
493static void\r
494irsnd_on (void)\r
495{\r
496 if (! irsnd_is_on)\r
497 {\r
cb93f9e9 498#ifndef ANALYZE\r
08f2dd9d 499# if defined(PIC_C18) // PIC C18\r
df24bb50 500 PWMon();\r
501 // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
ad4d3d41 502\r
08f2dd9d 503# elif defined (ARM_STM32) // STM32\r
df24bb50 504 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
505 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
506 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r
95b27043 507\r
df24bb50 508# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
509 analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%\r
ad4d3d41 510\r
511# elif defined (__AVR_XMEGA__) \r
ea585783 512# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A\r
df24bb50 513 XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A \r
ea585783 514# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B\r
df24bb50 515 XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B \r
ea585783 516# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C\r
df24bb50 517 XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C\r
ea585783 518# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D\r
df24bb50 519 XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D\r
ea585783 520# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A\r
df24bb50 521 XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A\r
ea585783 522# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B\r
df24bb50 523 XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B\r
ad4d3d41 524# else\r
525# error wrong value of IRSND_OCx\r
526# endif // IRSND_OCx\r
527\r
08f2dd9d 528# else // AVR\r
529# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 530 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r
08f2dd9d 531# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 532 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r
08f2dd9d 533# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 534 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)\r
08f2dd9d 535# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 536 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0\r
08f2dd9d 537# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 538 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A\r
08f2dd9d 539# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 540 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)\r
08f2dd9d 541# else\r
542# error wrong value of IRSND_OCx\r
543# endif // IRSND_OCx\r
544# endif // C18\r
cb93f9e9 545#endif // ANALYZE\r
f50e01e7 546\r
547#if IRSND_USE_CALLBACK == 1\r
df24bb50 548 if (irsnd_callback_ptr)\r
549 {\r
550 (*irsnd_callback_ptr) (TRUE);\r
551 }\r
f50e01e7 552#endif // IRSND_USE_CALLBACK == 1\r
553\r
df24bb50 554 irsnd_is_on = TRUE;\r
4225a882 555 }\r
556}\r
557\r
558/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
559 * Switch PWM off\r
560 * @details Switches PWM off\r
561 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
562 */\r
563static void\r
564irsnd_off (void)\r
565{\r
566 if (irsnd_is_on)\r
567 {\r
cb93f9e9 568#ifndef ANALYZE\r
9c86ff1a 569 \r
08f2dd9d 570# if defined(PIC_C18) // PIC C18\r
df24bb50 571 PWMoff();\r
572 // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
ad4d3d41 573\r
08f2dd9d 574# elif defined (ARM_STM32) // STM32\r
df24bb50 575 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r
576 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r
577 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
578 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r
95b27043 579\r
df24bb50 580# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY\r
95b27043 581 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
ad4d3d41 582\r
583# elif defined (__AVR_XMEGA__)\r
22a5040e 584# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A \r
df24bb50 585 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected\r
22a5040e 586# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B \r
df24bb50 587 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected\r
ad4d3d41 588# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C\r
df24bb50 589 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected\r
ad4d3d41 590# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D\r
df24bb50 591 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected\r
22a5040e 592# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A\r
df24bb50 593 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected\r
22a5040e 594# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B\r
df24bb50 595 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected\r
ad4d3d41 596# else\r
597# error wrong value of IRSND_OCx\r
598# endif // IRSND_OCx\r
599\r
08f2dd9d 600# else //AVR\r
9c86ff1a 601\r
08f2dd9d 602# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 603 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.\r
08f2dd9d 604# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 605 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.\r
08f2dd9d 606# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 607 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.\r
08f2dd9d 608# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 609 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.\r
08f2dd9d 610# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 611 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.\r
08f2dd9d 612# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 613 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.\r
08f2dd9d 614# else\r
615# error wrong value of IRSND_OCx\r
616# endif // IRSND_OCx\r
df24bb50 617 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
08f2dd9d 618# endif //C18\r
cb93f9e9 619#endif // ANALYZE\r
f50e01e7 620\r
621#if IRSND_USE_CALLBACK == 1\r
df24bb50 622 if (irsnd_callback_ptr)\r
623 {\r
624 (*irsnd_callback_ptr) (FALSE);\r
625 }\r
f50e01e7 626#endif // IRSND_USE_CALLBACK == 1\r
627\r
df24bb50 628 irsnd_is_on = FALSE;\r
4225a882 629 }\r
630}\r
631\r
632/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
633 * Set PWM frequency\r
634 * @details sets pwm frequency\r
635 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
636 */\r
7fe8188d 637#if defined(__12F1840)\r
638extern void pwm_init(uint16_t freq);\r
639#include <stdio.h>\r
640#endif\r
641\r
4225a882 642static void\r
08f2dd9d 643irsnd_set_freq (IRSND_FREQ_TYPE freq)\r
4225a882 644{\r
cb93f9e9 645#ifndef ANALYZE\r
7fe8188d 646# if defined(PIC_C18) // PIC C18 or XC8\r
647# if defined(__12F1840) // XC8\r
df24bb50 648 TRISA2=0; \r
649 PR2=freq;\r
650 CCP1M0=1;\r
651 CCP1M1=1;\r
652 CCP1M2=1;\r
653 CCP1M3=1;\r
654 DC1B0=1;\r
655 DC1B1=0;\r
656 CCPR1L = 0b01101001;\r
657 TMR2IF = 0;\r
658 TMR2ON=1;\r
659 CCP1CON &=(~0b0011); // p 197 "active high"\r
7fe8188d 660# else // PIC C18\r
df24bb50 661 OpenPWM(freq); \r
662 SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%\r
7fe8188d 663# endif\r
df24bb50 664 PWMoff();\r
08f2dd9d 665# elif defined (ARM_STM32) // STM32\r
df24bb50 666 static uint32_t TimeBaseFreq = 0;\r
08f2dd9d 667\r
df24bb50 668 if (TimeBaseFreq == 0)\r
669 {\r
670 RCC_ClocksTypeDef RCC_ClocksStructure;\r
671 /* Get system clocks and store timer clock in variable */\r
672 RCC_GetClocksFreq(&RCC_ClocksStructure);\r
08f2dd9d 673# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
df24bb50 674 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
675 {\r
676 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r
677 }\r
678 else\r
679 {\r
680 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;\r
681 }\r
08f2dd9d 682# else\r
df24bb50 683 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
684 {\r
685 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r
686 }\r
687 else\r
688 {\r
689 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;\r
690 }\r
08f2dd9d 691# endif\r
df24bb50 692 }\r
95b27043 693\r
df24bb50 694 freq = TimeBaseFreq/freq;\r
08f2dd9d 695\r
df24bb50 696 /* Set frequency */\r
697 TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
698 /* Set duty cycle */\r
699 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
08f2dd9d 700\r
95b27043 701# elif defined (TEENSY_ARM_CORTEX_M4)\r
df24bb50 702 analogWriteResolution(8); // 8 bit\r
95b27043 703 analogWriteFrequency(IRSND_PIN, freq);\r
704 analogWrite(IRSND_PIN, 0); // pwm off, LOW level\r
ad4d3d41 705\r
706# elif defined (__AVR_XMEGA__)\r
df24bb50 707 XMEGA_Timer.CCA = freq;\r
ad4d3d41 708\r
08f2dd9d 709# else // AVR\r
710\r
711# if IRSND_OCx == IRSND_OC2\r
df24bb50 712 OCR2 = freq; // use register OCR2 for OC2\r
08f2dd9d 713# elif IRSND_OCx == IRSND_OC2A // use OC2A\r
df24bb50 714 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
08f2dd9d 715# elif IRSND_OCx == IRSND_OC2B // use OC2B\r
df24bb50 716 OCR2A = freq; // use register OCR2A for OC2A and OC2B!\r
08f2dd9d 717# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 718 OCR0 = freq; // use register OCR2 for OC2\r
08f2dd9d 719# elif IRSND_OCx == IRSND_OC0A // use OC0A\r
df24bb50 720 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
08f2dd9d 721# elif IRSND_OCx == IRSND_OC0B // use OC0B\r
df24bb50 722 OCR0A = freq; // use register OCR0A for OC0A and OC0B!\r
08f2dd9d 723# else\r
724# error wrong value of IRSND_OCx\r
725# endif\r
726# endif //PIC_C18\r
cb93f9e9 727#endif // ANALYZE\r
4225a882 728}\r
729\r
730/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
731 * Initialize the PWM\r
732 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels\r
733 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
734 */\r
735void\r
736irsnd_init (void)\r
737{\r
cb93f9e9 738#ifndef ANALYZE\r
7fe8188d 739# if defined(PIC_C18) // PIC C18 or XC8 compiler\r
740# if ! defined(__12F1840) // only C18:\r
df24bb50 741 OpenTimer;\r
7fe8188d 742# endif\r
df24bb50 743 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
744 IRSND_PIN = 0; // set IO to outout\r
745 PWMoff();\r
08f2dd9d 746# elif defined (ARM_STM32) // STM32\r
df24bb50 747 GPIO_InitTypeDef GPIO_InitStructure;\r
748 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
749 TIM_OCInitTypeDef TIM_OCInitStructure;\r
08f2dd9d 750\r
751 /* GPIOx clock enable */\r
752# if defined (ARM_STM32L1XX)\r
df24bb50 753 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
08f2dd9d 754# elif defined (ARM_STM32F10X)\r
df24bb50 755 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
756 // RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping\r
08f2dd9d 757# elif defined (ARM_STM32F4XX)\r
df24bb50 758 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);\r
08f2dd9d 759# endif\r
760\r
df24bb50 761 /* GPIO Configuration */\r
762 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;\r
08f2dd9d 763# if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)\r
df24bb50 764 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
765 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
766 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
767 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
768 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
769 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);\r
08f2dd9d 770# elif defined (ARM_STM32F10X)\r
df24bb50 771 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
772 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
773 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);\r
774 // GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping\r
08f2dd9d 775# endif\r
776\r
df24bb50 777 /* TIMx clock enable */\r
08f2dd9d 778# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
df24bb50 779 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
08f2dd9d 780# else\r
df24bb50 781 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
08f2dd9d 782# endif\r
08f2dd9d 783\r
df24bb50 784 /* Time base configuration */\r
785 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r
786 TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
787 TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
788 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
789 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r
95b27043 790\r
df24bb50 791 /* PWM1 Mode configuration */\r
792 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
793 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
794 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
795 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
796 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
95b27043 797\r
df24bb50 798 /* Preload configuration */\r
799 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
800 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
95b27043 801\r
df24bb50 802 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r
95b27043 803\r
804# elif defined (TEENSY_ARM_CORTEX_M4)\r
805 if (!digitalPinHasPWM(IRSND_PIN))\r
df24bb50 806 {\r
807 return;\r
95b27043 808 }\r
22a5040e 809\r
95b27043 810# elif defined (__AVR_XMEGA__)\r
df24bb50 811 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
812 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
22a5040e 813\r
df24bb50 814 XMEGA_Timer.PER = 0xFFFF; //Topwert\r
815 XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC\r
22a5040e 816\r
817# if AVR_PRESCALER == 8\r
df24bb50 818 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8\r
22a5040e 819# else\r
df24bb50 820 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1\r
22a5040e 821# endif\r
df24bb50 822 \r
22a5040e 823# else // AVR\r
df24bb50 824 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
825 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
08f2dd9d 826\r
827# if IRSND_OCx == IRSND_OC2 // use OC2\r
df24bb50 828 TCCR2 = (1<<WGM21); // CTC mode\r
a03ad359 829# if AVR_PRESCALER == 8\r
df24bb50 830 TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8\r
a03ad359 831# else\r
df24bb50 832 TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1\r
a03ad359 833# endif\r
08f2dd9d 834# elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B\r
df24bb50 835 TCCR2A = (1<<WGM21); // CTC mode\r
a03ad359 836# if AVR_PRESCALER == 8\r
df24bb50 837 TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8\r
a03ad359 838# else\r
df24bb50 839 TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1\r
a03ad359 840# endif\r
08f2dd9d 841# elif IRSND_OCx == IRSND_OC0 // use OC0\r
df24bb50 842 TCCR0 = (1<<WGM01); // CTC mode\r
a03ad359 843# if AVR_PRESCALER == 8\r
df24bb50 844 TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8\r
a03ad359 845# else\r
df24bb50 846 TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1\r
a03ad359 847# endif\r
08f2dd9d 848# elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B\r
df24bb50 849 TCCR0A = (1<<WGM01); // CTC mode\r
a03ad359 850# if AVR_PRESCALER == 8\r
df24bb50 851 TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8\r
a03ad359 852# else\r
df24bb50 853 TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1\r
a03ad359 854# endif\r
08f2dd9d 855# else\r
856# error wrong value of IRSND_OCx\r
857# endif\r
df24bb50 858 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
08f2dd9d 859# endif //PIC_C18\r
cb93f9e9 860#endif // ANALYZE\r
4225a882 861}\r
862\r
f50e01e7 863#if IRSND_USE_CALLBACK == 1\r
864void\r
865irsnd_set_callback_ptr (void (*cb)(uint8_t))\r
866{\r
867 irsnd_callback_ptr = cb;\r
868}\r
869#endif // IRSND_USE_CALLBACK == 1\r
870\r
4225a882 871uint8_t\r
872irsnd_is_busy (void)\r
873{\r
874 return irsnd_busy;\r
875}\r
876\r
877static uint16_t\r
878bitsrevervse (uint16_t x, uint8_t len)\r
879{\r
880 uint16_t xx = 0;\r
881\r
882 while(len)\r
883 {\r
df24bb50 884 xx <<= 1;\r
885 if (x & 1)\r
886 {\r
887 xx |= 1;\r
888 }\r
889 x >>= 1;\r
890 len--;\r
4225a882 891 }\r
892 return xx;\r
893}\r
894\r
895\r
9547ee89 896#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
897static uint8_t sircs_additional_bitlen;\r
898#endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
899\r
4225a882 900uint8_t\r
879b06c2 901irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)\r
4225a882 902{\r
903#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
904 static uint8_t toggle_bit_recs80;\r
905#endif\r
906#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
907 static uint8_t toggle_bit_recs80ext;\r
908#endif\r
909#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
910 static uint8_t toggle_bit_rc5;\r
9547ee89 911#endif\r
779fbc81 912#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
9547ee89 913 static uint8_t toggle_bit_rc6;\r
beda975f 914#endif\r
915#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
916 static uint8_t toggle_bit_thomson;\r
4225a882 917#endif\r
918 uint16_t address;\r
919 uint16_t command;\r
920\r
879b06c2 921 if (do_wait)\r
4225a882 922 {\r
df24bb50 923 while (irsnd_busy)\r
924 {\r
925 // do nothing;\r
926 }\r
879b06c2 927 }\r
928 else if (irsnd_busy)\r
929 {\r
df24bb50 930 return (FALSE);\r
4225a882 931 }\r
932\r
933 irsnd_protocol = irmp_data_p->protocol;\r
beda975f 934 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;\r
4225a882 935\r
936 switch (irsnd_protocol)\r
937 {\r
938#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 939 case IRMP_SIRCS_PROTOCOL:\r
940 {\r
941 // uint8_t sircs_additional_command_len;\r
942 uint8_t sircs_additional_address_len;\r
943\r
944 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen\r
945\r
946 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)\r
947 {\r
948 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;\r
949 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);\r
950 }\r
951 else\r
952 {\r
953 // sircs_additional_command_len = sircs_additional_bitlen;\r
954 sircs_additional_address_len = 0;\r
955 }\r
956\r
957 command = bitsrevervse (irmp_data_p->command, 15);\r
958\r
959 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC\r
960 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****\r
961\r
962 if (sircs_additional_address_len > 0)\r
963 {\r
964 address = bitsrevervse (irmp_data_p->address, 5);\r
965 irsnd_buffer[1] |= (address & 0x0010) >> 4;\r
966 irsnd_buffer[2] = (address & 0x000F) << 4;\r
967 }\r
968 irsnd_busy = TRUE;\r
969 break;\r
970 }\r
4225a882 971#endif\r
972#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 973 case IRMP_APPLE_PROTOCOL:\r
974 {\r
975 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command\r
976 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)\r
977\r
978 address = bitsrevervse (address, NEC_ADDRESS_LEN);\r
979 command = bitsrevervse (command, NEC_COMMAND_LEN);\r
980\r
981 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command\r
982\r
983 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
984 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
985 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
986 irsnd_buffer[3] = 0x8B; // 10001011 (id)\r
987 irsnd_busy = TRUE;\r
988 break;\r
989 }\r
990 case IRMP_NEC_PROTOCOL:\r
991 {\r
992 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);\r
993 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);\r
994\r
995 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
996 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
997 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
998 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
999 irsnd_busy = TRUE;\r
1000 break;\r
1001 }\r
7644ac04 1002#endif\r
1003#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 1004 case IRMP_NEC16_PROTOCOL:\r
1005 {\r
1006 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);\r
1007 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);\r
1008\r
1009 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA\r
1010 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
1011 irsnd_busy = TRUE;\r
1012 break;\r
1013 }\r
7644ac04 1014#endif\r
1015#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 1016 case IRMP_NEC42_PROTOCOL:\r
1017 {\r
1018 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);\r
1019 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);\r
1020\r
1021 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA\r
1022 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa\r
1023 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa\r
1024 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC\r
1025 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc\r
1026 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc\r
1027 irsnd_busy = TRUE;\r
1028 break;\r
1029 }\r
4225a882 1030#endif\r
c1dfa01f 1031#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 1032 case IRMP_LGAIR_PROTOCOL:\r
1033 {\r
1034 address = irmp_data_p->address;\r
1035 command = irmp_data_p->command;\r
1036\r
1037 irsnd_buffer[0] = ( (address & 0x00FF)); // AAAAAAAA\r
1038 irsnd_buffer[1] = ( (command & 0xFF00) >> 8); // CCCCCCCC\r
1039 irsnd_buffer[2] = ( (command & 0x00FF)); // CCCCCCCC\r
1040 irsnd_buffer[3] = (( ((command & 0xF000) >> 12) + // checksum\r
1041 ((command & 0x0F00) >> 8) +\r
1042 ((command & 0x00F0) >>4 ) +\r
1043 ((command & 0x000F))) & 0x000F) << 4;\r
1044 irsnd_busy = TRUE;\r
1045 break;\r
1046 }\r
c1dfa01f 1047#endif\r
4225a882 1048#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 1049 case IRMP_SAMSUNG_PROTOCOL:\r
1050 {\r
1051 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1052 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);\r
1053\r
1054 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1055 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1056 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC\r
1057 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc\r
1058 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000\r
1059 irsnd_busy = TRUE;\r
1060 break;\r
1061 }\r
1062 case IRMP_SAMSUNG32_PROTOCOL:\r
1063 {\r
1064 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1065 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);\r
1066\r
1067 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1068 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1069 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1070 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC\r
1071 irsnd_busy = TRUE;\r
1072 break;\r
1073 }\r
4225a882 1074#endif\r
ac8504f8 1075#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 1076 case IRMP_SAMSUNG48_PROTOCOL:\r
1077 {\r
1078 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
1079 command = bitsrevervse (irmp_data_p->command, 16);\r
1080\r
1081 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1082 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1083 irsnd_buffer[2] = ((command & 0xFF00) >> 8); // CCCCCCCC\r
1084 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
1085 irsnd_buffer[4] = (command & 0x00FF); // CCCCCCCC\r
1086 irsnd_buffer[5] = ~(command & 0x00FF); // cccccccc\r
1087 irsnd_busy = TRUE;\r
1088 break;\r
1089 }\r
ac8504f8 1090#endif\r
4225a882 1091#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 1092 case IRMP_MATSUSHITA_PROTOCOL:\r
1093 {\r
1094 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);\r
1095 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);\r
1096\r
1097 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
1098 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA\r
1099 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA\r
1100 irsnd_busy = TRUE;\r
1101 break;\r
1102 }\r
4225a882 1103#endif\r
3d2da98a 1104#if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1\r
df24bb50 1105 case IRMP_TECHNICS_PROTOCOL:\r
1106 {\r
1107 command = bitsrevervse (irmp_data_p->command, TECHNICS_COMMAND_LEN);\r
1108\r
1109 irsnd_buffer[0] = (command & 0x07FC) >> 3; // CCCCCCCC\r
1110 irsnd_buffer[1] = ((command & 0x0007) << 5) | ((~command & 0x07C0) >> 6); // CCCccccc\r
1111 irsnd_buffer[2] = (~command & 0x003F) << 2; // cccccc\r
1112 irsnd_busy = TRUE;\r
1113 break;\r
1114 }\r
3d2da98a 1115#endif\r
770a1a9d 1116#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 1117 case IRMP_KASEIKYO_PROTOCOL:\r
1118 {\r
1119 uint8_t xor_value;\r
1120 uint16_t genre2;\r
95b27043 1121\r
df24bb50 1122 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);\r
1123 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);\r
1124 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);\r
95b27043 1125\r
df24bb50 1126 xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r
95b27043 1127\r
df24bb50 1128 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1129 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
1130 irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC\r
1131 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC\r
1132 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
95b27043 1133\r
df24bb50 1134 xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r
95b27043 1135\r
df24bb50 1136 irsnd_buffer[5] = xor_value;\r
1137 irsnd_busy = TRUE;\r
1138 break;\r
1139 }\r
95b27043 1140#endif\r
1141#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 1142 case IRMP_PANASONIC_PROTOCOL:\r
1143 {\r
1144 address = bitsrevervse (irmp_data_p->address, PANASONIC_ADDRESS_LEN);\r
1145 command = bitsrevervse (irmp_data_p->command, PANASONIC_COMMAND_LEN);\r
1146\r
1147 irsnd_buffer[0] = 0x40; // 01000000\r
1148 irsnd_buffer[1] = 0x04; // 00000100\r
1149 irsnd_buffer[2] = 0x01; // 00000001\r
1150 irsnd_buffer[3] = (address & 0xFF00) >> 8; // AAAAAAAA\r
1151 irsnd_buffer[4] = (address & 0x00FF); // AAAAAAAA\r
1152 irsnd_buffer[5] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1153 irsnd_buffer[6] = (command & 0x00FF); // CCCCCCCC\r
1154\r
1155 irsnd_busy = TRUE;\r
1156 break;\r
1157 }\r
770a1a9d 1158#endif\r
4225a882 1159#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 1160 case IRMP_RECS80_PROTOCOL:\r
1161 {\r
1162 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x40;\r
1163\r
1164 irsnd_buffer[0] = 0x80 | toggle_bit_recs80 | ((irmp_data_p->address & 0x0007) << 3) |\r
1165 ((irmp_data_p->command & 0x0038) >> 3); // STAAACCC\r
1166 irsnd_buffer[1] = (irmp_data_p->command & 0x07) << 5; // CCC00000\r
1167 irsnd_busy = TRUE;\r
1168 break;\r
1169 }\r
4225a882 1170#endif\r
1171#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 1172 case IRMP_RECS80EXT_PROTOCOL:\r
1173 {\r
1174 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;\r
1175\r
1176 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |\r
1177 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC\r
1178 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000\r
1179 irsnd_busy = TRUE;\r
1180 break;\r
1181 }\r
4225a882 1182#endif\r
1183#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 1184 case IRMP_RC5_PROTOCOL:\r
1185 {\r
1186 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;\r
1187\r
1188 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |\r
1189 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC\r
1190 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000\r
1191 irsnd_busy = TRUE;\r
1192 break;\r
1193 }\r
4225a882 1194#endif\r
9547ee89 1195#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 1196 case IRMP_RC6_PROTOCOL:\r
1197 {\r
1198 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
1199\r
1200 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000\r
1201 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC\r
1202 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC\r
1203 irsnd_busy = TRUE;\r
1204 break;\r
1205 }\r
9547ee89 1206#endif\r
1207#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 1208 case IRMP_RC6A_PROTOCOL:\r
1209 {\r
1210 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;\r
1211\r
1212 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110\r
1213 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA\r
1214 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC\r
1215 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
1216 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC\r
1217 irsnd_busy = TRUE;\r
1218 break;\r
1219 }\r
9547ee89 1220#endif\r
4225a882 1221#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 1222 case IRMP_DENON_PROTOCOL:\r
1223 {\r
1224 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)\r
1225 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC\r
1226 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)\r
1227 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc\r
1228 irsnd_busy = TRUE;\r
1229 break;\r
1230 }\r
4225a882 1231#endif\r
beda975f 1232#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 1233 case IRMP_THOMSON_PROTOCOL:\r
1234 {\r
1235 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;\r
1236\r
1237 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)\r
1238 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC\r
1239 irsnd_busy = TRUE;\r
1240 break;\r
1241 }\r
95b27043 1242#endif\r
1243#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 1244 case IRMP_BOSE_PROTOCOL:\r
1245 {\r
1246 command = bitsrevervse (irmp_data_p->command, BOSE_COMMAND_LEN);\r
1247\r
1248 irsnd_buffer[0] = (command & 0xFF00) >> 8; // CCCCCCCC\r
1249 irsnd_buffer[1] = ~((command & 0xFF00) >> 8); // cccccccc\r
1250 irsnd_busy = TRUE;\r
1251 break;\r
1252 }\r
beda975f 1253#endif\r
4225a882 1254#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 1255 case IRMP_NUBERT_PROTOCOL:\r
1256 {\r
1257 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
1258 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
1259 irsnd_busy = TRUE;\r
1260 break;\r
1261 }\r
5481e9cd 1262#endif\r
0715cf5e 1263#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 1264 case IRMP_FAN_PROTOCOL:\r
1265 {\r
1266 irsnd_buffer[0] = irmp_data_p->command >> 3; // CCCCCCCC\r
1267 irsnd_buffer[1] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
1268 irsnd_busy = TRUE;\r
1269 break;\r
1270 }\r
0715cf5e 1271#endif\r
15dd9c32 1272#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 1273 case IRMP_SPEAKER_PROTOCOL:\r
1274 {\r
1275 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
1276 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
1277 irsnd_busy = TRUE;\r
1278 break;\r
1279 }\r
15dd9c32 1280#endif\r
5481e9cd 1281#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 1282 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
1283 {\r
1284 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC\r
1285 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC\r
1286 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
1287 irsnd_busy = TRUE;\r
1288 break;\r
1289 }\r
4225a882 1290#endif\r
5b437ff6 1291#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 1292 case IRMP_GRUNDIG_PROTOCOL:\r
1293 {\r
1294 command = bitsrevervse (irmp_data_p->command, TELEFUNKEN_COMMAND_LEN);\r
5b437ff6 1295\r
df24bb50 1296 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)\r
1297 irsnd_buffer[1] = 0xC0; // 11\r
1298 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)\r
1299 irsnd_buffer[3] = (command << 6) & 0xC0; // CC\r
d155e9ab 1300\r
df24bb50 1301 irsnd_busy = TRUE;\r
1302 break;\r
1303 }\r
d155e9ab 1304#endif\r
9c07687e 1305#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 1306 case IRMP_TELEFUNKEN_PROTOCOL:\r
1307 {\r
1308 irsnd_buffer[0] = irmp_data_p->command >> 7; // CCCCCCCC\r
1309 irsnd_buffer[1] = (irmp_data_p->command << 1) & 0xff; // CCCCCCC\r
9c07687e 1310\r
df24bb50 1311 irsnd_busy = TRUE;\r
1312 break;\r
1313 }\r
9c07687e 1314#endif\r
a48187fa 1315#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 1316 case IRMP_IR60_PROTOCOL:\r
1317 {\r
1318 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);\r
08f2dd9d 1319#if 0\r
df24bb50 1320 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)\r
1321 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)\r
08f2dd9d 1322#else\r
df24bb50 1323 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)\r
1324 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)\r
08f2dd9d 1325#endif\r
a48187fa 1326\r
df24bb50 1327 irsnd_busy = TRUE;\r
1328 break;\r
1329 }\r
a48187fa 1330#endif\r
d155e9ab 1331#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 1332 case IRMP_NOKIA_PROTOCOL:\r
1333 {\r
1334 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);\r
1335 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);\r
1336\r
1337 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)\r
1338 irsnd_buffer[1] = 0xFF; // 11111111\r
1339 irsnd_buffer[2] = 0x80; // 1\r
1340 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)\r
1341 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA\r
1342 irsnd_buffer[5] = (address << 7); // A\r
1343\r
1344 irsnd_busy = TRUE;\r
1345 break;\r
1346 }\r
5b437ff6 1347#endif\r
a7054daf 1348#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 1349 case IRMP_SIEMENS_PROTOCOL:\r
1350 {\r
1351 irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA\r
1352 irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC\r
1353 irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r
1354\r
1355 irsnd_busy = TRUE;\r
1356 break;\r
1357 }\r
b5ea7869 1358#endif\r
cb93f9e9 1359#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 1360 case IRMP_RUWIDO_PROTOCOL:\r
1361 {\r
1362 irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA\r
1363 irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC\r
1364 irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c\r
1365 irsnd_busy = TRUE;\r
1366 break;\r
1367 }\r
cb93f9e9 1368#endif\r
48664931 1369#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 1370 case IRMP_FDC_PROTOCOL:\r
1371 {\r
1372 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);\r
1373 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);\r
1374\r
1375 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA\r
1376 irsnd_buffer[1] = 0; // 00000000\r
1377 irsnd_buffer[2] = 0; // 0000RRRR\r
1378 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC\r
1379 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc\r
1380 irsnd_busy = TRUE;\r
1381 break;\r
1382 }\r
c7c9a4a1 1383#endif\r
1384#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 1385 case IRMP_RCCAR_PROTOCOL:\r
1386 {\r
1387 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1\r
1388 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V\r
1389\r
1390 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3\r
1391 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0\r
1392 \r
1393 irsnd_busy = TRUE;\r
1394 break;\r
1395 }\r
a7054daf 1396#endif\r
c7a47e89 1397#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 1398 case IRMP_JVC_PROTOCOL:\r
1399 {\r
1400 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);\r
1401 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);\r
c7a47e89 1402\r
df24bb50 1403 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC\r
1404 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC\r
c7a47e89 1405\r
df24bb50 1406 irsnd_busy = TRUE;\r
1407 break;\r
1408 }\r
c7a47e89 1409#endif\r
9405f84a 1410#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 1411 case IRMP_NIKON_PROTOCOL:\r
1412 {\r
1413 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC\r
1414 irsnd_busy = TRUE;\r
1415 break;\r
1416 }\r
f50e01e7 1417#endif\r
1418#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 1419 case IRMP_LEGO_PROTOCOL:\r
1420 {\r
1421 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);\r
1422\r
1423 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
1424 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc\r
1425 irsnd_busy = TRUE;\r
1426 break;\r
1427 }\r
fa09ce10 1428#endif\r
1429#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 1430 case IRMP_A1TVBOX_PROTOCOL:\r
1431 {\r
1432 irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA\r
1433 irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC\r
1434 irsnd_buffer[2] = (irmp_data_p->command << 6); // CC\r
1435\r
1436 irsnd_busy = TRUE;\r
1437 break;\r
1438 }\r
e664a9f3 1439#endif\r
c9b6916a 1440#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 1441 case IRMP_ROOMBA_PROTOCOL:\r
1442 {\r
1443 irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.\r
1444 irsnd_busy = TRUE;\r
1445 break;\r
1446 }\r
c9b6916a 1447#endif\r
003c1008 1448#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 1449 case IRMP_PENTAX_PROTOCOL:\r
1450 {\r
1451 irsnd_buffer[0] = (irmp_data_p->command & 0x3F) << 2; // CCCCCC..\r
1452 irsnd_busy = TRUE;\r
1453 break;\r
1454 }\r
003c1008 1455#endif\r
43c535be 1456#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
1457# define ACP_SET_BIT(acp24_bitno, c, irmp_bitno) \\r
df24bb50 1458 do \\r
1459 { \\r
1460 if ((c) & (1<<(irmp_bitno))) \\r
1461 { \\r
1462 irsnd_buffer[((acp24_bitno)>>3)] |= 1 << (((7 - (acp24_bitno)) & 0x07)); \\r
1463 } \\r
1464 } while (0)\r
1465\r
1466 case IRMP_ACP24_PROTOCOL:\r
1467 {\r
1468 uint16_t cmd = irmp_data_p->command;\r
1469 uint8_t i;\r
1470\r
1471 address = bitsrevervse (irmp_data_p->address, ACP24_ADDRESS_LEN);\r
1472\r
1473 for (i = 0; i < 8; i++)\r
1474 {\r
1475 irsnd_buffer[i] = 0x00; // CCCCCCCC\r
1476 }\r
1477\r
1478 // ACP24-Frame:\r
1479 // 1 2 3 4 5 6\r
1480 // 0123456789012345678901234567890123456789012345678901234567890123456789\r
1481 // N VVMMM ? ??? t vmA x y TTTT\r
1482 // \r
1483 // irmp_data_p->command:\r
1484 // \r
1485 // 5432109876543210\r
1486 // NAVVvMMMmtxyTTTT\r
1487\r
1488 ACP_SET_BIT( 0, cmd, 15);\r
1489 ACP_SET_BIT(24, cmd, 14);\r
1490 ACP_SET_BIT( 2, cmd, 13);\r
1491 ACP_SET_BIT( 3, cmd, 12);\r
1492 ACP_SET_BIT(22, cmd, 11);\r
1493 ACP_SET_BIT( 4, cmd, 10);\r
1494 ACP_SET_BIT( 5, cmd, 9);\r
1495 ACP_SET_BIT( 6, cmd, 8);\r
1496 ACP_SET_BIT(23, cmd, 7);\r
1497 ACP_SET_BIT(20, cmd, 6);\r
1498 ACP_SET_BIT(26, cmd, 5);\r
1499 ACP_SET_BIT(44, cmd, 4);\r
1500 ACP_SET_BIT(66, cmd, 3);\r
1501 ACP_SET_BIT(67, cmd, 2);\r
1502 ACP_SET_BIT(68, cmd, 1);\r
1503 ACP_SET_BIT(69, cmd, 0);\r
1504\r
1505 irsnd_busy = TRUE;\r
1506 break;\r
1507 }\r
1508#endif\r
1509\r
1510 default:\r
1511 {\r
1512 break;\r
1513 }\r
4225a882 1514 }\r
1515\r
1516 return irsnd_busy;\r
1517}\r
1518\r
beda975f 1519void\r
1520irsnd_stop (void)\r
1521{\r
acf7fb44 1522 irsnd_repeat = 0;\r
beda975f 1523}\r
1524\r
4225a882 1525/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
1526 * ISR routine\r
1527 * @details ISR routine, called 10000 times per second\r
1528 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
1529 */\r
1530uint8_t\r
1531irsnd_ISR (void)\r
1532{\r
a48187fa 1533 static uint8_t send_trailer = FALSE;\r
1534 static uint8_t current_bit = 0xFF;\r
1535 static uint8_t pulse_counter = 0;\r
1536 static IRSND_PAUSE_LEN pause_counter = 0;\r
1537 static uint8_t startbit_pulse_len = 0;\r
1538 static IRSND_PAUSE_LEN startbit_pause_len = 0;\r
1539 static uint8_t pulse_1_len = 0;\r
1540 static uint8_t pause_1_len = 0;\r
1541 static uint8_t pulse_0_len = 0;\r
1542 static uint8_t pause_0_len = 0;\r
1543 static uint8_t has_stop_bit = 0;\r
1544 static uint8_t new_frame = TRUE;\r
1545 static uint8_t complete_data_len = 0;\r
1546 static uint8_t n_repeat_frames = 0; // number of repetition frames\r
1547 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions\r
1548 static uint8_t auto_repetition_counter = 0; // auto_repetition counter\r
1549 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!\r
1550 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!\r
1551 static uint8_t repeat_counter = 0; // repeat counter\r
1552 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!\r
1553 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!\r
5481e9cd 1554#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
a48187fa 1555 static uint8_t last_bit_value;\r
5481e9cd 1556#endif\r
a48187fa 1557 static uint8_t pulse_len = 0xFF;\r
08f2dd9d 1558 static IRSND_PAUSE_LEN pause_len = 0xFF;\r
4225a882 1559\r
1560 if (irsnd_busy)\r
1561 {\r
df24bb50 1562 if (current_bit == 0xFF && new_frame) // start of transmission...\r
1563 {\r
1564 if (auto_repetition_counter > 0)\r
1565 {\r
1566 auto_repetition_pause_counter++;\r
08f2dd9d 1567\r
df24bb50 1568 if (auto_repetition_pause_counter >= auto_repetition_pause_len)\r
1569 {\r
1570 auto_repetition_pause_counter = 0;\r
4225a882 1571\r
08f2dd9d 1572#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 1573 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame\r
1574 {\r
1575 current_bit = 16;\r
1576 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;\r
1577 }\r
1578 else\r
08f2dd9d 1579#endif\r
1580#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 1581 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame\r
1582 {\r
1583 current_bit = 15;\r
1584 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;\r
1585 }\r
1586 else\r
08f2dd9d 1587#endif\r
1588#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 1589 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame\r
1590 {\r
1591 current_bit = 7;\r
1592 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;\r
1593 }\r
1594 else\r
08f2dd9d 1595#endif\r
1596#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 1597 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame\r
1598 {\r
1599 if (auto_repetition_counter + 1 < n_auto_repetitions)\r
1600 {\r
1601 current_bit = 23;\r
1602 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;\r
1603 }\r
1604 else // nokia stop frame\r
1605 {\r
1606 current_bit = 0xFF;\r
1607 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
1608 }\r
1609 }\r
1610 else\r
1611#endif\r
1612 {\r
1613 ;\r
1614 }\r
1615 }\r
1616 else\r
1617 {\r
cb93f9e9 1618#ifdef ANALYZE\r
df24bb50 1619 if (irsnd_is_on)\r
1620 {\r
1621 putchar ('0');\r
1622 }\r
1623 else\r
1624 {\r
1625 putchar ('1');\r
1626 }\r
1627#endif\r
1628 return irsnd_busy;\r
1629 }\r
1630 }\r
1631 else if (packet_repeat_pause_counter < repeat_frame_pause_len)\r
1632 {\r
1633 packet_repeat_pause_counter++;\r
cb93f9e9 1634#ifdef ANALYZE\r
df24bb50 1635 if (irsnd_is_on)\r
1636 {\r
1637 putchar ('0');\r
1638 }\r
1639 else\r
1640 {\r
1641 putchar ('1');\r
1642 }\r
1643#endif\r
1644 return irsnd_busy;\r
1645 }\r
1646 else\r
1647 {\r
1648 if (send_trailer)\r
1649 {\r
1650 irsnd_busy = FALSE;\r
1651 send_trailer = FALSE;\r
1652 return irsnd_busy;\r
1653 }\r
1654 \r
1655 n_repeat_frames = irsnd_repeat;\r
1656\r
1657 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)\r
1658 {\r
1659 n_repeat_frames = 255;\r
1660 }\r
1661\r
1662 packet_repeat_pause_counter = 0;\r
1663 pulse_counter = 0;\r
1664 pause_counter = 0;\r
1665\r
1666 switch (irsnd_protocol)\r
1667 {\r
4225a882 1668#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 1669 case IRMP_SIRCS_PROTOCOL:\r
1670 {\r
1671 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;\r
1672 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;\r
1673 pulse_1_len = SIRCS_1_PULSE_LEN;\r
1674 pause_1_len = SIRCS_PAUSE_LEN - 1;\r
1675 pulse_0_len = SIRCS_0_PULSE_LEN;\r
1676 pause_0_len = SIRCS_PAUSE_LEN - 1;\r
1677 has_stop_bit = SIRCS_STOP_BIT;\r
1678 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;\r
1679 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame\r
1680 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause\r
1681 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;\r
1682 irsnd_set_freq (IRSND_FREQ_40_KHZ);\r
1683 break;\r
1684 }\r
4225a882 1685#endif\r
1686#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 1687 case IRMP_NEC_PROTOCOL:\r
1688 {\r
1689 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1690\r
1691 if (repeat_counter > 0)\r
1692 {\r
1693 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;\r
1694 complete_data_len = 0;\r
1695 }\r
1696 else\r
1697 {\r
1698 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1699 complete_data_len = NEC_COMPLETE_DATA_LEN;\r
1700 }\r
1701\r
1702 pulse_1_len = NEC_PULSE_LEN;\r
1703 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1704 pulse_0_len = NEC_PULSE_LEN;\r
1705 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1706 has_stop_bit = NEC_STOP_BIT;\r
1707 n_auto_repetitions = 1; // 1 frame\r
1708 auto_repetition_pause_len = 0;\r
1709 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1710 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1711 break;\r
1712 }\r
4225a882 1713#endif\r
7644ac04 1714#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 1715 case IRMP_NEC16_PROTOCOL:\r
1716 {\r
1717 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1718 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1719 pulse_1_len = NEC_PULSE_LEN;\r
1720 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1721 pulse_0_len = NEC_PULSE_LEN;\r
1722 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1723 has_stop_bit = NEC_STOP_BIT;\r
1724 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit\r
1725 n_auto_repetitions = 1; // 1 frame\r
1726 auto_repetition_pause_len = 0;\r
1727 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1728 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1729 break;\r
1730 }\r
7644ac04 1731#endif\r
1732#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 1733 case IRMP_NEC42_PROTOCOL:\r
1734 {\r
1735 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1736 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1737 pulse_1_len = NEC_PULSE_LEN;\r
1738 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1739 pulse_0_len = NEC_PULSE_LEN;\r
1740 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1741 has_stop_bit = NEC_STOP_BIT;\r
1742 complete_data_len = NEC42_COMPLETE_DATA_LEN;\r
1743 n_auto_repetitions = 1; // 1 frame\r
1744 auto_repetition_pause_len = 0;\r
1745 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1746 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1747 break;\r
1748 }\r
7644ac04 1749#endif\r
c1dfa01f 1750#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 1751 case IRMP_LGAIR_PROTOCOL:\r
1752 {\r
1753 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
1754 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
1755 pulse_1_len = NEC_PULSE_LEN;\r
1756 pause_1_len = NEC_1_PAUSE_LEN - 1;\r
1757 pulse_0_len = NEC_PULSE_LEN;\r
1758 pause_0_len = NEC_0_PAUSE_LEN - 1;\r
1759 has_stop_bit = NEC_STOP_BIT;\r
1760 complete_data_len = LGAIR_COMPLETE_DATA_LEN;\r
1761 n_auto_repetitions = 1; // 1 frame\r
1762 auto_repetition_pause_len = 0;\r
1763 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;\r
1764 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1765 break;\r
1766 }\r
c1dfa01f 1767#endif\r
4225a882 1768#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 1769 case IRMP_SAMSUNG_PROTOCOL:\r
1770 {\r
1771 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1772 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1773 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1774 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1775 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1776 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1777 has_stop_bit = SAMSUNG_STOP_BIT;\r
1778 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;\r
1779 n_auto_repetitions = 1; // 1 frame\r
1780 auto_repetition_pause_len = 0;\r
1781 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;\r
1782 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1783 break;\r
1784 }\r
1785\r
1786 case IRMP_SAMSUNG32_PROTOCOL:\r
1787 {\r
1788 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1789 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1790 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1791 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1792 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1793 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1794 has_stop_bit = SAMSUNG_STOP_BIT;\r
1795 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;\r
1796 n_auto_repetitions = SAMSUNG32_FRAMES; // 1 frame\r
1797 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r
1798 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;\r
1799 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1800 break;\r
1801 }\r
4225a882 1802#endif\r
ac8504f8 1803#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 1804 case IRMP_SAMSUNG48_PROTOCOL:\r
1805 {\r
1806 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
1807 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
1808 pulse_1_len = SAMSUNG_PULSE_LEN;\r
1809 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;\r
1810 pulse_0_len = SAMSUNG_PULSE_LEN;\r
1811 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;\r
1812 has_stop_bit = SAMSUNG_STOP_BIT;\r
1813 complete_data_len = SAMSUNG48_COMPLETE_DATA_LEN;\r
1814 n_auto_repetitions = SAMSUNG48_FRAMES; // 1 frame\r
1815 auto_repetition_pause_len = SAMSUNG48_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause\r
1816 repeat_frame_pause_len = SAMSUNG48_FRAME_REPEAT_PAUSE_LEN;\r
1817 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1818 break;\r
1819 }\r
ac8504f8 1820#endif\r
4225a882 1821#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 1822 case IRMP_MATSUSHITA_PROTOCOL:\r
1823 {\r
1824 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
1825 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r
1826 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
1827 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r
1828 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
1829 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r
1830 has_stop_bit = MATSUSHITA_STOP_BIT;\r
1831 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;\r
1832 n_auto_repetitions = 1; // 1 frame\r
1833 auto_repetition_pause_len = 0;\r
1834 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r
1835 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1836 break;\r
1837 }\r
4225a882 1838#endif\r
3d2da98a 1839#if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1\r
df24bb50 1840 case IRMP_TECHNICS_PROTOCOL:\r
1841 {\r
1842 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
1843 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;\r
1844 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
1845 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;\r
1846 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
1847 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;\r
1848 has_stop_bit = MATSUSHITA_STOP_BIT;\r
1849 complete_data_len = TECHNICS_COMPLETE_DATA_LEN; // here TECHNICS\r
1850 n_auto_repetitions = 1; // 1 frame\r
1851 auto_repetition_pause_len = 0;\r
1852 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;\r
1853 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1854 break;\r
1855 }\r
3d2da98a 1856#endif\r
770a1a9d 1857#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 1858 case IRMP_KASEIKYO_PROTOCOL:\r
1859 {\r
1860 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;\r
1861 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;\r
1862 pulse_1_len = KASEIKYO_PULSE_LEN;\r
1863 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;\r
1864 pulse_0_len = KASEIKYO_PULSE_LEN;\r
1865 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;\r
1866 has_stop_bit = KASEIKYO_STOP_BIT;\r
1867 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;\r
1868 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame\r
1869 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause\r
1870 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;\r
1871 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1872 break;\r
1873 }\r
95b27043 1874#endif\r
1875#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 1876 case IRMP_PANASONIC_PROTOCOL:\r
1877 {\r
1878 startbit_pulse_len = PANASONIC_START_BIT_PULSE_LEN;\r
1879 startbit_pause_len = PANASONIC_START_BIT_PAUSE_LEN - 1;\r
1880 pulse_1_len = PANASONIC_PULSE_LEN;\r
1881 pause_1_len = PANASONIC_1_PAUSE_LEN - 1;\r
1882 pulse_0_len = PANASONIC_PULSE_LEN;\r
1883 pause_0_len = PANASONIC_0_PAUSE_LEN - 1;\r
1884 has_stop_bit = PANASONIC_STOP_BIT;\r
1885 complete_data_len = PANASONIC_COMPLETE_DATA_LEN;\r
1886 n_auto_repetitions = PANASONIC_FRAMES; // 1 frame\r
1887 auto_repetition_pause_len = PANASONIC_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause\r
1888 repeat_frame_pause_len = PANASONIC_FRAME_REPEAT_PAUSE_LEN;\r
1889 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1890 break;\r
1891 }\r
770a1a9d 1892#endif\r
4225a882 1893#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 1894 case IRMP_RECS80_PROTOCOL:\r
1895 {\r
1896 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;\r
1897 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;\r
1898 pulse_1_len = RECS80_PULSE_LEN;\r
1899 pause_1_len = RECS80_1_PAUSE_LEN - 1;\r
1900 pulse_0_len = RECS80_PULSE_LEN;\r
1901 pause_0_len = RECS80_0_PAUSE_LEN - 1;\r
1902 has_stop_bit = RECS80_STOP_BIT;\r
1903 complete_data_len = RECS80_COMPLETE_DATA_LEN;\r
1904 n_auto_repetitions = 1; // 1 frame\r
1905 auto_repetition_pause_len = 0;\r
1906 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;\r
1907 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1908 break;\r
1909 }\r
4225a882 1910#endif\r
1911#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 1912 case IRMP_RECS80EXT_PROTOCOL:\r
1913 {\r
1914 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;\r
1915 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;\r
1916 pulse_1_len = RECS80EXT_PULSE_LEN;\r
1917 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;\r
1918 pulse_0_len = RECS80EXT_PULSE_LEN;\r
1919 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;\r
1920 has_stop_bit = RECS80EXT_STOP_BIT;\r
1921 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;\r
1922 n_auto_repetitions = 1; // 1 frame\r
1923 auto_repetition_pause_len = 0;\r
1924 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;\r
1925 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1926 break;\r
1927 }\r
4225a882 1928#endif\r
9c07687e 1929#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 1930 case IRMP_TELEFUNKEN_PROTOCOL:\r
1931 {\r
1932 startbit_pulse_len = TELEFUNKEN_START_BIT_PULSE_LEN;\r
1933 startbit_pause_len = TELEFUNKEN_START_BIT_PAUSE_LEN - 1;\r
1934 pulse_1_len = TELEFUNKEN_PULSE_LEN;\r
1935 pause_1_len = TELEFUNKEN_1_PAUSE_LEN - 1;\r
1936 pulse_0_len = TELEFUNKEN_PULSE_LEN;\r
1937 pause_0_len = TELEFUNKEN_0_PAUSE_LEN - 1;\r
1938 has_stop_bit = TELEFUNKEN_STOP_BIT;\r
1939 complete_data_len = TELEFUNKEN_COMPLETE_DATA_LEN;\r
1940 n_auto_repetitions = 1; // 1 frames\r
1941 auto_repetition_pause_len = 0; // TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN; // xx ms pause\r
1942 repeat_frame_pause_len = TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
1943 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
1944 break;\r
1945 }\r
9c07687e 1946#endif\r
4225a882 1947#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 1948 case IRMP_RC5_PROTOCOL:\r
1949 {\r
1950 startbit_pulse_len = RC5_BIT_LEN;\r
1951 startbit_pause_len = RC5_BIT_LEN;\r
1952 pulse_len = RC5_BIT_LEN;\r
1953 pause_len = RC5_BIT_LEN;\r
1954 has_stop_bit = RC5_STOP_BIT;\r
1955 complete_data_len = RC5_COMPLETE_DATA_LEN;\r
1956 n_auto_repetitions = 1; // 1 frame\r
1957 auto_repetition_pause_len = 0;\r
1958 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;\r
1959 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1960 break;\r
1961 }\r
4225a882 1962#endif\r
9547ee89 1963#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 1964 case IRMP_RC6_PROTOCOL:\r
1965 {\r
1966 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
1967 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
1968 pulse_len = RC6_BIT_LEN;\r
1969 pause_len = RC6_BIT_LEN;\r
1970 has_stop_bit = RC6_STOP_BIT;\r
1971 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;\r
1972 n_auto_repetitions = 1; // 1 frame\r
1973 auto_repetition_pause_len = 0;\r
1974 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
1975 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1976 break;\r
1977 }\r
9547ee89 1978#endif\r
1979#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 1980 case IRMP_RC6A_PROTOCOL:\r
1981 {\r
1982 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;\r
1983 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;\r
1984 pulse_len = RC6_BIT_LEN;\r
1985 pause_len = RC6_BIT_LEN;\r
1986 has_stop_bit = RC6_STOP_BIT;\r
1987 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;\r
1988 n_auto_repetitions = 1; // 1 frame\r
1989 auto_repetition_pause_len = 0;\r
1990 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;\r
1991 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
1992 break;\r
1993 }\r
9547ee89 1994#endif\r
4225a882 1995#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 1996 case IRMP_DENON_PROTOCOL:\r
1997 {\r
1998 startbit_pulse_len = 0x00;\r
1999 startbit_pause_len = 0x00;\r
2000 pulse_1_len = DENON_PULSE_LEN;\r
2001 pause_1_len = DENON_1_PAUSE_LEN - 1;\r
2002 pulse_0_len = DENON_PULSE_LEN;\r
2003 pause_0_len = DENON_0_PAUSE_LEN - 1;\r
2004 has_stop_bit = DENON_STOP_BIT;\r
2005 complete_data_len = DENON_COMPLETE_DATA_LEN;\r
2006 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command\r
2007 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame\r
2008 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;\r
2009 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better\r
2010 break;\r
2011 }\r
4225a882 2012#endif\r
beda975f 2013#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 2014 case IRMP_THOMSON_PROTOCOL:\r
2015 {\r
2016 startbit_pulse_len = 0x00;\r
2017 startbit_pause_len = 0x00;\r
2018 pulse_1_len = THOMSON_PULSE_LEN;\r
2019 pause_1_len = THOMSON_1_PAUSE_LEN - 1;\r
2020 pulse_0_len = THOMSON_PULSE_LEN;\r
2021 pause_0_len = THOMSON_0_PAUSE_LEN - 1;\r
2022 has_stop_bit = THOMSON_STOP_BIT;\r
2023 complete_data_len = THOMSON_COMPLETE_DATA_LEN;\r
2024 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame\r
2025 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;\r
2026 repeat_frame_pause_len = THOMSON_FRAME_REPEAT_PAUSE_LEN;\r
2027 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2028 break;\r
2029 }\r
95b27043 2030#endif\r
2031#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 2032 case IRMP_BOSE_PROTOCOL:\r
2033 {\r
2034 startbit_pulse_len = BOSE_START_BIT_PULSE_LEN;\r
2035 startbit_pause_len = BOSE_START_BIT_PAUSE_LEN - 1;\r
2036 pulse_1_len = BOSE_PULSE_LEN;\r
2037 pause_1_len = BOSE_1_PAUSE_LEN - 1;\r
2038 pulse_0_len = BOSE_PULSE_LEN;\r
2039 pause_0_len = BOSE_0_PAUSE_LEN - 1;\r
2040 has_stop_bit = BOSE_STOP_BIT;\r
2041 complete_data_len = BOSE_COMPLETE_DATA_LEN;\r
2042 n_auto_repetitions = BOSE_FRAMES; // 1 frame\r
2043 auto_repetition_pause_len = BOSE_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause\r
2044 repeat_frame_pause_len = BOSE_FRAME_REPEAT_PAUSE_LEN;\r
2045 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2046 break;\r
2047 }\r
beda975f 2048#endif\r
4225a882 2049#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 2050 case IRMP_NUBERT_PROTOCOL:\r
2051 {\r
2052 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;\r
2053 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;\r
2054 pulse_1_len = NUBERT_1_PULSE_LEN;\r
2055 pause_1_len = NUBERT_1_PAUSE_LEN - 1;\r
2056 pulse_0_len = NUBERT_0_PULSE_LEN;\r
2057 pause_0_len = NUBERT_0_PAUSE_LEN - 1;\r
2058 has_stop_bit = NUBERT_STOP_BIT;\r
2059 complete_data_len = NUBERT_COMPLETE_DATA_LEN;\r
2060 n_auto_repetitions = NUBERT_FRAMES; // 2 frames\r
2061 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2062 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;\r
2063 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2064 break;\r
2065 }\r
5481e9cd 2066#endif\r
0715cf5e 2067#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 2068 case IRMP_FAN_PROTOCOL:\r
2069 {\r
2070 startbit_pulse_len = FAN_START_BIT_PULSE_LEN;\r
2071 startbit_pause_len = FAN_START_BIT_PAUSE_LEN - 1;\r
2072 pulse_1_len = FAN_1_PULSE_LEN;\r
2073 pause_1_len = FAN_1_PAUSE_LEN - 1;\r
2074 pulse_0_len = FAN_0_PULSE_LEN;\r
2075 pause_0_len = FAN_0_PAUSE_LEN - 1;\r
2076 has_stop_bit = FAN_STOP_BIT;\r
2077 complete_data_len = FAN_COMPLETE_DATA_LEN;\r
2078 n_auto_repetitions = FAN_FRAMES; // only 1 frame\r
2079 auto_repetition_pause_len = FAN_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2080 repeat_frame_pause_len = FAN_FRAME_REPEAT_PAUSE_LEN;\r
2081 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2082 break;\r
2083 }\r
0715cf5e 2084#endif\r
15dd9c32 2085#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 2086 case IRMP_SPEAKER_PROTOCOL:\r
2087 {\r
2088 startbit_pulse_len = SPEAKER_START_BIT_PULSE_LEN;\r
2089 startbit_pause_len = SPEAKER_START_BIT_PAUSE_LEN - 1;\r
2090 pulse_1_len = SPEAKER_1_PULSE_LEN;\r
2091 pause_1_len = SPEAKER_1_PAUSE_LEN - 1;\r
2092 pulse_0_len = SPEAKER_0_PULSE_LEN;\r
2093 pause_0_len = SPEAKER_0_PAUSE_LEN - 1;\r
2094 has_stop_bit = SPEAKER_STOP_BIT;\r
2095 complete_data_len = SPEAKER_COMPLETE_DATA_LEN;\r
2096 n_auto_repetitions = SPEAKER_FRAMES; // 2 frames\r
2097 auto_repetition_pause_len = SPEAKER_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause\r
2098 repeat_frame_pause_len = SPEAKER_FRAME_REPEAT_PAUSE_LEN;\r
2099 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2100 break;\r
2101 }\r
15dd9c32 2102#endif\r
5481e9cd 2103#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2104 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
2105 {\r
2106 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;\r
2107 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;\r
2108 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;\r
2109 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;\r
2110 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;\r
2111 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;\r
2112 has_stop_bit = BANG_OLUFSEN_STOP_BIT;\r
2113 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;\r
2114 n_auto_repetitions = 1; // 1 frame\r
2115 auto_repetition_pause_len = 0;\r
2116 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;\r
2117 last_bit_value = 0;\r
2118 irsnd_set_freq (IRSND_FREQ_455_KHZ);\r
2119 break;\r
2120 }\r
5b437ff6 2121#endif\r
2122#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 2123 case IRMP_GRUNDIG_PROTOCOL:\r
2124 {\r
2125 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2126 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2127 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2128 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2129 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2130 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;\r
2131 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames\r
2132 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
2133 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2134 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2135 break;\r
2136 }\r
a48187fa 2137#endif\r
2138#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 2139 case IRMP_IR60_PROTOCOL:\r
2140 {\r
2141 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2142 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2143 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2144 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2145 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2146 complete_data_len = IR60_COMPLETE_DATA_LEN;\r
2147 n_auto_repetitions = IR60_FRAMES; // 2 frames\r
2148 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause\r
2149 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2150 irsnd_set_freq (IRSND_FREQ_30_KHZ);\r
2151 break;\r
2152 }\r
d155e9ab 2153#endif\r
2154#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2155 case IRMP_NOKIA_PROTOCOL:\r
2156 {\r
2157 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2158 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;\r
2159 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2160 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2161 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;\r
2162 complete_data_len = NOKIA_COMPLETE_DATA_LEN;\r
2163 n_auto_repetitions = NOKIA_FRAMES; // 2 frames\r
2164 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause\r
2165 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause\r
2166 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2167 break;\r
2168 }\r
a7054daf 2169#endif\r
2170#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 2171 case IRMP_SIEMENS_PROTOCOL:\r
2172 {\r
2173 startbit_pulse_len = SIEMENS_BIT_LEN;\r
2174 startbit_pause_len = SIEMENS_BIT_LEN;\r
2175 pulse_len = SIEMENS_BIT_LEN;\r
2176 pause_len = SIEMENS_BIT_LEN;\r
2177 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
2178 complete_data_len = SIEMENS_COMPLETE_DATA_LEN;\r
2179 n_auto_repetitions = 1; // 1 frame\r
2180 auto_repetition_pause_len = 0;\r
2181 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;\r
2182 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2183 break;\r
2184 }\r
b5ea7869 2185#endif\r
cb93f9e9 2186#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 2187 case IRMP_RUWIDO_PROTOCOL:\r
2188 {\r
2189 startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;\r
2190 startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;\r
2191 pulse_len = RUWIDO_BIT_PULSE_LEN;\r
2192 pause_len = RUWIDO_BIT_PAUSE_LEN;\r
2193 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
2194 complete_data_len = RUWIDO_COMPLETE_DATA_LEN;\r
2195 n_auto_repetitions = 1; // 1 frame\r
2196 auto_repetition_pause_len = 0;\r
2197 repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;\r
2198 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
2199 break;\r
2200 }\r
cb93f9e9 2201#endif\r
48664931 2202#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 2203 case IRMP_FDC_PROTOCOL:\r
2204 {\r
2205 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;\r
2206 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;\r
2207 complete_data_len = FDC_COMPLETE_DATA_LEN;\r
2208 pulse_1_len = FDC_PULSE_LEN;\r
2209 pause_1_len = FDC_1_PAUSE_LEN - 1;\r
2210 pulse_0_len = FDC_PULSE_LEN;\r
2211 pause_0_len = FDC_0_PAUSE_LEN - 1;\r
2212 has_stop_bit = FDC_STOP_BIT;\r
2213 n_auto_repetitions = 1; // 1 frame\r
2214 auto_repetition_pause_len = 0;\r
2215 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;\r
2216 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2217 break;\r
2218 }\r
c7c9a4a1 2219#endif\r
2220#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 2221 case IRMP_RCCAR_PROTOCOL:\r
2222 {\r
2223 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;\r
2224 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;\r
2225 complete_data_len = RCCAR_COMPLETE_DATA_LEN;\r
2226 pulse_1_len = RCCAR_PULSE_LEN;\r
2227 pause_1_len = RCCAR_1_PAUSE_LEN - 1;\r
2228 pulse_0_len = RCCAR_PULSE_LEN;\r
2229 pause_0_len = RCCAR_0_PAUSE_LEN - 1;\r
2230 has_stop_bit = RCCAR_STOP_BIT;\r
2231 n_auto_repetitions = 1; // 1 frame\r
2232 auto_repetition_pause_len = 0;\r
2233 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;\r
2234 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2235 break;\r
2236 }\r
4225a882 2237#endif\r
c7a47e89 2238#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 2239 case IRMP_JVC_PROTOCOL:\r
2240 {\r
2241 if (repeat_counter != 0) // skip start bit if repetition frame\r
2242 {\r
2243 current_bit = 0;\r
2244 }\r
2245\r
2246 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;\r
2247 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;\r
2248 complete_data_len = JVC_COMPLETE_DATA_LEN;\r
2249 pulse_1_len = JVC_PULSE_LEN;\r
2250 pause_1_len = JVC_1_PAUSE_LEN - 1;\r
2251 pulse_0_len = JVC_PULSE_LEN;\r
2252 pause_0_len = JVC_0_PAUSE_LEN - 1;\r
2253 has_stop_bit = JVC_STOP_BIT;\r
2254 n_auto_repetitions = 1; // 1 frame\r
2255 auto_repetition_pause_len = 0;\r
2256 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;\r
2257 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2258 break;\r
2259 }\r
c7a47e89 2260#endif\r
9405f84a 2261#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 2262 case IRMP_NIKON_PROTOCOL:\r
2263 {\r
2264 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;\r
2265 startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;\r
2266 complete_data_len = NIKON_COMPLETE_DATA_LEN;\r
2267 pulse_1_len = NIKON_PULSE_LEN;\r
2268 pause_1_len = NIKON_1_PAUSE_LEN - 1;\r
2269 pulse_0_len = NIKON_PULSE_LEN;\r
2270 pause_0_len = NIKON_0_PAUSE_LEN - 1;\r
2271 has_stop_bit = NIKON_STOP_BIT;\r
2272 n_auto_repetitions = 1; // 1 frame\r
2273 auto_repetition_pause_len = 0;\r
2274 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;\r
2275 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2276 break;\r
2277 }\r
9405f84a 2278#endif\r
f50e01e7 2279#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 2280 case IRMP_LEGO_PROTOCOL:\r
2281 {\r
2282 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;\r
2283 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;\r
2284 complete_data_len = LEGO_COMPLETE_DATA_LEN;\r
2285 pulse_1_len = LEGO_PULSE_LEN;\r
2286 pause_1_len = LEGO_1_PAUSE_LEN - 1;\r
2287 pulse_0_len = LEGO_PULSE_LEN;\r
2288 pause_0_len = LEGO_0_PAUSE_LEN - 1;\r
2289 has_stop_bit = LEGO_STOP_BIT;\r
2290 n_auto_repetitions = 1; // 1 frame\r
2291 auto_repetition_pause_len = 0;\r
2292 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;\r
2293 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2294 break;\r
2295 }\r
fa09ce10 2296#endif\r
2297#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2298 case IRMP_A1TVBOX_PROTOCOL:\r
2299 {\r
2300 startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN\r
2301 startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN\r
2302 pulse_len = A1TVBOX_BIT_PULSE_LEN;\r
2303 pause_len = A1TVBOX_BIT_PAUSE_LEN;\r
2304 has_stop_bit = A1TVBOX_STOP_BIT;\r
2305 complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data\r
2306 n_auto_repetitions = 1; // 1 frame\r
2307 auto_repetition_pause_len = 0;\r
2308 repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;\r
2309 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2310 break;\r
2311 }\r
c9b6916a 2312#endif\r
2313#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 2314 case IRMP_ROOMBA_PROTOCOL:\r
2315 {\r
2316 startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;\r
2317 startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;\r
2318 pulse_1_len = ROOMBA_1_PULSE_LEN;\r
2319 pause_1_len = ROOMBA_1_PAUSE_LEN - 1;\r
2320 pulse_0_len = ROOMBA_0_PULSE_LEN;\r
2321 pause_0_len = ROOMBA_0_PAUSE_LEN - 1;\r
2322 has_stop_bit = ROOMBA_STOP_BIT;\r
2323 complete_data_len = ROOMBA_COMPLETE_DATA_LEN;\r
2324 n_auto_repetitions = ROOMBA_FRAMES; // 8 frames\r
2325 auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
2326 repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
2327 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2328 break;\r
2329 }\r
003c1008 2330#endif\r
2331#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 2332 case IRMP_PENTAX_PROTOCOL:\r
2333 {\r
2334 startbit_pulse_len = PENTAX_START_BIT_PULSE_LEN;\r
2335 startbit_pause_len = PENTAX_START_BIT_PAUSE_LEN;\r
2336 complete_data_len = PENTAX_COMPLETE_DATA_LEN;\r
2337 pulse_1_len = PENTAX_PULSE_LEN;\r
2338 pause_1_len = PENTAX_1_PAUSE_LEN - 1;\r
2339 pulse_0_len = PENTAX_PULSE_LEN;\r
2340 pause_0_len = PENTAX_0_PAUSE_LEN - 1;\r
2341 has_stop_bit = PENTAX_STOP_BIT;\r
2342 n_auto_repetitions = 1; // 1 frame\r
2343 auto_repetition_pause_len = 0;\r
2344 repeat_frame_pause_len = PENTAX_FRAME_REPEAT_PAUSE_LEN;\r
2345 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2346 break;\r
2347 }\r
43c535be 2348#endif\r
2349#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
df24bb50 2350 case IRMP_ACP24_PROTOCOL:\r
2351 {\r
2352 startbit_pulse_len = ACP24_START_BIT_PULSE_LEN;\r
2353 startbit_pause_len = ACP24_START_BIT_PAUSE_LEN - 1;\r
2354 complete_data_len = ACP24_COMPLETE_DATA_LEN;\r
2355 pulse_1_len = ACP24_PULSE_LEN;\r
2356 pause_1_len = ACP24_1_PAUSE_LEN - 1;\r
2357 pulse_0_len = ACP24_PULSE_LEN;\r
2358 pause_0_len = ACP24_0_PAUSE_LEN - 1;\r
2359 has_stop_bit = ACP24_STOP_BIT;\r
2360 n_auto_repetitions = 1; // 1 frame\r
2361 auto_repetition_pause_len = 0;\r
2362 repeat_frame_pause_len = ACP24_FRAME_REPEAT_PAUSE_LEN;\r
2363 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
2364 break;\r
2365 }\r
2366#endif\r
2367 default:\r
2368 {\r
2369 irsnd_busy = FALSE;\r
2370 break;\r
2371 }\r
2372 }\r
2373 }\r
2374 }\r
2375\r
2376 if (irsnd_busy)\r
2377 {\r
2378 new_frame = FALSE;\r
2379\r
2380 switch (irsnd_protocol)\r
2381 {\r
4225a882 2382#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
df24bb50 2383 case IRMP_SIRCS_PROTOCOL:\r
4225a882 2384#endif\r
2385#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
df24bb50 2386 case IRMP_NEC_PROTOCOL:\r
4225a882 2387#endif\r
7644ac04 2388#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 2389 case IRMP_NEC16_PROTOCOL:\r
7644ac04 2390#endif\r
2391#if IRSND_SUPPORT_NEC42_PROTOCOL == 1\r
df24bb50 2392 case IRMP_NEC42_PROTOCOL:\r
7644ac04 2393#endif\r
c1dfa01f 2394#if IRSND_SUPPORT_LGAIR_PROTOCOL == 1\r
df24bb50 2395 case IRMP_LGAIR_PROTOCOL:\r
c1dfa01f 2396#endif\r
4225a882 2397#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 2398 case IRMP_SAMSUNG_PROTOCOL:\r
2399 case IRMP_SAMSUNG32_PROTOCOL:\r
4225a882 2400#endif\r
ac8504f8 2401#if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1\r
df24bb50 2402 case IRMP_SAMSUNG48_PROTOCOL:\r
ac8504f8 2403#endif\r
4225a882 2404#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 2405 case IRMP_MATSUSHITA_PROTOCOL:\r
4225a882 2406#endif\r
3d2da98a 2407#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
df24bb50 2408 case IRMP_TECHNICS_PROTOCOL:\r
3d2da98a 2409#endif\r
770a1a9d 2410#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
df24bb50 2411 case IRMP_KASEIKYO_PROTOCOL:\r
95b27043 2412#endif\r
2413#if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1\r
df24bb50 2414 case IRMP_PANASONIC_PROTOCOL:\r
770a1a9d 2415#endif\r
4225a882 2416#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
df24bb50 2417 case IRMP_RECS80_PROTOCOL:\r
4225a882 2418#endif\r
2419#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
df24bb50 2420 case IRMP_RECS80EXT_PROTOCOL:\r
4225a882 2421#endif\r
9c07687e 2422#if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1\r
df24bb50 2423 case IRMP_TELEFUNKEN_PROTOCOL:\r
9c07687e 2424#endif\r
4225a882 2425#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
df24bb50 2426 case IRMP_DENON_PROTOCOL:\r
95b27043 2427#endif\r
2428#if IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
df24bb50 2429 case IRMP_BOSE_PROTOCOL:\r
4225a882 2430#endif\r
2431#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
df24bb50 2432 case IRMP_NUBERT_PROTOCOL:\r
5481e9cd 2433#endif\r
0715cf5e 2434#if IRSND_SUPPORT_FAN_PROTOCOL == 1\r
df24bb50 2435 case IRMP_FAN_PROTOCOL:\r
0715cf5e 2436#endif\r
15dd9c32 2437#if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1\r
df24bb50 2438 case IRMP_SPEAKER_PROTOCOL:\r
15dd9c32 2439#endif\r
5481e9cd 2440#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2441 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
4225a882 2442#endif\r
c7c9a4a1 2443#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 2444 case IRMP_FDC_PROTOCOL:\r
b5ea7869 2445#endif\r
c7c9a4a1 2446#if IRSND_SUPPORT_RCCAR_PROTOCOL == 1\r
df24bb50 2447 case IRMP_RCCAR_PROTOCOL:\r
c7c9a4a1 2448#endif\r
c7a47e89 2449#if IRSND_SUPPORT_JVC_PROTOCOL == 1\r
df24bb50 2450 case IRMP_JVC_PROTOCOL:\r
c7a47e89 2451#endif\r
9405f84a 2452#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
df24bb50 2453 case IRMP_NIKON_PROTOCOL:\r
9405f84a 2454#endif\r
f50e01e7 2455#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
df24bb50 2456 case IRMP_LEGO_PROTOCOL:\r
f50e01e7 2457#endif\r
cb93f9e9 2458#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
df24bb50 2459 case IRMP_THOMSON_PROTOCOL:\r
cb93f9e9 2460#endif\r
c9b6916a 2461#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
df24bb50 2462 case IRMP_ROOMBA_PROTOCOL:\r
c9b6916a 2463#endif\r
003c1008 2464#if IRSND_SUPPORT_PENTAX_PROTOCOL == 1\r
df24bb50 2465 case IRMP_PENTAX_PROTOCOL:\r
003c1008 2466#endif\r
43c535be 2467#if IRSND_SUPPORT_ACP24_PROTOCOL == 1\r
df24bb50 2468 case IRMP_ACP24_PROTOCOL:\r
43c535be 2469#endif\r
a7054daf 2470\r
7644ac04 2471#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \\r
3d2da98a 2472 IRSND_SUPPORT_LGAIR_PROTOCOL == 1 || IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || IRSND_SUPPORT_TECHNICS_PROTOCOL == 1 || \\r
770a1a9d 2473 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \\r
0715cf5e 2474 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_FAN_PROTOCOL == 1 || IRSND_SUPPORT_SPEAKER_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \\r
2475 IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || \\r
2476 IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || IRSND_SUPPORT_ROOMBA_PROTOCOL == 1 || IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1 || \\r
df24bb50 2477 IRSND_SUPPORT_PENTAX_PROTOCOL == 1 || IRSND_SUPPORT_ACP24_PROTOCOL == 1 || IRSND_SUPPORT_PANASONIC_PROTOCOL == 1 || IRSND_SUPPORT_BOSE_PROTOCOL == 1\r
2478 {\r
2479 if (pulse_counter == 0)\r
2480 {\r
2481 if (current_bit == 0xFF) // send start bit\r
2482 {\r
2483 pulse_len = startbit_pulse_len;\r
2484 pause_len = startbit_pause_len;\r
2485 }\r
2486 else if (current_bit < complete_data_len) // send n'th bit\r
2487 {\r
5481e9cd 2488#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
df24bb50 2489 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)\r
2490 {\r
2491 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits\r
2492 {\r
2493 pulse_len = SAMSUNG_PULSE_LEN;\r
2494 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?\r
2495 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
2496 }\r
2497 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)\r
2498 {\r
2499 pulse_len = SAMSUNG_PULSE_LEN;\r
2500 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;\r
2501 }\r
2502 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit\r
2503 {\r
2504 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
2505\r
2506 pulse_len = SAMSUNG_PULSE_LEN;\r
2507 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?\r
2508 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);\r
2509 }\r
2510 }\r
2511 else\r
5481e9cd 2512#endif\r
2513\r
7644ac04 2514#if IRSND_SUPPORT_NEC16_PROTOCOL == 1\r
df24bb50 2515 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)\r
2516 {\r
2517 if (current_bit < NEC16_ADDRESS_LEN) // send address bits\r
2518 {\r
2519 pulse_len = NEC_PULSE_LEN;\r
2520 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?\r
2521 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
2522 }\r
2523 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)\r
2524 {\r
2525 pulse_len = NEC_PULSE_LEN;\r
2526 pause_len = NEC_START_BIT_PAUSE_LEN - 1;\r
2527 }\r
2528 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit\r
2529 {\r
2530 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
2531\r
2532 pulse_len = NEC_PULSE_LEN;\r
2533 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?\r
2534 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);\r
2535 }\r
2536 }\r
2537 else\r
7644ac04 2538#endif\r
2539\r
5481e9cd 2540#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
df24bb50 2541 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)\r
2542 {\r
2543 if (current_bit == 0) // send 2nd start bit\r
2544 {\r
2545 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
2546 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
2547 }\r
2548 else if (current_bit == 1) // send 3rd start bit\r
2549 {\r
2550 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;\r
2551 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;\r
2552 }\r
2553 else if (current_bit == 2) // send 4th start bit\r
2554 {\r
2555 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
2556 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;\r
2557 }\r
2558 else if (current_bit == 19) // send trailer bit\r
2559 {\r
2560 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
2561 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;\r
2562 }\r
2563 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit\r
2564 {\r
2565 uint8_t cur_bit_value = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? 1 : 0;\r
2566 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
2567\r
2568 if (cur_bit_value == last_bit_value)\r
2569 {\r
2570 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;\r
2571 }\r
2572 else\r
2573 {\r
2574 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);\r
2575 last_bit_value = cur_bit_value;\r
2576 }\r
2577 }\r
2578 }\r
2579 else\r
2580#endif\r
2581 if (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7))))\r
2582 {\r
2583 pulse_len = pulse_1_len;\r
2584 pause_len = pause_1_len;\r
2585 }\r
2586 else\r
2587 {\r
2588 pulse_len = pulse_0_len;\r
2589 pause_len = pause_0_len;\r
2590 }\r
2591 }\r
2592 else if (has_stop_bit) // send stop bit\r
2593 {\r
2594 pulse_len = pulse_0_len;\r
2595\r
2596 if (auto_repetition_counter < n_auto_repetitions)\r
2597 {\r
2598 pause_len = pause_0_len;\r
2599 }\r
2600 else\r
2601 {\r
2602 pause_len = 255; // last frame: pause of 255\r
2603 }\r
2604 }\r
2605 }\r
2606\r
2607 if (pulse_counter < pulse_len)\r
2608 {\r
2609 if (pulse_counter == 0)\r
2610 {\r
2611 irsnd_on ();\r
2612 }\r
2613 pulse_counter++;\r
2614 }\r
2615 else if (pause_counter < pause_len)\r
2616 {\r
2617 if (pause_counter == 0)\r
2618 {\r
2619 irsnd_off ();\r
2620 }\r
2621 pause_counter++;\r
2622 }\r
2623 else\r
2624 {\r
2625 current_bit++;\r
2626\r
2627 if (current_bit >= complete_data_len + has_stop_bit)\r
2628 {\r
2629 current_bit = 0xFF;\r
2630 auto_repetition_counter++;\r
2631\r
2632 if (auto_repetition_counter == n_auto_repetitions)\r
2633 {\r
2634 irsnd_busy = FALSE;\r
2635 auto_repetition_counter = 0;\r
2636 }\r
2637 new_frame = TRUE;\r
2638 }\r
2639\r
2640 pulse_counter = 0;\r
2641 pause_counter = 0;\r
2642 }\r
2643 break;\r
2644 }\r
a7054daf 2645#endif\r
2646\r
4225a882 2647#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
df24bb50 2648 case IRMP_RC5_PROTOCOL:\r
a7054daf 2649#endif\r
9547ee89 2650#if IRSND_SUPPORT_RC6_PROTOCOL == 1\r
df24bb50 2651 case IRMP_RC6_PROTOCOL:\r
9547ee89 2652#endif\r
2653#if IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2654 case IRMP_RC6A_PROTOCOL:\r
9547ee89 2655#endif\r
a7054daf 2656#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
df24bb50 2657 case IRMP_SIEMENS_PROTOCOL:\r
a7054daf 2658#endif\r
cb93f9e9 2659#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
df24bb50 2660 case IRMP_RUWIDO_PROTOCOL:\r
cb93f9e9 2661#endif\r
a7054daf 2662#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
df24bb50 2663 case IRMP_GRUNDIG_PROTOCOL:\r
a7054daf 2664#endif\r
a48187fa 2665#if IRSND_SUPPORT_IR60_PROTOCOL == 1\r
df24bb50 2666 case IRMP_IR60_PROTOCOL:\r
a48187fa 2667#endif\r
a7054daf 2668#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2669 case IRMP_NOKIA_PROTOCOL:\r
fa09ce10 2670#endif\r
2671#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2672 case IRMP_A1TVBOX_PROTOCOL:\r
a7054daf 2673#endif\r
4225a882 2674\r
cb93f9e9 2675#if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \\r
2676 IRSND_SUPPORT_RC6_PROTOCOL == 1 || \\r
2677 IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \\r
2678 IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \\r
2679 IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r
2680 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \\r
2681 IRSND_SUPPORT_IR60_PROTOCOL == 1 || \\r
2682 IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \\r
2683 IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2684 {\r
2685 if (pulse_counter == pulse_len && pause_counter == pause_len)\r
2686 {\r
2687 current_bit++;\r
4225a882 2688\r
df24bb50 2689 if (current_bit >= complete_data_len)\r
2690 {\r
2691 current_bit = 0xFF;\r
a7054daf 2692\r
a48187fa 2693#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2694 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
2695 {\r
2696 auto_repetition_counter++;\r
2697\r
2698 if (repeat_counter > 0)\r
2699 { // set 117 msec pause time\r
2700 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;\r
2701 }\r
2702\r
2703 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame\r
2704 {\r
2705 n_auto_repetitions++; // increment number of auto repetitions\r
2706 repeat_counter++;\r
2707 }\r
2708 else if (auto_repetition_counter == n_auto_repetitions)\r
2709 {\r
2710 irsnd_busy = FALSE;\r
2711 auto_repetition_counter = 0;\r
2712 }\r
2713 }\r
2714 else\r
2715#endif\r
2716 {\r
2717 irsnd_busy = FALSE;\r
2718 }\r
2719\r
2720 new_frame = TRUE;\r
2721 irsnd_off ();\r
2722 }\r
2723\r
2724 pulse_counter = 0;\r
2725 pause_counter = 0;\r
2726 }\r
2727\r
2728 if (! new_frame)\r
2729 {\r
2730 uint8_t first_pulse;\r
5b437ff6 2731\r
a48187fa 2732#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
df24bb50 2733 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)\r
2734 {\r
2735 if (current_bit == 0xFF || // start bit of start-frame\r
2736 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)\r
2737 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)\r
2738 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)\r
2739 {\r
2740 pulse_len = startbit_pulse_len;\r
2741 pause_len = startbit_pause_len;\r
2742 first_pulse = TRUE;\r
2743 }\r
2744 else // send n'th bit\r
2745 {\r
2746 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2747 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;\r
2748 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;\r
2749 }\r
2750 }\r
2751 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||\r
2752 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)\r
2753#endif\r
2754 {\r
2755 if (current_bit == 0xFF) // 1 start bit\r
2756 {\r
9547ee89 2757#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2758 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2759 {\r
2760 pulse_len = startbit_pulse_len;\r
2761 pause_len = startbit_pause_len;\r
2762 }\r
2763 else\r
fa09ce10 2764#endif\r
2765#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
df24bb50 2766 if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)\r
2767 {\r
2768 current_bit = 0;\r
2769 }\r
2770 else\r
2771#endif\r
2772 {\r
2773 ;\r
2774 }\r
2775\r
2776 first_pulse = TRUE;\r
2777 }\r
2778 else // send n'th bit\r
2779 {\r
9547ee89 2780#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1\r
df24bb50 2781 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2782 {\r
2783 pulse_len = RC6_BIT_LEN;\r
2784 pause_len = RC6_BIT_LEN;\r
2785\r
2786 if (irsnd_protocol == IRMP_RC6_PROTOCOL)\r
2787 {\r
2788 if (current_bit == 4) // toggle bit (double len)\r
2789 {\r
2790 pulse_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN\r
2791 pause_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN\r
2792 }\r
2793 }\r
2794 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)\r
2795 {\r
2796 if (current_bit == 4) // toggle bit (double len)\r
2797 {\r
2798 pulse_len = RC6_BIT_3_LEN; // = 3 * RC6_BIT_LEN\r
2799 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN\r
2800 }\r
2801 else if (current_bit == 5) // toggle bit (double len)\r
2802 {\r
2803 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN\r
2804 }\r
2805 }\r
2806 }\r
2807#endif\r
2808 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;\r
2809 }\r
2810\r
2811 if (irsnd_protocol == IRMP_RC5_PROTOCOL)\r
2812 {\r
2813 first_pulse = first_pulse ? FALSE : TRUE;\r
2814 }\r
2815 }\r
2816\r
2817 if (first_pulse)\r
2818 {\r
2819 // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
2820\r
2821 if (pulse_counter < pulse_len)\r
2822 {\r
2823 if (pulse_counter == 0)\r
2824 {\r
2825 irsnd_on ();\r
2826 }\r
2827 pulse_counter++;\r
2828 }\r
2829 else // if (pause_counter < pause_len)\r
2830 {\r
2831 if (pause_counter == 0)\r
2832 {\r
2833 irsnd_off ();\r
2834 }\r
2835 pause_counter++;\r
2836 }\r
2837 }\r
2838 else\r
2839 {\r
2840 // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
2841\r
2842 if (pause_counter < pause_len)\r
2843 {\r
2844 if (pause_counter == 0)\r
2845 {\r
2846 irsnd_off ();\r
2847 }\r
2848 pause_counter++;\r
2849 }\r
2850 else // if (pulse_counter < pulse_len)\r
2851 {\r
2852 if (pulse_counter == 0)\r
2853 {\r
2854 irsnd_on ();\r
2855 }\r
2856 pulse_counter++;\r
2857 }\r
2858 }\r
2859 }\r
2860 break;\r
2861 }\r
9547ee89 2862#endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||\r
cb93f9e9 2863 // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
5b437ff6 2864\r
df24bb50 2865 default:\r
2866 {\r
2867 irsnd_busy = FALSE;\r
2868 break;\r
2869 }\r
2870 }\r
2871 }\r
2872\r
2873 if (! irsnd_busy)\r
2874 {\r
2875 if (repeat_counter < n_repeat_frames)\r
2876 {\r
c7c9a4a1 2877#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
df24bb50 2878 if (irsnd_protocol == IRMP_FDC_PROTOCOL)\r
2879 {\r
2880 irsnd_buffer[2] |= 0x0F;\r
2881 }\r
2882#endif\r
2883 repeat_counter++;\r
2884 irsnd_busy = TRUE;\r
2885 }\r
2886 else\r
2887 {\r
2888 irsnd_busy = TRUE; //Rainer\r
2889 send_trailer = TRUE;\r
2890 n_repeat_frames = 0;\r
2891 repeat_counter = 0;\r
2892 }\r
2893 }\r
4225a882 2894 }\r
2895\r
cb93f9e9 2896#ifdef ANALYZE\r
4225a882 2897 if (irsnd_is_on)\r
2898 {\r
df24bb50 2899 putchar ('0');\r
4225a882 2900 }\r
2901 else\r
2902 {\r
df24bb50 2903 putchar ('1');\r
4225a882 2904 }\r
2905#endif\r
2906\r
2907 return irsnd_busy;\r
2908}\r
2909\r
cb93f9e9 2910#ifdef ANALYZE\r
4225a882 2911\r
2912// main function - for unix/linux + windows only!\r
2913// AVR: see main.c!\r
2914// Compile it under linux with:\r
2915// cc irsnd.c -o irsnd\r
2916//\r
2917// usage: ./irsnd protocol hex-address hex-command >filename\r
2918\r
2919int\r
2920main (int argc, char ** argv)\r
2921{\r
4225a882 2922 int protocol;\r
2923 int address;\r
2924 int command;\r
4225a882 2925 IRMP_DATA irmp_data;\r
2926\r
a7054daf 2927 if (argc != 4 && argc != 5)\r
4225a882 2928 {\r
df24bb50 2929 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);\r
2930 return 1;\r
4225a882 2931 }\r
2932\r
2933 if (sscanf (argv[1], "%d", &protocol) == 1 &&\r
df24bb50 2934 sscanf (argv[2], "%x", &address) == 1 &&\r
2935 sscanf (argv[3], "%x", &command) == 1)\r
4225a882 2936 {\r
df24bb50 2937 irmp_data.protocol = protocol;\r
2938 irmp_data.address = address;\r
2939 irmp_data.command = command;\r
4225a882 2940\r
df24bb50 2941 if (argc == 5)\r
2942 {\r
2943 irmp_data.flags = atoi (argv[4]);\r
2944 }\r
2945 else\r
2946 {\r
2947 irmp_data.flags = 0;\r
2948 }\r
a7054daf 2949\r
df24bb50 2950 irsnd_init ();\r
4225a882 2951\r
df24bb50 2952 (void) irsnd_send_data (&irmp_data, TRUE);\r
4225a882 2953\r
df24bb50 2954 while (irsnd_busy)\r
2955 {\r
2956 irsnd_ISR ();\r
2957 }\r
beda975f 2958\r
df24bb50 2959 putchar ('\n');\r
a03ad359 2960\r
f874da09 2961#if 1 // enable here to send twice\r
df24bb50 2962 (void) irsnd_send_data (&irmp_data, TRUE);\r
a03ad359 2963\r
df24bb50 2964 while (irsnd_busy)\r
2965 {\r
2966 irsnd_ISR ();\r
2967 }\r
a03ad359 2968\r
df24bb50 2969 putchar ('\n');\r
f874da09 2970#endif\r
4225a882 2971 }\r
2972 else\r
2973 {\r
df24bb50 2974 fprintf (stderr, "%s: wrong arguments\n", argv[0]);\r
2975 return 1;\r
4225a882 2976 }\r
2977 return 0;\r
2978}\r
2979\r
cb93f9e9 2980#endif // ANALYZE\r
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)