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Commit | Line | Data |
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a16ba2b0 L |
1 | page 255\r |
2 | .z80\r | |
3 | \r | |
4 | extrn ddtz,bpent\r | |
5 | extrn $stack\r | |
30d1329e | 6 | extrn charini,?const,?conin\r |
8df5b655 | 7 | extrn ?cono,?conos\r |
a16ba2b0 L |
8 | extrn romend\r |
9 | \r | |
10 | \r | |
64cc2207 | 11 | global iobyte\r |
a16ba2b0 L |
12 | global isv_sw\r |
13 | \r | |
14 | include config.inc\r | |
fecee241 L |
15 | if CPU_Z180\r |
16 | include z180reg.inc\r | |
17 | include z180.lib\r | |
18 | endif\r | |
815c1735 | 19 | \r |
a16ba2b0 L |
20 | \r |
21 | \r | |
22 | \r | |
23 | ;----------------------------------------------------------------------\r | |
24 | \r | |
25 | cseg\r | |
8df5b655 | 26 | romstart equ $\r |
a16ba2b0 | 27 | \r |
8df5b655 | 28 | org romstart+0\r |
815c1735 | 29 | jp start\r |
a16ba2b0 | 30 | \r |
64cc2207 L |
31 | iobyte: db 2\r |
32 | \r | |
a16ba2b0 L |
33 | ; restart vectors\r |
34 | \r | |
35 | rsti defl 1\r | |
36 | rept 7\r | |
8df5b655 | 37 | org 8*rsti + romstart\r |
fecee241 L |
38 | jp bpent\r |
39 | rsti defl rsti+1\r | |
a16ba2b0 L |
40 | endm\r |
41 | \r | |
42 | ;----------------------------------------------------------------------\r | |
fecee241 L |
43 | ; Config space\r |
44 | ;\r | |
45 | \r | |
8df5b655 | 46 | org romstart+40h\r |
349c01b1 L |
47 | \r |
48 | dw 0\r | |
49 | db 0\r | |
50 | \r | |
a16ba2b0 | 51 | \r |
fecee241 L |
52 | if ROMSYS\r |
53 | $crom: defb c$rom ;\r | |
54 | else\r | |
55 | db 0 ;\r | |
56 | endif\r | |
a16ba2b0 | 57 | \r |
8df5b655 | 58 | INIWAITS defl CWAITIO\r |
fecee241 | 59 | if ROMSYS\r |
8df5b655 | 60 | INIWAITS defl INIWAITS+CWAITROM\r |
fecee241 | 61 | endif\r |
8df5b655 L |
62 | \r |
63 | ;----------------------------------------------------------------------\r | |
64 | \r | |
65 | org romstart+50h\r | |
66 | start:\r | |
67 | jp cstart\r | |
68 | jp wstart\r | |
69 | jp ?const\r | |
70 | jp ?conin\r | |
71 | jp ?cono\r | |
72 | jp ?conos\r | |
73 | jp charini\r | |
74 | \r | |
75 | ;----------------------------------------------------------------------\r | |
76 | \r | |
fecee241 L |
77 | hwini0:\r |
78 | if CPU_Z180\r | |
fecee241 L |
79 | db 3 ;count\r |
80 | db rcr,CREFSH ;configure DRAM refresh\r | |
81 | db dcntl,INIWAITS ;wait states\r | |
82 | db cbar,SYS$CBAR\r | |
fecee241 | 83 | endif\r |
2fe44122 | 84 | db 0\r |
fecee241 L |
85 | \r |
86 | if CPU_Z180\r | |
a16ba2b0 L |
87 | dmclrt: ;clear ram per dma\r |
88 | db dmct_e-dmclrt-2 ;\r | |
89 | db sar0l ;first port\r | |
815c1735 | 90 | dw nullbyte ;src (fixed)\r |
a16ba2b0 L |
91 | nullbyte:\r |
92 | db 000h ;src\r | |
93 | dw romend ;dst (inc), start after "rom" code\r | |
94 | db 00h ;dst\r | |
95 | dw 0-romend ;count (64k)\r | |
96 | dmct_e:\r | |
2fe44122 | 97 | db 0\r |
fecee241 L |
98 | endif\r |
99 | \r | |
a16ba2b0 | 100 | \r |
8df5b655 | 101 | cstart:\r |
fecee241 | 102 | if CPU_Z180\r |
a16ba2b0 | 103 | \r |
30d1329e L |
104 | push af\r |
105 | in0 a,(itc) ;Illegal opcode trap?\r | |
106 | jp m,??st01\r | |
107 | ld a,i ;I register == 0 ?\r | |
fecee241 | 108 | jr z,hw_reset ; yes, harware reset\r |
a16ba2b0 L |
109 | \r |
110 | ??st01:\r | |
fecee241 | 111 | ; TODO: SYS$CBR\r |
30d1329e L |
112 | ld a,(syscbr)\r |
113 | out0 (cbr),a\r | |
114 | pop af ;restore registers\r | |
30d1329e | 115 | jp bpent ;\r |
a16ba2b0 | 116 | \r |
fecee241 | 117 | hw_reset:\r |
a16ba2b0 L |
118 | di ;0058\r |
119 | ld a,CREFSH\r | |
120 | out0 (rcr),a ; configure DRAM refresh\r | |
121 | ld a,CWAITIO\r | |
122 | out0 (dcntl),a ; wait states\r | |
123 | \r | |
815c1735 L |
124 | ld a,M_NCD ;No Clock Divide\r |
125 | out0 (ccr),a\r | |
bad2d92d L |
126 | ; ld a,M_X2CM ;X2 Clock Multiplier\r |
127 | ; out0 (cmr),a\r | |
fecee241 | 128 | else\r |
8df5b655 L |
129 | di\r |
130 | xor a\r | |
131 | ld (@cbnk),a\r | |
fecee241 | 132 | endif\r |
815c1735 | 133 | \r |
fecee241 | 134 | ; check warm start mark\r |
a16ba2b0 | 135 | \r |
8df5b655 L |
136 | ld ix,mark_55AA ; top of common area\r |
137 | ld a,0aah ;\r | |
138 | cp (ix+000h) ;\r | |
139 | jr nz,kstart ;\r | |
140 | cp (ix+002h) ;\r | |
141 | jr nz,kstart ;\r | |
142 | cpl ;\r | |
143 | cp (ix+001h) ;\r | |
144 | jr nz,kstart ;\r | |
145 | cp (ix+003h) ;\r | |
146 | jr nz,kstart ;\r | |
147 | ld sp,$stack ; mark found, check\r | |
148 | jp z,wstart ; check ok,\r | |
fecee241 | 149 | \r |
a16ba2b0 L |
150 | ; ram not ok, initialize -- kstart --\r |
151 | \r | |
152 | kstart:\r | |
fecee241 L |
153 | if CPU_Z180\r |
154 | ld a,SYS$CBAR\r | |
155 | out0 (cbar),a\r | |
156 | ld a,SYS$CBR\r | |
8df5b655 | 157 | out0 (cbr),a\r |
fecee241 | 158 | endif\r |
a16ba2b0 | 159 | \r |
a16ba2b0 | 160 | ld sp,$stack ;01e1\r |
815c1735 | 161 | \r |
a16ba2b0 L |
162 | ; Clear RAM using DMA0\r |
163 | \r | |
fecee241 L |
164 | if CPU_Z180\r |
165 | if 0\r | |
8df5b655 | 166 | \r |
a16ba2b0 | 167 | ld hl,dmclrt ;load DMA registers\r |
2fe44122 | 168 | call ioiniml\r |
a16ba2b0 L |
169 | ld a,0cbh ;01ef dst +1, src fixed, burst\r |
170 | out0 (dmode),a ;01f1\r | |
171 | \r | |
172 | ld b,512/64\r | |
815c1735 | 173 | ld a,062h ;01f4 enable dma0,\r |
a16ba2b0 L |
174 | ??cl_1:\r |
175 | out0 (dstat),a ;01f9 clear (up to) 64k\r | |
176 | djnz ??cl_1 ; end of RAM?\r | |
8df5b655 | 177 | \r |
fecee241 L |
178 | endif\r |
179 | endif\r | |
a16ba2b0 L |
180 | \r |
181 | ld hl,055AAh ;set warm start mark\r | |
fecee241 L |
182 | ld (mark_55AA),hl\r |
183 | ld (mark_55AA+2),hl\r | |
184 | \r | |
185 | ; -- wstart --\r | |
a16ba2b0 | 186 | \r |
a16ba2b0 L |
187 | wstart:\r |
188 | call sysram_init ;027f\r | |
189 | call ivtab_init\r | |
fecee241 L |
190 | if CPU_Z180\r |
191 | call prt0_init\r | |
192 | endif\r | |
a16ba2b0 | 193 | \r |
30d1329e | 194 | call charini\r |
bad2d92d | 195 | call bufferinit\r |
a16ba2b0 | 196 | \r |
fecee241 L |
197 | if CPU_Z80\r |
198 | ld a,0\r | |
199 | call selbnk\r | |
200 | endif\r | |
a16ba2b0 L |
201 | \r |
202 | im 2 ;?030e\r | |
203 | ei ;0282\r | |
204 | \r | |
30d1329e L |
205 | call ?const ;0284\r |
206 | call ?const ;0287\r | |
a16ba2b0 | 207 | or a ;028a\r |
30d1329e | 208 | call nz,?conin ;028d\r |
815c1735 | 209 | \r |
fecee241 L |
210 | if CPU_Z180\r |
211 | ld e,0 ;Sys$Bank\r | |
212 | else\r | |
8df5b655 | 213 | ; TODO:\r |
fecee241 | 214 | endif\r |
a16ba2b0 | 215 | jp ddtz ;0290\r |
815c1735 | 216 | \r |
30d1329e | 217 | \r |
fecee241 | 218 | if CPU_Z180\r |
8df5b655 | 219 | ; TODO: SYS$CBR\r |
30d1329e | 220 | syscbr: db 1\r |
fecee241 | 221 | endif\r |
30d1329e | 222 | \r |
a16ba2b0 L |
223 | ;\r |
224 | ;----------------------------------------------------------------------\r | |
225 | ;\r | |
226 | \r | |
a16ba2b0 L |
227 | ;TODO: Make a ringbuffer module.\r |
228 | \r | |
229 | global buf.init\r | |
815c1735 | 230 | \r |
a16ba2b0 L |
231 | buf.init:\r |
232 | ld (ix+o.in_idx),0\r | |
233 | ld (ix+o.out_idx),0\r | |
234 | ld (ix+o.mask),a\r | |
235 | ret\r | |
236 | \r | |
349c01b1 | 237 | ;----------------------------------------------------------------------\r |
4caee1ec | 238 | \r |
6a4e9540 L |
239 | extrn msginit,msg.sout\r |
240 | extrn mtx.fifo,mrx.fifo\r | |
241 | extrn co.fifo,ci.fifo\r | |
4caee1ec L |
242 | \r |
243 | \r | |
a16ba2b0 | 244 | bufferinit:\r |
fecee241 L |
245 | if CPU_Z180\r |
246 | call msginit\r | |
815c1735 | 247 | \r |
a16ba2b0 | 248 | ld hl,buffers\r |
6a4e9540 | 249 | ld b,buftablen\r |
a16ba2b0 | 250 | bfi_1:\r |
6a4e9540 L |
251 | ld a,(hl)\r |
252 | inc hl\r | |
253 | ld (bufdat+0),a\r | |
a16ba2b0 L |
254 | ld e,(hl)\r |
255 | inc hl\r | |
256 | ld d,(hl)\r | |
257 | inc hl\r | |
2fa1a706 | 258 | ex de,hl\r |
6a4e9540 L |
259 | \r |
260 | or a\r | |
261 | jr nz,bfi_2\r | |
2fa1a706 | 262 | call hwl2phy\r |
6a4e9540 L |
263 | ld (40h+0),hl\r |
264 | ld (40h+2),a\r | |
2fa1a706 | 265 | out (AVRINT5),a\r |
6a4e9540 L |
266 | jr bfi_3 \r |
267 | bfi_2:\r | |
2fa1a706 | 268 | call hwl2phy\r |
a16ba2b0 L |
269 | ld (bufdat+1),hl\r |
270 | ld (bufdat+3),a\r | |
a16ba2b0 L |
271 | ld hl,inimsg\r |
272 | call msg.sout\r | |
6a4e9540 | 273 | bfi_3:\r |
2fa1a706 | 274 | ex de,hl\r |
a16ba2b0 L |
275 | djnz bfi_1\r |
276 | ret\r | |
fecee241 | 277 | \r |
2fa1a706 | 278 | else ;CPU_Z180\r |
fecee241 L |
279 | \r |
280 | call msginit\r | |
8df5b655 L |
281 | \r |
282 | ld hl,buffers\r | |
283 | ld b,buftablen\r | |
284 | bfi_1:\r | |
285 | ld a,(hl)\r | |
286 | inc hl\r | |
287 | ld (bufdat+0),a\r | |
288 | ld e,(hl)\r | |
289 | inc hl\r | |
290 | ld d,(hl)\r | |
291 | inc hl\r | |
292 | ex de,hl\r | |
293 | \r | |
294 | or a\r | |
295 | jr nz,bfi_2\r | |
296 | \r | |
297 | ld a,(@cbnk)\r | |
2fa1a706 | 298 | call bnk2phy\r |
8df5b655 L |
299 | \r |
300 | ld (40h+0),hl\r | |
301 | ld (40h+2),a\r | |
302 | out (AVRINT5),a\r | |
303 | jr bfi_3\r | |
304 | bfi_2:\r | |
305 | \r | |
306 | ld a,(@cbnk)\r | |
2fa1a706 | 307 | call bnk2phy\r |
8df5b655 L |
308 | \r |
309 | ld (bufdat+1),hl\r | |
310 | ld (bufdat+3),a\r | |
311 | ld hl,inimsg\r | |
312 | call msg.sout\r | |
313 | bfi_3:\r | |
314 | ex de,hl\r | |
315 | djnz bfi_1\r | |
316 | ret\r | |
fecee241 | 317 | endif\r |
a16ba2b0 | 318 | \r |
a16ba2b0 | 319 | buffers:\r |
6a4e9540 L |
320 | db 0\r |
321 | dw mtx.fifo\r | |
322 | db 1\r | |
323 | dw mrx.fifo\r | |
324 | db 2\r | |
325 | dw co.fifo\r | |
326 | db 3\r | |
327 | dw ci.fifo\r | |
328 | buftablen equ ($ - buffers)/3\r | |
815c1735 L |
329 | \r |
330 | inimsg:\r | |
6a4e9540 | 331 | db inimsg_e - $ -1\r |
3531528e | 332 | db 0AEh\r |
a16ba2b0 L |
333 | db inimsg_e - $ -1\r |
334 | db 0\r | |
335 | bufdat:\r | |
336 | db 0\r | |
337 | dw 0\r | |
338 | db 0\r | |
e598b357 | 339 | inimsg_e:\r |
a16ba2b0 | 340 | \r |
4caee1ec | 341 | \r |
a16ba2b0 L |
342 | ;\r |
343 | ;----------------------------------------------------------------------\r | |
344 | ;\r | |
345 | \r | |
346 | sysram_init:\r | |
347 | ld hl,sysramw\r | |
348 | ld de,topcodsys\r | |
349 | ld bc,sysrame-sysramw\r | |
350 | ldir\r | |
351 | \r | |
352 | ret\r | |
353 | \r | |
354 | ;----------------------------------------------------------------------\r | |
355 | \r | |
356 | ivtab_init:\r | |
357 | ld hl,ivtab ;\r | |
358 | ld a,h ;\r | |
359 | ld i,a ;\r | |
fecee241 | 360 | if CPU_Z180\r |
a16ba2b0 | 361 | out0 (il),l ;\r |
fecee241 | 362 | endif\r |
a16ba2b0 L |
363 | \r |
364 | ; Let all vectors point to spurious int routines.\r | |
365 | \r | |
366 | ld d,high sp.int0\r | |
367 | ld a,low sp.int0\r | |
368 | ld b,9\r | |
815c1735 | 369 | ivt_i1:\r |
a16ba2b0 L |
370 | ld (hl),a\r |
371 | inc l\r | |
372 | ld (hl),d\r | |
373 | inc l\r | |
374 | add a,sp.int.len\r | |
375 | djnz ivt_i1\r | |
376 | ret\r | |
377 | \r | |
4caee1ec | 378 | ;----------------------------------------------------------------------\r |
a16ba2b0 | 379 | \r |
fecee241 | 380 | if CPU_Z180\r |
a16ba2b0 L |
381 | prt0_init:\r |
382 | ld a,i\r | |
383 | ld h,a\r | |
384 | in0 a,(il)\r | |
385 | and 0E0h\r | |
386 | or IV$PRT0\r | |
387 | ld l,a\r | |
388 | ld (hl),low iprt0\r | |
389 | inc hl\r | |
390 | ld (hl),high iprt0\r | |
391 | ld hl,prt0itab\r | |
2fe44122 | 392 | call ioiniml\r |
a16ba2b0 | 393 | ret\r |
815c1735 | 394 | \r |
a16ba2b0 L |
395 | prt0itab:\r |
396 | db prt0it_e-prt0itab-2\r | |
397 | db tmdr0l\r | |
398 | dw PRT_TC10MS\r | |
399 | dw PRT_TC10MS\r | |
400 | db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.\r | |
401 | prt0it_e:\r | |
2fe44122 | 402 | db 0\r |
fecee241 | 403 | endif\r |
a16ba2b0 | 404 | \r |
4caee1ec | 405 | \r |
a16ba2b0 L |
406 | ;\r |
407 | ;----------------------------------------------------------------------\r | |
408 | ;\r | |
409 | \r | |
2fe44122 | 410 | if CPU_Z180\r |
a16ba2b0 | 411 | io.ini:\r |
2fe44122 | 412 | if 0\r |
a16ba2b0 L |
413 | push bc\r |
414 | ld b,0 ;high byte port adress\r | |
2fe44122 | 415 | ioi_nxt:\r |
a16ba2b0 L |
416 | ld a,(hl) ;count\r |
417 | inc hl\r | |
8df5b655 L |
418 | or a\r |
419 | jr z,ioi_e\r | |
2fe44122 | 420 | \r |
a16ba2b0 L |
421 | ld c,(hl) ;port address\r |
422 | inc hl\r | |
2fe44122 | 423 | ioi_r:\r |
a16ba2b0 L |
424 | outi\r |
425 | inc b ;outi decrements b\r | |
426 | dec a\r | |
2fe44122 L |
427 | jr nz,ioi_r\r |
428 | jr ioi_nxt\r | |
fecee241 | 429 | ioi_e: \r |
2fe44122 L |
430 | pop bc\r |
431 | ret\r | |
432 | \r | |
433 | else ;(if 1/0)\r | |
434 | \r | |
435 | push bc\r | |
436 | jr ioi_nxt\r | |
437 | ioi_l:\r | |
438 | ld c,(hl) ;port address\r | |
439 | inc hl\r | |
440 | inc c\r | |
441 | ioi_r:\r | |
442 | dec c ;otim increments c\r | |
443 | otim\r | |
444 | jr z,ioi_r\r | |
445 | ioi_nxt:\r | |
446 | ld b,(hl) ;count\r | |
447 | inc hl\r | |
448 | inc b ;stop if count == 0\r | |
449 | djnz ioi_l\r | |
450 | pop bc\r | |
451 | ret\r | |
452 | \r | |
453 | endif ;(1/0)\r | |
454 | \r | |
fecee241 | 455 | else\r |
2fe44122 L |
456 | \r |
457 | io.ini:\r | |
458 | push bc\r | |
8df5b655 L |
459 | jr ioi_nxt\r |
460 | ioi_l:\r | |
461 | ld c,(hl) ;port address\r | |
462 | inc hl\r | |
463 | otir\r | |
464 | ioi_nxt:\r | |
465 | ld b,(hl) ;count\r | |
466 | inc hl\r | |
467 | inc b\r | |
468 | djnz ioi_l\r | |
fecee241 | 469 | endif\r |
a16ba2b0 L |
470 | pop bc\r |
471 | ret\r | |
472 | \r | |
2fe44122 L |
473 | ;----------------------------------------------------------------------\r |
474 | \r | |
fecee241 | 475 | if CPU_Z180\r |
2fe44122 L |
476 | \r |
477 | global ioiniml\r | |
478 | \r | |
479 | ioiniml:\r | |
a16ba2b0 | 480 | push bc\r |
2fe44122 L |
481 | xor a\r |
482 | ioml_lp:\r | |
a16ba2b0 L |
483 | ld b,(hl)\r |
484 | inc hl\r | |
2fe44122 L |
485 | cp b\r |
486 | jr z,ioml_e\r | |
487 | \r | |
a16ba2b0 L |
488 | ld c,(hl)\r |
489 | inc hl\r | |
815c1735 | 490 | otimr\r |
2fe44122 L |
491 | jr ioml_lp\r |
492 | ioml_e:\r | |
815c1735 | 493 | pop bc\r |
2fe44122 | 494 | ret z\r |
fecee241 | 495 | endif\r |
815c1735 | 496 | \r |
a16ba2b0 L |
497 | io.ini.l:\r |
498 | ;\r | |
499 | \r | |
a16ba2b0 | 500 | \r |
a16ba2b0 | 501 | \r |
4caee1ec | 502 | ;----------------------------------------------------------------------\r |
a16ba2b0 | 503 | ;\r |
fecee241 | 504 | if CPU_Z180\r |
a16ba2b0 | 505 | \r |
2fa1a706 L |
506 | ;--------------------------------------------------------------------\r |
507 | ; Return the BBR value for the given bank number\r | |
fecee241 | 508 | ;\r |
2fa1a706 | 509 | ; in a: Bank number\r |
fecee241 | 510 | ; out a: bbr value\r |
a16ba2b0 | 511 | \r |
fecee241 | 512 | bnk2log:\r |
2fa1a706 L |
513 | or a ;\r |
514 | ret z ; Bank 0 is at physical address 0\r | |
515 | \r | |
516 | push bc ;\r | |
517 | ld b,a ;\r | |
518 | ld c,CA ;\r | |
519 | mlt bc ;\r | |
520 | ld a,c ;\r | |
521 | add a,10h ;\r | |
522 | pop bc ;\r | |
523 | ret ;\r | |
524 | \r | |
525 | ;--------------------------------------------------------------\r | |
a16ba2b0 | 526 | \r |
2fa1a706 L |
527 | ;in hl: Log. Address\r |
528 | ; a: Bank number\r | |
a16ba2b0 L |
529 | ;\r |
530 | ;out ahl: Phys. (linear) Address\r | |
531 | \r | |
532 | \r | |
2fa1a706 | 533 | bnk2phy:\r |
fecee241 | 534 | call bnk2log\r |
a16ba2b0 | 535 | ; fall thru\r |
2fa1a706 | 536 | \r |
a16ba2b0 L |
537 | ;--------------------------------------------------------------\r |
538 | ;\r | |
2fa1a706 | 539 | ; hl: Log. Address\r |
fecee241 | 540 | ; a: Bank base (bbr)\r |
a16ba2b0 | 541 | ;\r |
2fa1a706 L |
542 | ; 2 0 0\r |
543 | ; 0 6 8 0\r | |
544 | ; hl hhhhhhhhllllllll\r | |
545 | ; a + bbbbbbbb\r | |
546 | ;\r | |
547 | ; OP: ahl = (a<<12) + (h<<8) + l\r | |
a16ba2b0 | 548 | ;\r |
4caee1ec | 549 | ;out ahl: Phys. (linear) Address\r |
a16ba2b0 | 550 | \r |
2fa1a706 | 551 | log2phy:\r |
a16ba2b0 | 552 | push bc ;\r |
2fa1a706 | 553 | l2p_i:\r |
a16ba2b0 L |
554 | ld c,a ;\r |
555 | ld b,16 ;\r | |
fecee241 | 556 | mlt bc ; bc = a<<4\r |
2fa1a706 L |
557 | ld a,c ;\r |
558 | add a,h ;\r | |
559 | ld h,a ;\r | |
560 | ld a,b ;\r | |
561 | adc a,0 ;\r | |
fecee241 L |
562 | pop bc ;\r |
563 | ret ;\r | |
564 | \r | |
8df5b655 L |
565 | ;--------------------------------------------------------------\r |
566 | ;\r | |
2fa1a706 L |
567 | ; hl: Log. Address\r |
568 | ;\r | |
8df5b655 L |
569 | ;\r |
570 | ; OP: ahl = (bankbase<<12) + (d<<8) + e\r | |
571 | ;\r | |
572 | ;out ahl: Phys. (linear) Address\r | |
573 | \r | |
574 | \r | |
2fa1a706 | 575 | hwl2phy:\r |
8df5b655 | 576 | push bc ;\r |
2fa1a706 L |
577 | in0 c,(cbar) ;\r |
578 | ld a,h ;\r | |
579 | or 00fh ; log. addr in common1?\r | |
8df5b655 L |
580 | cp c\r |
581 | jr c,hlp_1\r | |
2fa1a706 L |
582 | \r |
583 | in0 a,(cbr) ; yes, cbr is address base\r | |
584 | jr hl2p_x\r | |
8df5b655 | 585 | hlp_1:\r |
2fa1a706 | 586 | ld b,16 ; log. address in baked area?\r |
8df5b655 | 587 | mlt bc\r |
2fa1a706 | 588 | ld a,h\r |
8df5b655 | 589 | cp c\r |
2fa1a706 L |
590 | jr c,hlp_2\r |
591 | in0 a,(bbr) ; yes, bbr is address base\r | |
592 | jr hl2p_x\r | |
593 | hlp_2:\r | |
594 | xor a ; common1\r | |
595 | hl2p_x:\r | |
596 | jr nz,l2p_i\r | |
597 | \r | |
598 | pop bc ; bank part is 0, no translation\r | |
8df5b655 L |
599 | ret ;\r |
600 | \r | |
8df5b655 | 601 | \r |
2fa1a706 L |
602 | \r |
603 | else ;CPU_Z180\r | |
604 | \r | |
8df5b655 L |
605 | ;----------------------------------------------------------------------\r |
606 | ;\r | |
607 | \r | |
2fa1a706 | 608 | bnk2phy:\r |
8df5b655 L |
609 | sla h\r |
610 | jr nc,b2p_1 ;A15=1 --> common\r | |
611 | ld a,3\r | |
612 | b2p_1:\r | |
613 | srl a\r | |
614 | rr h\r | |
615 | ret\r | |
616 | \r | |
fecee241 | 617 | endif\r |
a16ba2b0 L |
618 | \r |
619 | ;--------------------------------------------------------------\r | |
620 | ;\r | |
621 | ;return:\r | |
622 | ; hl = hl + a\r | |
623 | ; Flags undefined\r | |
624 | ;\r | |
625 | \r | |
626 | add_hl_a:\r | |
815c1735 L |
627 | add a,l\r |
628 | ld l,a\r | |
629 | ret nc\r | |
630 | inc h\r | |
631 | ret\r | |
a16ba2b0 L |
632 | \r |
633 | ; ---------------------------------------------------------\r | |
634 | \r | |
635 | sysramw:\r | |
636 | \r | |
637 | .phase isvsw_loc\r | |
638 | topcodsys:\r | |
639 | \r | |
640 | ; Trampoline for interrupt routines in banked ram.\r | |
641 | ; Switch stack pointer to "system" stack in top ram\r | |
642 | ; Save cbar\r | |
815c1735 | 643 | \r |
a16ba2b0 | 644 | isv_sw: ;\r |
2fa1a706 | 645 | ex (sp),hl ;save hl, 'return adr' in hl\r |
a16ba2b0 L |
646 | push de ;\r |
647 | push af ;\r | |
2fa1a706 | 648 | ex de,hl ;'return address' in de\r |
a16ba2b0 L |
649 | ld hl,0 ;\r |
650 | add hl,sp ;\r | |
651 | ld a,h ;\r | |
652 | cp 0f8h ;\r | |
2fa1a706 | 653 | jr nc,isw_1 ;stack allready in top ram\r |
a16ba2b0 L |
654 | ld sp,$stack ;\r |
655 | isw_1:\r | |
2fa1a706 | 656 | push hl ;save user stack pointer\r |
a16ba2b0 L |
657 | in0 h,(cbar) ;\r |
658 | push hl ;\r | |
659 | ld a,SYS$CBAR ;\r | |
660 | out0 (cbar),a ;\r | |
661 | ex de,hl ;\r | |
662 | ld e,(hl) ;\r | |
663 | inc hl ;\r | |
664 | ld d,(hl) ;\r | |
665 | ex de,hl ;\r | |
666 | push bc ;\r | |
667 | call jphl ;\r | |
668 | \r | |
669 | pop bc ;\r | |
670 | pop hl ;\r | |
671 | out0 (cbar),h ;\r | |
672 | pop hl ;\r | |
673 | ld sp,hl ;\r | |
674 | pop af ;\r | |
675 | pop de ;\r | |
676 | pop hl ;\r | |
677 | ei ;\r | |
678 | ret ;\r | |
679 | jphl:\r | |
680 | jp (hl) ;\r | |
681 | \r | |
682 | ; ---------------------------------------------------------\r | |
683 | \r | |
fecee241 | 684 | if CPU_Z180\r |
4caee1ec | 685 | \r |
a16ba2b0 L |
686 | iprt0:\r |
687 | push af\r | |
688 | push hl\r | |
689 | in0 a,(tcr)\r | |
690 | in0 a,(tmdr0l)\r | |
691 | in0 a,(tmdr0h)\r | |
692 | ld a,(tim_ms)\r | |
693 | inc a\r | |
694 | cp 100\r | |
695 | jr nz,iprt_1\r | |
696 | xor a\r | |
697 | ld hl,(tim_s)\r | |
698 | inc hl\r | |
699 | ld (tim_s),hl\r | |
700 | iprt_1:\r | |
701 | ld (tim_ms),a\r | |
702 | pop hl\r | |
703 | pop af\r | |
704 | ei\r | |
705 | ret\r | |
706 | \r | |
fecee241 | 707 | endif\r |
8df5b655 | 708 | \r |
a16ba2b0 L |
709 | ; ---------------------------------------------------------\r |
710 | \r | |
711 | sp.int0:\r | |
712 | ld a,0d0h\r | |
713 | jr sp.i.1\r | |
714 | sp.int.len equ $-sp.int0\r | |
715 | ld a,0d1h\r | |
716 | jr sp.i.1\r | |
717 | ld a,0d2h\r | |
718 | jr sp.i.1\r | |
719 | ld a,0d3h\r | |
720 | jr sp.i.1\r | |
721 | ld a,0d4h\r | |
722 | jr sp.i.1\r | |
723 | ld a,0d5h\r | |
724 | jr sp.i.1\r | |
725 | ld a,0d6h\r | |
726 | jr sp.i.1\r | |
727 | ld a,0d7h\r | |
728 | jr sp.i.1\r | |
729 | ld a,0d8h\r | |
730 | sp.i.1:\r | |
731 | ; out (80h),a\r | |
732 | halt\r | |
733 | \r | |
8df5b655 L |
734 | ; ---------------------------------------------------------\r |
735 | \r | |
fecee241 | 736 | if CPU_Z80\r |
8df5b655 L |
737 | \r |
738 | ; Get IFF2\r | |
739 | ; This routine may not be loaded in page zero\r | |
740 | ;\r | |
741 | ; return Carry clear, if INTs are enabled.\r | |
742 | ;\r | |
743 | global getiff\r | |
744 | getiff:\r | |
745 | xor a ;clear accu and carry\r | |
746 | push af ;stack bottom := 00xxh\r | |
747 | pop af\r | |
748 | ld a,i ;P flag := IFF2\r | |
749 | ret pe ;exit carry clear, if enabled\r | |
750 | dec sp\r | |
751 | dec sp ;has stack bottom been overwritten?\r | |
752 | pop af\r | |
753 | and a ;if not 00xxh, INTs were\r | |
754 | ret nz ;actually enabled\r | |
755 | scf ;Otherwise, they really are disabled\r | |
756 | ret\r | |
757 | \r | |
758 | ;----------------------------------------------------------------------\r | |
759 | \r | |
760 | global selbnk\r | |
761 | \r | |
762 | ; a: bank (0..2)\r | |
763 | \r | |
764 | selbnk:\r | |
765 | push bc\r | |
766 | ld c,a\r | |
767 | call getiff\r | |
768 | push af\r | |
769 | \r | |
770 | ld a,c\r | |
771 | di\r | |
772 | ld (@cbnk),a\r | |
773 | ld a,5\r | |
774 | out (SIOAC),a\r | |
775 | ld a,(mm_sio0)\r | |
776 | rla\r | |
777 | srl c\r | |
778 | rra\r | |
779 | out (SIOAC),a\r | |
780 | ld (mm_sio0),a\r | |
781 | \r | |
782 | ld a,5\r | |
783 | out (SIOBC),a\r | |
784 | ld a,(mm_sio1)\r | |
785 | rla\r | |
786 | srl c\r | |
787 | rra\r | |
788 | out (SIOBC),a\r | |
789 | ld (mm_sio1),a\r | |
790 | pop af\r | |
791 | pop bc\r | |
792 | ret c ;INTs were disabled\r | |
793 | ei\r | |
794 | ret\r | |
795 | \r | |
796 | ;----------------------------------------------------------------------\r | |
797 | \r | |
798 | ; c: bank (0..2)\r | |
799 | \r | |
fecee241 | 800 | if 0\r |
8df5b655 L |
801 | \r |
802 | selbnk:\r | |
803 | ld a,(@cbnk)\r | |
804 | xor c\r | |
805 | and 3\r | |
806 | ret z ;no change\r | |
807 | \r | |
808 | call getiff\r | |
809 | push af\r | |
810 | ld a,c\r | |
811 | di\r | |
812 | ld (@cbnk),a\r | |
813 | ld a,5\r | |
814 | out (SIOAC),a\r | |
815 | ld a,(mm_sio0)\r | |
816 | rla\r | |
817 | srl c\r | |
818 | rra\r | |
819 | out (SIOAC),a\r | |
820 | ld (mm_sio0),a\r | |
821 | \r | |
822 | ld a,5\r | |
823 | out (SIOBC),a\r | |
824 | ld a,(mm_sio1)\r | |
825 | rla\r | |
826 | srl c\r | |
827 | rra\r | |
828 | out (SIOBC),a\r | |
829 | ld (mm_sio1),a\r | |
830 | pop af\r | |
831 | ret nc ;INTs were disabled\r | |
832 | ei\r | |
833 | ret\r | |
834 | \r | |
fecee241 | 835 | endif\r |
8df5b655 L |
836 | \r |
837 | ;----------------------------------------------------------------------\r | |
838 | \r | |
fecee241 | 839 | if 0\r |
8df5b655 L |
840 | ex af,af'\r |
841 | push af\r | |
842 | ex af,af'\r | |
843 | \r | |
844 | rra\r | |
845 | jr nc,stbk1\r | |
846 | ex af,af'\r | |
847 | ld a,5\r | |
848 | out (SIOAC),a\r | |
849 | ld a,(mm_sio0)\r | |
850 | rla\r | |
851 | srl c\r | |
852 | rra\r | |
853 | out (SIOAC),a\r | |
854 | ld (mm_sio1),a\r | |
855 | ex af,af'\r | |
856 | \r | |
857 | stbk1:\r | |
858 | rra\r | |
859 | jr nc,stbk2\r | |
860 | ex af,af'\r | |
861 | ld a,5\r | |
862 | out (SIOBC),a\r | |
863 | ld a,(mm_sio1)\r | |
864 | rla\r | |
865 | srl c\r | |
866 | rra\r | |
867 | out (SIOBC),a\r | |
868 | ld (mm_sio1),a\r | |
869 | ex af,af'\r | |
870 | \r | |
871 | stbk2:\r | |
fecee241 | 872 | endif\r |
8df5b655 L |
873 | \r |
874 | global @cbnk\r | |
875 | global mm_sio0, mm_sio1\r | |
876 | \r | |
877 | @cbnk: db 0 ; current bank (0..2)\r | |
878 | mm_sio0:\r | |
879 | ds 1\r | |
880 | mm_sio1:\r | |
881 | ds 1\r | |
882 | \r | |
883 | \r | |
fecee241 | 884 | endif\r |
8df5b655 L |
885 | \r |
886 | ;----------------------------------------------------------------------\r | |
887 | \r | |
a16ba2b0 L |
888 | curph defl $\r |
889 | .dephase\r | |
890 | sysrame:\r | |
891 | .phase curph\r | |
892 | tim_ms: db 0\r | |
893 | tim_s: dw 0\r | |
894 | .dephase\r | |
815c1735 | 895 | \r |
a16ba2b0 L |
896 | ;-----------------------------------------------------\r |
897 | \r | |
8df5b655 | 898 | \r |
a16ba2b0 L |
899 | cseg\r |
900 | \r | |
901 | ;.phase 0ffc0h\r | |
902 | ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table\r | |
903 | ;.dephase\r | |
904 | \r | |
fecee241 L |
905 | ;.phase 0fffah\r |
906 | mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack\r | |
907 | ;ds 4\r | |
a16ba2b0 L |
908 | ;.dephase\r |
909 | \r | |
910 | \r | |
911 | end\r | |
912 | \r |