switch fifos conin,conout

[z180-stamp.git] / z180 / init.180

	page	255\r
	.z80\r
\r
	extrn ddtz,bpent\r
	extrn $stack\r
	extrn charini,?const,?conin\r
	extrn ?cono,?conos\r
	extrn romend\r
\r
\r
	global	iobyte\r
	global	isv_sw\r
\r
	include config.inc\r
    if CPU_Z180\r
	include	z180reg.inc\r
	include z180.lib\r
    endif\r
\r
\r
\r
\r
;----------------------------------------------------------------------\r
\r
	cseg\r
romstart equ	$\r
\r
	org	romstart+0\r
	jp start\r
\r
iobyte:	db	2\r
\r
; restart vectors\r
\r
rsti	defl	1\r
	rept	7\r
	org	8*rsti + romstart\r
	jp bpent\r
rsti	defl rsti+1\r
	endm\r
\r
;----------------------------------------------------------------------\r
; Config space\r
;\r
\r
	org	romstart+40h\r
\r
	dw	0\r
	db	0\r
\r
\r
    if ROMSYS\r
$crom:	defb c$rom		;\r
    else\r
	db	0		;\r
    endif\r
\r
INIWAITS defl	CWAITIO\r
    if	ROMSYS\r
INIWAITS defl	INIWAITS+CWAITROM\r
    endif\r
\r
;----------------------------------------------------------------------\r
\r
	org	romstart+50h\r
start:\r
	jp	cstart\r
	jp	wstart\r
	jp	?const\r
	jp	?conin\r
	jp	?cono\r
	jp	?conos\r
	jp	charini\r
\r
;----------------------------------------------------------------------\r
\r
hwini0:\r
    if CPU_Z180\r
	db	3		;count\r
	db	rcr,CREFSH	;configure DRAM refresh\r
	db	dcntl,INIWAITS	;wait states\r
	db	cbr,SYS$CBR\r
	db	cbar,SYS$CBAR\r
    endif\r
	db     0\r
\r
    if CPU_Z180\r
dmclrt:				;clear ram per dma\r
	db	dmct_e-dmclrt-2 ;\r
	db	sar0l		;first port\r
	dw	nullbyte	;src (fixed)\r
nullbyte:\r
	db 	000h		;src\r
	dw	romend		;dst (inc), start after "rom" code\r
	db	00h		;dst\r
	dw 	0-romend	;count (64k)\r
dmct_e:\r
	db	0\r
    endif\r
\r
\r
cstart:\r
    if CPU_Z180\r
\r
	push af\r
	in0 a,(itc)		;Illegal opcode trap?\r
	jp m,??st01\r
	ld a,i			;I register == 0 ?\r
	jr z,hw_reset		;    yes, harware reset\r
\r
??st01:\r
	; TODO: SYS$CBR\r
	ld	a,(syscbr)\r
	out0	(cbr),a\r
	pop af			;restore registers\r
	jp bpent		;\r
\r
hw_reset:\r
	di			;0058\r
	ld	a,CREFSH\r
	out0	(rcr),a		;	configure DRAM refresh\r
	ld	a,CWAITIO\r
	out0	(dcntl),a	;	wait states\r
\r
	ld	a,M_NCD		;No Clock Divide\r
	out0	(ccr),a\r
;	ld	a,M_X2CM	;X2 Clock Multiplier\r
;	out0	(cmr),a\r
    else\r
	di\r
	xor	a\r
	ld	(@cbnk),a\r
    endif\r
\r
; check warm start mark\r
\r
	ld ix,mark_55AA		; top of common area\r
	ld a,0aah		;\r
	cp (ix+000h)		;\r
	jr nz,kstart		;\r
	cp (ix+002h)		;\r
	jr nz,kstart		;\r
	cpl			;\r
	cp (ix+001h)		;\r
	jr nz,kstart		;\r
	cp (ix+003h)		;\r
	jr nz,kstart		;\r
	ld sp,$stack		; mark found, check\r
	jp z,wstart		; check ok,\r
\r
; ram not ok, initialize    --  kstart --\r
\r
kstart:\r
    if CPU_Z180\r
	ld	a,SYS$CBR\r
	out0	(cbr),a\r
	ld	a,SYS$CBAR\r
	out0	(cbar),a\r
    endif\r
\r
	ld	sp,$stack	;01e1\r
\r
; Clear RAM using DMA0\r
\r
    if CPU_Z180\r
     if 0\r
\r
	ld	hl,dmclrt	;load DMA registers\r
	call	ioiniml\r
	ld	a,0cbh		;01ef	dst +1, src fixed, burst\r
	out0	(dmode),a	;01f1\r
\r
	ld	b,512/64\r
	ld	a,062h		;01f4	enable dma0,\r
??cl_1:\r
	out0	(dstat),a	;01f9	clear (up to) 64k\r
	djnz	??cl_1		;	end of RAM?\r
\r
     endif\r
    endif\r
\r
	ld	hl,055AAh	;set warm start mark\r
	ld	(mark_55AA),hl\r
	ld	(mark_55AA+2),hl\r
\r
;	--  wstart  --\r
\r
wstart:\r
	call	sysram_init\r
	call	ivtab_init\r
    if CPU_Z180\r
;	call	prt0_init\r
    endif\r
\r
	call	charini\r
	call	bufferinit\r
\r
    if CPU_Z80\r
	ld	a,0\r
	call	selbnk\r
    endif\r
\r
	ld	a,INIDONEVAL	;tell others (CP/M) that hardware and fifos\r
	ld	(INIDONE),a	;    are allready initialized\r
\r
	im 2\r
	ei\r
\r
	call ?const\r
	call ?const\r
	or a\r
	call nz,?conin\r
\r
    if CPU_Z180\r
	ld e,0			;Sys$Bank\r
    else\r
; TODO:\r
    endif\r
	jp ddtz\r
\r
\r
    if CPU_Z180\r
; TODO: SYS$CBR\r
syscbr:	db	0\r
    endif\r
\r
;\r
;----------------------------------------------------------------------\r
;\r
\r
	global	buf.init\r
\r
buf.init:\r
	ld	(ix+o.in_idx),0\r
	ld	(ix+o.out_idx),0\r
	ld	(ix+o.mask),a\r
\r
	ld	a,(ix+o.id)\r
	cp	4\r
	ret	nc\r
\r
	push	de\r
	push	hl\r
	ld	hl,fifo_list\r
	push	hl		;save fifo_list\r
	ld	e,a\r
	ld	d,0\r
	add	hl,de\r
	add	hl,de\r
	add	hl,de\r
	push	ix\r
	pop	de\r
; TODO: address translation\r
	ld	(hl),e\r
	inc	hl\r
	ld	(hl),d\r
	pop	hl		;get fifo_list back\r
	or	a\r
	jr	nz,bufi_ex\r
\r
	ld	(040h),hl\r
	ld	(040h+2),a\r
bufi_ex:\r
	pop	hl\r
	pop	de\r
\r
	ret\r
\r
\r
fifo_list:\r
	rept 4\r
	 dw	0\r
	 db	0\r
	endm\r
\r
;----------------------------------------------------------------------\r
\r
	extrn	msginit,msg.sout\r
	extrn	mtx.fifo,mrx.fifo\r
	extrn	co.fifo,ci.fifo\r
\r
\r
bufferinit:\r
    if CPU_Z180\r
	call	msginit\r
\r
	ld	hl,buffers\r
	ld	b,buftablen\r
bfi_1:\r
	ld	a,(hl)\r
	inc	hl\r
	ld	(bufdat+0),a\r
	ld	e,(hl)\r
	inc	hl\r
	ld	d,(hl)\r
	inc	hl\r
	ex	de,hl\r
\r
	or	a\r
	jr	nz,bfi_2\r
;	call	hwl2phy\r
;	ld	(40h+0),hl\r
;	ld	(40h+2),a\r
	out	(AVRINT5),a\r
	jr	bfi_3\r
bfi_2:\r
	call	hwl2phy\r
	ld	(bufdat+1),hl\r
	ld	(bufdat+3),a\r
	ld	hl,inimsg\r
	call	msg.sout\r
bfi_3:\r
	ex	de,hl\r
	djnz	bfi_1\r
	ret\r
\r
    else ;CPU_Z180\r
\r
	call	msginit\r
\r
	ld	hl,buffers\r
	ld	b,buftablen\r
bfi_1:\r
	ld	a,(hl)\r
	inc	hl\r
	ld	(bufdat+0),a\r
	ld	e,(hl)\r
	inc	hl\r
	ld	d,(hl)\r
	inc	hl\r
	ex	de,hl\r
\r
	or	a\r
	jr	nz,bfi_2\r
\r
	ld	a,(@cbnk)\r
	call	bnk2phy\r
\r
	ld	(40h+0),hl\r
	ld	(40h+2),a\r
	out	(AVRINT5),a\r
	jr	bfi_3\r
bfi_2:\r
\r
	ld	a,(@cbnk)\r
	call	bnk2phy\r
\r
	ld	(bufdat+1),hl\r
	ld	(bufdat+3),a\r
	ld	hl,inimsg\r
	call	msg.sout\r
bfi_3:\r
	ex	de,hl\r
	djnz	bfi_1\r
	ret\r
    endif\r
\r
buffers:\r
	db	0\r
	dw	mtx.fifo\r
	db	1\r
	dw	mrx.fifo\r
	db	2\r
	dw	ci.fifo\r
	db	3\r
	dw	co.fifo\r
buftablen equ	($ - buffers)/3\r
\r
inimsg:\r
	db	inimsg_e - $ -1\r
	db	0AEh\r
	db	inimsg_e - $ -1\r
	db	0\r
bufdat:\r
	db	0\r
	dw	0\r
	db	0\r
inimsg_e:\r
\r
\r
;\r
;----------------------------------------------------------------------\r
;\r
\r
sysram_init:\r
	ld hl,sysramw\r
	ld de,topcodsys\r
	ld bc,sysrame-sysramw\r
	ldir\r
\r
	ret\r
\r
;----------------------------------------------------------------------\r
\r
ivtab_init:\r
	ld	hl,ivtab	;\r
	ld	a,h		;\r
	ld	i,a		;\r
    if CPU_Z180\r
	out0	(il),l		;\r
    endif\r
\r
; Let all vectors point to spurious int routines.\r
\r
	ld	d,high sp.int0\r
	ld	a,low  sp.int0\r
	ld	b,9\r
ivt_i1:\r
	ld	(hl),a\r
	inc	l\r
	ld	(hl),d\r
	inc	l\r
	add	a,sp.int.len\r
	djnz	ivt_i1\r
	ret\r
\r
;----------------------------------------------------------------------\r
\r
    if CPU_Z180\r
prt0_init:\r
	ld	a,i\r
	ld	h,a\r
	in0	a,(il)\r
	and	0E0h\r
	or	IV$PRT0\r
	ld	l,a\r
	ld	(hl),low  iprt0\r
	inc	hl\r
	ld	(hl),high iprt0\r
	ld	hl,prt0itab\r
	call	ioiniml\r
	ret\r
\r
prt0itab:\r
	db	prt0it_e-prt0itab-2\r
	db	tmdr0l\r
	dw	PRT_TC10MS\r
	dw	PRT_TC10MS\r
	db	M_TIE0+M_TDE0	;enable timer 0 interrupt and down count.\r
prt0it_e:\r
	db	0\r
    endif\r
\r
\r
;\r
;----------------------------------------------------------------------\r
;\r
\r
    if CPU_Z180\r
io.ini:\r
     if 0\r
	push	bc\r
	ld	b,0		;high byte port adress\r
ioi_nxt:\r
	ld	a,(hl)		;count\r
	inc	hl\r
	or	a\r
	jr	z,ioi_e\r
\r
	ld	c,(hl)		;port address\r
	inc	hl\r
ioi_r:\r
	outi\r
	inc	b		;outi decrements b\r
	dec	a\r
	jr	nz,ioi_r\r
	jr	ioi_nxt\r
ioi_e:\r
	pop	bc\r
	ret\r
\r
     else ;(if 1/0)\r
\r
	push	bc\r
	jr	ioi_nxt\r
ioi_l:\r
	ld	c,(hl)		;port address\r
	inc	hl\r
	inc	c\r
ioi_r:\r
	dec	c		;otim increments c\r
	otim\r
	jr	z,ioi_r\r
ioi_nxt:\r
	ld	b,(hl)		;count\r
	inc	hl\r
	inc	b		;stop if count == 0\r
	djnz	ioi_l\r
	pop	bc\r
	ret\r
\r
     endif ;(1/0)\r
\r
    else\r
\r
io.ini:\r
	push	bc\r
	jr	ioi_nxt\r
ioi_l:\r
	ld	c,(hl)		;port address\r
	inc	hl\r
	otir\r
ioi_nxt:\r
	ld	b,(hl)		;count\r
	inc	hl\r
	inc	b\r
	djnz	ioi_l\r
    endif\r
	pop	bc\r
	ret\r
\r
;----------------------------------------------------------------------\r
\r
    if CPU_Z180\r
\r
	global ioiniml\r
\r
ioiniml:\r
	push	bc\r
	xor	a\r
ioml_lp:\r
	ld	b,(hl)\r
	inc	hl\r
	cp	b\r
	jr	z,ioml_e\r
\r
	ld	c,(hl)\r
	inc	hl\r
	otimr\r
	jr	ioml_lp\r
ioml_e:\r
	pop	bc\r
	ret	z\r
    endif\r
\r
io.ini.l:\r
;\r
\r
\r
\r
;----------------------------------------------------------------------\r
;\r
    if CPU_Z180\r
\r
;--------------------------------------------------------------------\r
; Return the BBR value for the given bank number\r
;\r
; in  a: Bank number\r
; out a: bbr value\r
\r
bnk2log:\r
	or	a		;\r
	ret	z		; Bank 0 is at physical address 0\r
\r
	push	bc		;\r
	ld	b,a		;\r
	ld	c,CA		;\r
	mlt	bc		;\r
	ld	a,c		;\r
	add	a,10h		;\r
	pop	bc		;\r
	ret			;\r
\r
;--------------------------------------------------------------\r
\r
;in  hl: Log. Address\r
;     a: Bank number\r
;\r
;out ahl: Phys. (linear) Address\r
\r
\r
bnk2phy:\r
	call	bnk2log\r
	; fall thru\r
\r
;--------------------------------------------------------------\r
;\r
; hl: Log. Address\r
;  a: Bank base (bbr)\r
;\r
;	     2           0       0\r
;	     0   6       8       0\r
; hl	          hhhhhhhhllllllll\r
;  a	+     bbbbbbbb\r
;\r
; OP: ahl = (a<<12) + (h<<8) + l\r
;\r
;out ahl: Phys. (linear) Address\r
\r
log2phy:\r
	push	bc		;\r
l2p_i:\r
	ld	c,a		;\r
	ld	b,16		;\r
	mlt	bc		; bc = a<<4\r
	ld	a,c		;\r
	add	a,h		;\r
	ld	h,a		;\r
	ld	a,b		;\r
	adc	a,0		;\r
	pop	bc		;\r
	ret			;\r
\r
;--------------------------------------------------------------\r
;\r
; hl: Log. Address\r
;\r
;\r
; OP: ahl = (bankbase<<12) + (d<<8) + e\r
;\r
;out ahl: Phys. (linear) Address\r
\r
\r
hwl2phy:\r
	push	bc		;\r
	in0	c,(cbar)	;\r
	ld	a,h		;\r
	or	00fh		; log. addr in common1?\r
	cp	c\r
	jr	c,hlp_1\r
\r
	in0	a,(cbr)		; yes, cbr is address base\r
	jr	hl2p_x\r
hlp_1:\r
	ld	b,16		; log. address in baked area?\r
	mlt	bc\r
	ld	a,h\r
	cp	c\r
	jr	c,hlp_2\r
	in0	a,(bbr)		; yes, bbr is address base\r
	jr	hl2p_x\r
hlp_2:\r
	xor	a		; common1\r
hl2p_x:\r
	jr	nz,l2p_i\r
\r
	pop	bc		; bank part is 0, no translation\r
	ret			;\r
\r
\r
\r
    else	;CPU_Z180\r
\r
;----------------------------------------------------------------------\r
;\r
\r
bnk2phy:\r
	sla	h\r
	jr	nc,b2p_1		;A15=1 --> common\r
	ld	a,3\r
b2p_1:\r
	srl	a\r
	rr	h\r
	ret\r
\r
    endif\r
\r
;--------------------------------------------------------------\r
;\r
;return:\r
; hl = hl + a\r
; Flags undefined\r
;\r
\r
add_hl_a:\r
	add a,l\r
	ld l,a\r
	ret nc\r
	inc h\r
	ret\r
\r
; ---------------------------------------------------------\r
\r
sysramw:\r
\r
	.phase isvsw_loc\r
topcodsys:\r
\r
; Trampoline for interrupt routines in banked ram.\r
; Switch stack pointer to "system" stack in top ram\r
; Save cbar\r
\r
isv_sw:				;\r
	ex (sp),hl		;save hl, 'return adr' in hl\r
	push de			;\r
	push af			;\r
	ex de,hl		;'return address' in de\r
	ld hl,0			;\r
	add hl,sp		;\r
	ld a,h			;\r
	cp 0f8h			;\r
	jr nc,isw_1		;stack allready in top ram\r
	ld sp,$stack		;\r
isw_1:\r
	push hl			;save user stack pointer\r
	in0 h,(cbar)		;\r
	push hl			;\r
	ld a,SYS$CBAR		;\r
	out0 (cbar),a		;\r
	ex de,hl		;\r
	ld e,(hl)		;\r
	inc hl			;\r
	ld d,(hl)		;\r
	ex de,hl		;\r
	push bc			;\r
	call jphl		;\r
\r
	pop bc			;\r
	pop hl			;\r
	out0 (cbar),h		;\r
	pop hl			;\r
	ld sp,hl		;\r
	pop af			;\r
	pop de			;\r
	pop hl			;\r
	ei			;\r
	ret			;\r
jphl:\r
	jp (hl)			;\r
\r
; ---------------------------------------------------------\r
\r
    if CPU_Z180\r
\r
iprt0:\r
	push	af\r
	push	hl\r
	in0	a,(tcr)\r
	in0	a,(tmdr0l)\r
	in0	a,(tmdr0h)\r
	ld	a,(tim_ms)\r
	inc	a\r
	cp	100\r
	jr	nz,iprt_1\r
	xor	a\r
	ld	hl,(tim_s)\r
	inc	hl\r
	ld	(tim_s),hl\r
iprt_1:\r
	ld	(tim_ms),a\r
	pop	hl\r
	pop	af\r
	ei\r
	ret\r
\r
    endif\r
\r
; ---------------------------------------------------------\r
\r
sp.int0:\r
	ld	a,0d0h\r
	jr	sp.i.1\r
sp.int.len equ	$-sp.int0\r
	ld	a,0d1h\r
	jr	sp.i.1\r
	ld	a,0d2h\r
	jr	sp.i.1\r
	ld	a,0d3h\r
	jr	sp.i.1\r
	ld	a,0d4h\r
	jr	sp.i.1\r
	ld	a,0d5h\r
	jr	sp.i.1\r
	ld	a,0d6h\r
	jr	sp.i.1\r
	ld	a,0d7h\r
	jr	sp.i.1\r
	ld	a,0d8h\r
sp.i.1:\r
;	out	(80h),a\r
	halt\r
\r
; ---------------------------------------------------------\r
\r
    if CPU_Z80\r
\r
; Get IFF2\r
; This routine may not be loaded in page zero\r
;\r
; return Carry clear, if INTs are enabled.\r
;\r
	global getiff\r
getiff:\r
	xor	a		;clear accu and carry\r
	push	af		;stack bottom := 00xxh\r
	pop	af\r
	ld	a,i		;P flag := IFF2\r
	ret	pe		;exit carry clear, if enabled\r
	dec	sp\r
	dec	sp		;has stack bottom been overwritten?\r
	pop	af\r
	and	a		;if not 00xxh, INTs were\r
	ret	nz		;actually enabled\r
	scf			;Otherwise, they really are disabled\r
	ret\r
\r
;----------------------------------------------------------------------\r
\r
	global	selbnk\r
\r
; a: bank (0..2)\r
\r
selbnk:\r
	push	bc\r
	ld	c,a\r
	call	getiff\r
	push	af\r
\r
	ld	a,c\r
	di\r
	ld	(@cbnk),a\r
	ld	a,5\r
	out	(SIOAC),a\r
	ld	a,(mm_sio0)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOAC),a\r
	ld	(mm_sio0),a\r
\r
	ld	a,5\r
	out	(SIOBC),a\r
	ld	a,(mm_sio1)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOBC),a\r
	ld	(mm_sio1),a\r
	pop	af\r
	pop	bc\r
	ret	c			;INTs were disabled\r
	ei\r
	ret\r
\r
;----------------------------------------------------------------------\r
\r
; c: bank (0..2)\r
\r
    if 0\r
\r
selbnk:\r
	ld	a,(@cbnk)\r
	xor	c\r
	and	3\r
	ret	z		;no change\r
\r
	call	getiff\r
	push	af\r
	ld	a,c\r
	di\r
	ld	(@cbnk),a\r
	ld	a,5\r
	out	(SIOAC),a\r
	ld	a,(mm_sio0)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOAC),a\r
	ld	(mm_sio0),a\r
\r
	ld	a,5\r
	out	(SIOBC),a\r
	ld	a,(mm_sio1)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOBC),a\r
	ld	(mm_sio1),a\r
	pop	af\r
	ret	nc			;INTs were disabled\r
	ei\r
	ret\r
\r
    endif\r
\r
;----------------------------------------------------------------------\r
\r
    if 0\r
	ex	af,af'\r
	push	af\r
	ex	af,af'\r
\r
	rra\r
	jr	nc,stbk1\r
	ex	af,af'\r
	ld	a,5\r
	out	(SIOAC),a\r
	ld	a,(mm_sio0)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOAC),a\r
	ld	(mm_sio1),a\r
	ex	af,af'\r
\r
stbk1:\r
	rra\r
	jr	nc,stbk2\r
	ex	af,af'\r
	ld	a,5\r
	out	(SIOBC),a\r
	ld	a,(mm_sio1)\r
	rla\r
	srl	c\r
	rra\r
	out	(SIOBC),a\r
	ld	(mm_sio1),a\r
	ex	af,af'\r
\r
stbk2:\r
    endif\r
\r
	global	@cbnk\r
	global	mm_sio0, mm_sio1\r
\r
@cbnk:	db	0		; current bank (0..2)\r
mm_sio0:\r
	ds	1\r
mm_sio1:\r
	ds	1\r
\r
\r
    endif\r
\r
;----------------------------------------------------------------------\r
\r
curph	defl	$\r
	.dephase\r
sysrame:\r
	.phase curph\r
tim_ms:	db	0\r
tim_s:	dw	0\r
	.dephase\r
\r
;-----------------------------------------------------\r
\r
\r
	cseg\r
\r
	;.phase	0ffc0h\r
;ivtab	equ	0ffc0h		; 0ffc0h	;int vector table\r
	;.dephase\r
\r
	;.phase	0fffah\r
mark_55AA equ 0 - 2 - 4		;2 byte for trap stack\r
	;ds	4\r
	;.dephase\r
\r
\r
	end\r